IDT70V05L20GI

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM Features x x IDT70V05S/L x x True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25/35/55ns (max.) Low-power operation – IDT70V05S Active: 400mW (typ.) Standby: 3.3mW (typ.) – IDT70V05L Active: 380mW (typ.) Standby: 660µW (typ.) IDT70V05 easily expands data bus width to 16 bits or more x x x x x x x x using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 3.3V (±0.3V) power supply Available in 68-pin PGA and PLCC, and a 64-pin TQFP Industrial temperature range (-40°C to +85°C) is available for selected speeds Functional Block Diagram OEL R/WL OER CER R/WR CEL I/O0L- I/O7L I/O Control I/O Control I/O0R-I/O7R BUSYL(1,2) A12L A0L Address Decoder 13 BUSYR(1,2) MEMORY ARRAY 13 Address Decoder A12R A0R CEL OEL R/WL SEML INTL(2) NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. ARBITRATION INTERRUPT SEMAPHORE LOGIC CER OER R/WR M/S SEMR INTR(2) 2941 drw 01 MARCH 2000 1 ©2000 Integrated Device Technology, Inc. DSC 2941/6 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bitor-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM approach in 16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 400mW of power. The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC and a 64-pin thin quad flatpack (TQFP). Pin Configurations(1,2,3) INDEX I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I/O1L I/O0L N/C OE L R/W L SEML CE L N/C N/C VCC A12L A11L A10L A9L A8L A7L A6L 987 6543 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 IDT70V05J J68-1(4) 68-Pin PLCC Top View(5) 55 54 53 52 51 50 49 48 47 46 45 25 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A5L A4L A3L A2L A1L A0L INT L BUSY L GND M/S BUSY R INTR A0R A1R A2R A3R A4R 2941 drw 02 , I/O7R N/C OE R R/WR SEM R CE R N/C N/C GND A12R A11R A10R A9R A8R A7R A6R A5R SEML CEL R/WL I/O1L I/O0L INDEX 59 58 57 54 53 52 64 63 62 61 60 56 55 51 50 49 N/C VCC A12L A11L A10L A9L A8L A7L A6L A5L OEL NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J68-1 package body is approximately .95 in x .95 in x .17 in. PN64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate oriention of the actual part-marking 20 21 22 26 27 28 29 30 31 17 18 19 23 24 25 32 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 A4L A3L A2L A1L A0L 70V05PF PN-64(4) 64-Pin TQFP Top View(5) INTL BUSYL GND M/S , BUSYR INTR A0R A1R A2R A3R A4R 2941 drw 03 6.42 2 SEMR CER I/O6R I/O7R R/WR N/C GND A12R A11R A10R A9R A8R A7R A6R A5R OER IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't.) 51 11 53 A7L 55 A9L A5L 52 A6L 54 A8L 50 A4L 49 A3L 48 A2L 47 A1L 46 44 42 40 38 A0L BUSYL M/S INTR A1R 45 36 A3R 35 A4R 32 A7R 30 A9R 28 A11R 26 GND 24 N/C 34 A5R 33 A6R 31 A8R 29 A10R 27 A12R 25 N/C 23 10 INTL GND BUSYR A0R 43 41 39 37 A2R 09 08 07 56 57 A11L A10L 58 59 VCC A12L 60 61 N/C N/C 63 62 IDT70V05G G68-1(4) 68-Pin PGA Top View(5) 06 05 SEML 65 CEL 64 R/WL 04 03 02 OEL SEMR 20 22 CER 67 66 I/O0L N/C 1 3 68 I/O1L I/O2L I/O4L 2 4 I/O3L I/O5L B C 5 7 9 11 13 15 GND I/O7L GND I/O1R VCC I/O4R 6 I/O6L D 8 10 12 14 16 VCC I/O0R I/O2R I/O3R I/O5R E F G H J OER 21 R/WR 18 19 I/O7R N/C 17 I/O6R K L 2941 drw 04 , 01 A INDEX NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 1.18 in x 1.18 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate oriention of the actual part-marking. Pin Names Left Port Right Port Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground 2941 tbl 01 CEL R/ WL CER R/ WR OEL A 0L - A12L I/O0L - I/O7L OER A0R - A12R I/O0R - I/O7R SEML INTL BUSYL SEMR INTR BUSYR M/ S V CC GND 6.42 3 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table: Non-Contention Read/Write Control Inputs(1) Outputs CE H L L X R/W X L H X OE X X L H SEM H H H X I/O0-7 High-Z DATAIN DATAOUT High-Z Deselected: Power-Down Write to Memory Read Memory Outputs Disabled Mode NOTE: 1. A0L — A12L≠ A0R — A 12R 2941 tbl 02 Truth Table II: Semaphore Read/Write Control(1) Inputs(1) Outputs CE H H L R/W H ↑ X OE L X X SEM L L L I/O0-7 DATAOUT DATAIN ____ Mode Read Data in Semaphore Flag Write I/O0 into Semaphore Flag Not Allowed 2941 tbl 03 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from I/O0 -I/O 7. These eight semaphores are addressed by A0-A2. 6.42 4 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 Unit V Maximum Operating Temperature and Supply Voltage(1) Grade Commercial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 3.3V + 0.3V 3.3V + 0.3V 2941 tbl 05 TBIAS TSTG IOUT -55 to +125 -55 to +125 50 o C C Industrial o NOTE: 1. This is the parameter TA. mA 2941 tbl 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.3V. Recommended DC Operating Conditions Symbol VCC GND VIH Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.5 (1) Typ. 3.3 0 ____ Max. 3.6 0 VCC+0.3 0.8 (2) Unit V V V V 2941 tbl 06 Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 3dV V OUT = 3dV Max. 9 10 Unit pF pF 2941 tbl 07 VIL ____ NOTES: 1. VIL> -1.5V for pulse width less than 10ns. 2. VTERM must not exceed VCC +0.3V. NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitznce when the input and output signals switch from 0V to 3V or from 3V to 0V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V) 70V05S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current (1) 70V05L Min. ___ ___ ___ Test Conditions VCC = 3.6V, VIN = 0V to VCC VOUT = 0V to V CC IOL = + 4mA IOH = -4mA Min. ___ ___ ___ Max. 10 10 0.4 ___ Max. 5 5 0.4 ___ Unit µA µA V V 2941 tbl 08 Output Leakage Current Output Low Voltage Output High Voltage 2.4 2.4 NOTE: 1. At VCC < 2.0V input leakages are undefined. 6.42 5 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V) 70V05X15 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ.(2) 150 140 ____ ____ 70V05X20 Com'l & Ind Typ.(2) 140 130 140 130 20 15 20 15 80 75 80 75 1.0 0.2 1.0 0.2 80 75 80 75 Max. 200 175 225 195 30 25 45 40 110 100 130 115 5 2.5 15 5 115 100 130 115 70V05X25 Com'l & Ind Typ. (2) 130 125 130 125 16 13 16 13 75 72 75 72 1.0 0.2 1.0 0.2 75 70 75 70 Max. 190 165 210 180 30 25 45 40 110 95 125 110 5 2.5 15 5 105 90 120 105 Unit mA mA mA mA mA mA mA mA mA mA Max. 215 185 ____ ____ CE = VIL, Outputs Open SEM = VIH f = fMAX(3) ISB1 Standby Current (Both Ports - TTL Level Inputs) CER = C EL = VIH SEMR = SEML = VIH f = fMAX(3) 25 20 ____ ____ 35 30 ____ ____ ISB2 Standby Current (One Port - TTL Level Inputs) CEL or C ER = VIH Active Port Outputs Open, f=fMAX(3) 85 80 ____ ____ 120 110 ____ ____ ISB3 Full Standby Current (Both Ports CMOS Level Inputs) Both Ports C EL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V One Port C EL o r CER > VCC - 0.2V SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Open, f = fMAX(3) 1.0 0.2 ____ ____ 5 2.5 ____ ____ ISB4 Full Standby Current (One Port CMOS Level Inputs) 85 80 ____ ____ 125 105 ____ ____ 2941 tbl 09a 70V05X35 Com'l & Ind Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ.(2) 120 115 120 115 13 11 13 11 70 65 70 65 1.0 0.2 1.0 0.2 65 60 65 60 Max. 180 155 200 170 25 20 40 35 100 90 120 105 5 2.5 15 5 100 85 115 100 70V05X55 Com'l & Ind Typ. (2) 120 115 120 115 13 11 13 11 70 65 70 65 1.0 0.2 1.0 0.2 65 60 65 60 Max. 180 155 200 170 25 20 40 35 100 90 120 105 5 2.5 15 5 100 85 115 100 Unit mA mA mA mA mA mA mA mA mA mA CE = VIL, Outputs Open SEM = VIH f = fMAX(3) ISB1 Standby Current (Both Ports - TTL Level Inputs) CER = C EL = VIH SEMR = S EML = VIH f = fMAX(3) ISB2 Standby Current (One Port - TTL Level Inputs) CEL or C ER = VIH Active Port Outputs Open, f=fMAX(3) ISB3 Full Standby Current (Both Ports CMOS Level Inputs) Both Ports C EL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = S EML > VCC - 0.2V One Port C EL o r CER > VCC - 0.2V SEMR = S EML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Open, f = fMAX(3) ISB4 Full Standby Current (One Port CMOS Level Inputs) NOTES: 1. “X” in part number indicates power rating (S or L) 2. VCC = 3.3V, TA = +25°C. 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 2941 tbl 09b 6.42 6 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 3.3V 3.3V 590Ω DATAOUT 590Ω DATAOUT 435Ω 30pF 435Ω 5pF* AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1 and 2 2941 tbl 10 BUSY INT 2941 drw 05 Figure 1. AC Output Test Load Figure 2. Output Test Load *Including scope and jig. (For tLZ, tHZ, tWZ, tOW) Timing of Power-Up Power-Down CE ICC ISB tPU 50% tPD 50% 2941 drw 06 , 6.42 7 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 70V05X15 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time(3) Output Enable Access Time (3) Output Hold from Address Change Output Low-Z Time (1,2) 70V05X20 Com'l & Ind Min. Max. 70V05X25 Com'l & Ind Min. Max. Unit Parameter Min. Max. 15 ____ ____ 20 ____ ____ 25 ____ ____ ns ns ns ns ns ns ns ns ns ns ns 2941 tbl 11a 15 15 10 ____ 20 20 12 ____ 25 25 13 ____ ____ ____ ____ ____ ____ ____ 3 3 ____ 3 3 ____ 3 3 ____ ____ ____ ____ Output High-Z Time(1,2) Chip Enable to Power Up Time (1,2) Chip Disable to Power Down Time (1,2) Semaphore Flag Update Pulse (OE or S EM) Semaphore Address Access(3) 10 ____ 12 ____ 15 ____ 0 ____ 0 ____ 0 ____ 15 ____ 20 ____ 25 ____ 10 ____ 10 ____ 10 ____ 15 20 25 70V05X35 Com'l & Ind Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time(3) Output Enable Access Time (3) 70V05X55 Com'l & Ind Min. Max. Unit Parameter Min. Max. 35 ____ ____ ____ ____ 55 ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns 2941 tbl 11b 35 35 20 ____ ____ 55 55 30 ____ ____ Output Hold from Address Change Output Low-Z Time (1,2) 3 3 ____ 3 3 ____ Output High-Z Time(1,2) Chip Enable to Power Up Time (1,2) Chip Disable to Power Down Time (1,2) 15 ____ 25 ____ 0 ____ 0 ____ 35 ____ 50 ____ Semaphore Flag Update Pulse (OE or S EM) Semaphore Address Access(3) 15 ____ 15 ____ 35 55 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is determined by device characterization but is not production tested. 3. To access SRAM, CE = VIL, SEM = VIH. 4. 'X' in part number indicates power rating (S or L). 6.42 8 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Read Cycles(5) tRC ADDR tAA (4) tACE tAOE (4) (4) CE OE R/W tLZ DATAOUT (1) tOH VALID DATA (4) (2) tHZ BUSYOUT tBDD (3,4) 2941 drw 07 NOTES: 1. Timing depends on which signal is asserted last, OE or CE . 2. Timing depends on which signal is de-asserted first CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, t AA or tBDD . 5. SEM = VIH. 6.42 9 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 70V05X15 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write (3) 70V05X20 Com'l & Ind Min. Max. 70V05X25 Com'l & Ind Min. Max. Unit Parameter Min. Max. 15 12 12 0 12 0 10 ____ ____ ____ 20 15 15 0 15 0 15 ____ ____ ____ 25 20 20 0 20 0 15 ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns ns 2941 tbl 12a Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (4) (1,2) (1,2) (3) ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 10 ____ 12 ____ 15 ____ 0 ____ 0 ____ 0 ____ Write Enable to Output in High-Z 10 ____ 12 ____ 15 ____ Output Active from End-of-Write (1,2,4) SEM Flag Write to Read Time SEM Flag Contention Window 0 5 5 0 5 5 0 5 5 ____ ____ ____ ____ ____ ____ 70V05X35 Com'l & Ind Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write (3) 70V05X55 Com'l & Ind Min. Max. Unit Parameter Min. Max. 35 30 30 0 25 0 15 ____ ____ 55 45 45 0 40 0 30 ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns ns 2941 tbl 12b ____ ____ ____ ____ ____ ____ Address Valid to End-of-Write Address Set-up Time (3) Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (4) (1,2) (1,2) ____ ____ ____ ____ ____ ____ 15 ____ 25 ____ 0 ____ 0 ____ Write Enable to Output in High-Z Output Active from End-of-Write SEM Flag Write to Read Time SEM Flag Contention Window 15 ____ 25 ____ (1,2,4) 0 5 5 0 5 5 ____ ____ ____ ____ NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is determined by device characterization but is not production tested. 3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. “X” in part number indicates power rating (S or L). 610 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM (9) tAS (6) R/W tWZ (7) DATAOUT (4) tWP (2) tWR (3) tOW (4) tDW DATAIN tDH 2941 drw 08 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8) tWC ADDRESS tAW CE or SEM R/W (9) (6) (2) tAS tEW tWR (3) tDW DATAIN tDH 2941 drw 09 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or t WP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE, or R/W. 7. Timing depends on which enable signal is de-asserted first, CE, or R/W. 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIN. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 611 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS tAW SEM tEW tDW DATA0 R/W tAS tWP DATAIN VALID tDH tSOP DATA OUT VALID(2) tWR VALID ADDRESS tACE tOH tSWRD OE Write Cycle tAOE tSOP Read Cycle 2941 drw 10 NOTE: 1. CE = V IH for the duration of the above timing (both write and read cycle). 2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" MATCH SIDE (2) "A" R/W"A" SEM"A" tSPS A0"B"-A2"B" MATCH SIDE (2) "B" R/W"B" SEM"B" 2941 drw 11 NOTES: 1. DOR = D OL = VIL, CER = CE L = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. “A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. 612 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 70V05X15 Com'l Ony Symbol BUSY TIMING (M/S = VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Enable LOW BUSY Dis able Time from Chip Enable HIGH Arbitration Priority Set-up Time BUSY Disable to Valid Data Write Hold After B USY (5) (3) (2) ____ 70V05X20 Com'l & Ind Min. Max. 70V05X25 Com'l & Ind Min. Max. Unit Parameter Min. Max. 15 15 15 15 ____ ____ 20 20 20 17 ____ ____ 20 20 20 17 ____ ns ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ ____ ____ ____ 5 ____ 5 ____ 5 ____ 18 ____ 30 ____ 30 ____ 12 15 17 BUSY TIMING (M/S = VIL) tWB tWH BUSY Input to Write (4) Write Hold After B USY(5) 0 12 ____ 0 15 ____ 0 17 ____ ns ns ____ ____ ____ PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) ____ ____ 30 25 ____ ____ 45 35 ____ ____ 50 35 ns ns 2941 tbl 13a 70V05X35 Com'l & Ind Symbol BUSY TIMING (M/S = VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Ac cess Time from Chip Enable LOW BUSY Disable Time from Chip Enable HIGH Arbitration Priority Set-up Time (2) BUSY Disable to Valid Data(3) Write Hold After B USY(5) ____ 70V05X55 Com'l & Ind Min. Max. Unit Parameter Min. Max. 20 20 20 20 ____ ____ 45 40 40 35 ____ ns ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ 5 ____ 5 ____ 35 ____ 40 ____ 25 25 BUSY TIMING (M/S = VIL) tWB tWH BUSY Input to Write(4) Write Hold After B USY (5) 0 25 ____ 0 25 ____ ns ns ____ ____ PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) ____ ____ 60 45 ____ ____ 80 65 ns ns 2941 tbl 13b NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to “Timing Waveform of Read With BUSY (M/S = VIH)” or “Timing Waveform of Write With PortTo-Port Delay (M/S = VIL)”. 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – t WP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 6. 'X' is part number indicates power rating (S or L). 613 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read with BUSY(2,4,5) (M/S=VIH) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS ADDR"B" tBAA (1) tDH VALID MATCH tBDA tBDD BUSY"B" tWDD DATAOUT "B" tDDD (3) 2941 drw 12 VALID NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (SLAVE) then BUSY is input. For this example, BUSY “A” = V IH and BUSY“B” input is shown above. 5. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the port opposite from Port “A”. 614 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with BUSY tWP R/W"A" tWB(3) BUSY"B" tWH (1) R/W"B" (2) 2941 drw 13 , NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on port “B” Blocking R/W“B”, until BUSY “B” goes HIGH. 3. tWB is only for the slave version. Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE "A" tAPS CE "B" tBAC BUSY "B" 2941 drw 14 (2) tBDC Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDR"A" tAPS ADDR"B" tBAA (2) ADDRESS "N" MATCHING ADDRESS "N" tBDA BUSY"B" 2941 drw 15 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 615 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 70V05X15 Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 ____ ____ 70V05X20 Com'l & Ind Min. Max. 70V05X25 Com'l & Ind Min. Max. Unit Parameter Min. Max. 0 0 ____ ____ 0 0 ____ ____ ns ns ns ns 2941 tbl 14a ____ ____ ____ 15 15 20 20 20 20 ____ ____ ____ 70V05X35 Com'l & Ind Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 ____ ____ ____ ____ 70V05X55 Com'l & Ind Min. Max. Unit Parameter Min. Max. 0 0 ____ ____ ____ ____ ns ns ns ns 2941 tbl 14b 25 25 40 40 NOTES: 1. 'X' in part number indicates power rating (S or L). 616 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1) tWC ADDR"A" tAS (3) (2) (4) INTERRUPT SET ADDRESS tWR CE"A" R/W"A" tINS (3) INT"B" 2941 drw 16 tRC ADDR"B" tAS (3) INTERRUPT CLEAR ADDRESS (2) CE"B" OE"B" tINR (3) INT"B" 2941 drw 17 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Truth Table III. 3. Timing depends on which enable signal (CE or R/ W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 617 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table III — Interrupt Flag(1) Left Port R/WL L X X X Right Port A12L-A0L 1FFF X X 1FFE CEL L X X L OEL X X X L INTL X X L (3) (2) R/WR X X L X CER X L L X OER X L X X A12R-A0R X 1FFF 1FFE X INTR L(2) H X X (3) Function Set Right I NTR Flag Reset Right I NTR Flag Set Left I NTL Flag Reset Left I NTL Flag 2941tbl 15 H NOTES: 1. Assumes BUSYL = BUSY R = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. Truth Table IV — Address BUSY Arbitration Inputs Outputs A12L-A0L A12R-A0R NO MATCH MATCH MATCH MATCH CEL X H X L CER X X H L BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3) 2941 tbl 16 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V05 are push pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. VIL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D7 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D7 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free 2941 tbl 17 Status NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. 618 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges CE MASTER Dual Port SRAM BUSY (L) BUSY (R) CE SLAVE Dual Port SRAM BUSY (L) BUSY (R) BUSY (L) MASTER CE Dual Port SRAM BUSY (L) BUSY (R) SLAVE CE Dual Port SRAM BUSY (L) BUSY (R) BUSY (R) 2941 drw 18 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs. Functional Description The IDT70V05 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V05 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. The BUSY outputs on the IDT 70V05 SRAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these SRAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is set when the right port writes to memory location 1FFE (HEX). The left port clears the interrupt by reading address location 1FFE. Likewise, the right port interrupt flag (INTR) is set when the left port writes to memory location 1FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 1FFF. The message (8 bits) at 1FFE or 1FFF is user-defined. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT70V05 SRAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT70V05 SRAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Busy Logic Busy Logic provides a hardware indication that both ports of the SRAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the SRAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. Semaphores The IDT70V05 is a fast Dual-Port 8K x 8 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the DualPort SRAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port SRAM or any other shared resource. The Dual-Port SRAM features a fast access time, and both ports are 619 .42 DECODER IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or accessed, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port SRAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port SRAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table II where CE and SEM are both HIGH. Systems which can best use the IDT70V05 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V05's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V05 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V05 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. 620 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V05’s Dual-Port SRAM. Say the 8K x 8 SRAM was to be divided into two 4K x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K of Dual-Port SRAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 4K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 4K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 4K blocks of Dual-Port SRAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port SRAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned SRAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D Q R PORT SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ SEMAPHORE READ 2941 drw 19 , Figure 4. IDT70V05 Semaphore Logic 621 .42 IDT70V05S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Blank I PF G J 64-pin TQFP (PN64-1) 68-pin PGA (G68-1) 68-pin PLCC (J68-1) 15 20 25 35 55 S L 70V05 Commercial Only Commercial & Industrial Commercial & Industrial Commercial & Industrial Commercial & Industrial Standard Power Low Power , Speed in nanoseconds 64K (8K x 8) 3.3V Dual-Port RAM 2941 drw 20 Datasheet Document History 3/11/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Page 2 and 3 Added additional notes to pin configurations Changed drawing format Replaced IDT logo Added 15 & 20ns speed grades Upgraded DC parameters Added Industrial Temperature information Changed ±200mV to 0mV in notes 6/9/99: 11/10/99: 3/10/00: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 622 .42