IDT70V25S25J

HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM Integrated Device Technology, Inc. IDT70V25S/L FEATURES: • True Dual-Ported memory cells which allow simultaneous access of the same memory location • High-speed access — Commercial: 25/35/55ns (max.) • Low-power operation — IDT70V25S Active: 230mW (typ.) Standby: 3.3mW (typ.) — IDT70V25L Active: 230mW (typ.) Standby: 0.66mW (typ.) • Separate upper-byte and lower-byte control for multiplexed bus compatibility • IDT70V25 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device • M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave • Busy and Interrupt Flags • Devices are capable of withstanding greater than 2001V electrostatic charge. • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port • LVTTL-compatible, single 3.3V (± 0.3V) power supply • Available in 84-pin PGA, 84-pin PLCC, and 100-pin TQFP DESCRIPTION: The IDT70V25 is a high-speed 8K x 16 Dual-Port Static RAM. The IDT70V25 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual- FUNCTIONAL BLOCK DIAGRAM R/WL UBL UBR R/WR LBL CEL OEL LBR CER OER I/O8L-I/O15L I/O Control I/O0L-I/O7L I/O Control I/O8R-I/O15R I/O0R-I/O7R BUSYL(1,2) A12L A0L NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. BUSYR(1,2) Address Decoder 13 MEMORY ARRAY 13 Address Decoder A12R A0R CEL OEL R/WL SEML INTL(2) ARBITRATION INTERRUPT SEMAPHORE LOGIC CER OER R/WR SEMR INTR (2) M/S 2944 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE ©1996 Integrated Device Technology, Inc. For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391. OCTOBER 1996 DSC-2944/3 6.39 1 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 350mW of power. The IDT70V25 is packaged in a ceramic 84-pin PGA, an 84-Pin PLCC and a 100-pin Thin Quad Plastic Flatpack. PIN CONFIGURATIONS (1,2) I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L VCC R/ L SEML INDEX I/O8L I/O9L I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 IDT70V25 66 20 J84-1 65 21 84-PIN PLCC 64 22 (3) TOP VIEW 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 A12L A11L A10L A9L A8L A7L A6L A5L A4L A3L A2L A1L A0L INTL OEL UBL LBL CEL W BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R R/ R GND A12R A11R SEMR I/O9R A10R A9R A8R A7R OER UBR LBR CER W 2944 drw 02 VCC R/ L I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L SEML OEL N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 71 70 69 68 67 66 UBL LBL CEL A12L A11L A10L A9L A8L A7L A6L W INDEX N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L INTL IDT70V25 PN100-1 100-PIN TQFP TOP VIEW(3) 65 64 63 62 61 60 59 58 57 56 55 54 53 52 BUSYL GND M/S INTR BUSYR A0R A1R A2R A3R A4R N/C N/C N/C N/C 24 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R R/ R GND UBR LBR NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate the actual part marking. SEMR A12R A11R A10R A9R A8R A7R A6R A5R OER CER 6.39 W 2944 drw 03 2 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATIONS (CONT'D) (1,2) 63 61 60 58 55 54 51 48 46 45 42 11 I/O7L 66 I/O5L 64 I/O4L 62 I/O2L 59 I/O0L 56 OEL 49 SEML 50 LBL 47 A11L 44 A10L 43 A7L 40 10 I/O10L 67 I/O8L 65 I/O6L I/O3L I/O1L 57 UBL 53 CEL 52 A12L A9L A8L 41 A5L 39 09 I/O11L 69 I/O9L 68 GND VCC R/ WL A6L 38 A4L 37 08 I/O13L 72 I/O12L 71 73 33 A3L 35 A2L 34 INTL 07 I/O15L 75 I/O14L 70 VCC 74 BUSYL IDT7V025 G84-3 84-PIN PGA TOP VIEW(3) 32 A0L 31 36 06 I/O0R 76 GND 77 GND 78 GND 28 M/S 29 INTR A1L 30 05 I/O1R 79 I/O2R 80 VCC A0R BUSYR 27 26 04 I/O3R 81 I/O4R 83 7 11 12 A2R 23 A1R 25 03 I/O5R 82 1 I/O7R 2 5 GND 8 GND 10 SEMR 14 17 20 A5R 22 A3R 24 02 I/O6R 84 3 I/O9R I/O10R 4 I/O13R 6 I/O15R 9 R/ 15 WR UBR 13 A11R 16 A8R 18 A6R 19 A4R 21 01 I/O8R A I/O11R B I/O12R C I/O14R D OER E LBR F CER G A12R H A10R J A9R K A7R L 2944 drw 04 Index NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part- marking. PIN NAMES Left Port Right Port Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select Power Ground 2944 tbl 01 CEL R/WL OEL A0L – A12L I/O0L – I/O15L CER R/WR OER A0R – A12R I/O0R – I/O15R SEML UBL LBL INTL BUSYL M/S VCC SEMR UBR LBR INTR BUSYR GND 6.39 3 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL Inputs(1) Outputs CE H X L L L L L L X NOTE: R/W X X L L L H H H X OE X X X X X L L L H UB X H L H L L H L X LB X H H L L H L L X SEM H H H H H H H H X I/O8-15 High-Z High-Z DATAIN High-Z DATAIN DATAOUT High-Z High-Z I/O0-7 High-Z High-Z High-Z DATAIN DATAIN High-Z Both Bytes Deselected Mode Deselected: Power Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only DATAOUT Read Lower Byte Only High-Z Outputs Disabled 2944 tbl 02 DATAOUT DATAOUT Read Both Bytes 1. A0L — A12L ≠ A0R — A12R. TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL Inputs Outputs CE H X H X L L R/W H H OE L L X X UB X H X H L X LB X H X H X L SEM L L L L L L I/O8-15 I/O0-7 Mode DATAOUT DATAOUT Read Data in Semaphore Flag DATAOUT DATAOUT Read Data in Semaphore Flag DATAIN DATAIN — — DATAIN DATAIN — — Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag Not Allowed Not Allowed X X X X ABSOLUTE MAXIMUM RATINGS Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current NOTE: 2944 tbl 03 1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0 - I/O15). These eight semaphores are addressed by A0 - A2. (1) Commercial Unit –0.5 to +4.6 V RECOMMENDED DC OPERATING CONDITIONS Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 3.0 0 2.0 –0.3(1) Typ. 3.3 0 — — Max. Unit 3.6 0 0.8 V V V 2944 tbl 06 TA TBIAS TSTG IOUT 0 to +70 –55 to +125 –55 to +125 50 °C °C °C mA Vcc+0.3 V NOTES: 1. VIL≥ -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V. NOTES: 2944 tbl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20 mA for the period over VTERM > Vcc + 0.5V. CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)TQFP ONLY Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) Max. VIN = 3dV VOUT = 3dV 9 10 Unit pF pF RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Commercial Ambient Temperature 0°C to +70°C GND 0V VCC 3.3V ± 0.3 2944 tbl 05 NOTES: 2944 tbl 07 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 6.39 4 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V ± 0.3V) IDT70V25S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current (1) IDT70V25L Min. — — — 2.4 Max. 5 5 0.4 — Unit µA µA V V 2944 tbl 08 Test Conditions VCC = 3.6V, VIN = 0V to VCC Min. — — — 2.4 Max. 10 10 0.4 — Output Leakage Current Output Low Voltage Output High Voltage CE = VIH, VOUT = 0V to VCC IOL = 4mA IOH = -4mA NOTE: 1. At Vcc ≤ 2.0V input leakages are undefined. DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 3.3V ± 0.3V) 70V25X25 Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports — TTL Level Inputs) Standby Current (One Port — TTL Level Inputs) Test Condition Version COM’L. S L Typ.(2) 80 80 Max. 170 120 70V25X35 Typ.(2) 70 70 Max. 115 100 70V25X55 Typ.(2) Max. Unit 70 70 115 100 mA f = fMAX(3) CE = VIL, Outputs Open SEM = VIH CER = CEL = VIH SEMR = SEML = VIH CEL or CER = VIH(5) ISB1 f = fMAX(3) COM’L. S L 12 10 25 20 10 8 25 20 10 8 25 20 mA ISB2 Active Port Outputs Open f = fMAX(3) SEMR = SEML = VIH COM’L. S L 40 40 82 72 35 35 72 62 35 35 72 62 mA ISB3 Full Standby Current Both Ports CEL and (Both Ports — All CER ≥ VCC - 0.2V CMOS Level Inputs) VIN ≥ VCC - 0.2V or VIN ≤ 0.2V, f = 0(4) SEMR = SEML ≥ VCC - 0.2V Full Standby Current One Port CEL or (One Port — All CER ≥ VCC - 0.2V(5) CMOS Level Inputs) SEMR = SEML ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V Active Port Outputs Open, f = fMAX(3) COM’L. S L 1.0 0.2 5 2.5 1.0 0.2 5 2.5 1.0 0.2 5 2.5 mA ISB4 COM’L. S L 50 50 81 71 45 45 71 61 45 45 71 61 mA 2683 tbl 09 NOTES: 1. "X" in part numbers indicates power rating (S or L). 2. VCC = 5V, TA = +25°C, and are not production tested. Icc dc = 70mA (typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6.39 5 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE 3.3V 3.3V 590Ω DATAOUT 590Ω DATAOUT 435Ω 30pF 435Ω 5pF AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns Max. 1.5V 1.5V Figures 1 and 2 2944 tbl 11 BUSY INT 2944 drw 05 Figure 1. AC Output Load Figure 2. Output Test Load (For tLZ, tHZ, tWZ, tOW) Including scope and jig. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) Symbol READ CYCLE tRC tAA tACE tABE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Parameter IDT70V25X25 Min. Max. 25 — — — — 3 3 — 0 (2) (3) IDT70V25X35 Min. Max. 35 — — — — 3 3 — 0 — 15 — — 35 35 35 20 — — 20 — 55 — 45 IDT70V25X55 Min. Max. 55 — — — — 3 3 — 0 — 15 — — 55 55 55 30 — — 25 — 50 — 65 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2944 tbl 12 Read Cycle Time Address Access Time Chip Enable Access Time(3) Byte Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1, 2) — 25 25 25 15 — — 15 — 25 — 35 Output High-Z Time(1, 2) Chip Enable to Power Up Time(2) Chip Disable to Power Down Time Semaphore Address Access Time Semaphore Flag Update Pulse (OE or SEM) — 15 — NOTES: 1. Transition is measured ± 500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semephore, CE = VIH or UB & LB = VIH, and 4. "X" in part numbers indicates power rating (S or L). SEM = VIL. TIMING OF POWER-UP POWER-DOWN CE ICC ISB tPU 50% tPD 50% 2944 drw 06 6.39 6 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE WAVEFORM OF READ CYCLES(5) tRC ADDR tAA (4) (4) tACE tAOE (4) CE OE , LB tABE UB (4) R/ W tLZ (1) tOH VALID DATA (4) DATAOUT tHZ (2) BUSYOUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB. 3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD. 5. SEM = VIH. tBDD (3, 4) 2944 drw 07 AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5) Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Parameter IDT70V25X25 Min. Max. 25 20 20 0 20 0 15 — 0 — 0 5 5 (1, 2, 4) IDT70V25X35 Min. Max. 35 30 30 0 25 0 20 — 0 — 0 5 5 — — — — — — — 20 — 20 — — — IDT70V25X55 Min. Max. 55 45 45 0 40 0 30 — 0 — 0 5 5 — — — — — — — 25 — 25 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Write Cycle Time Chip Enable to End-of-Write(3) Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (4) (1, 2) (3) — — — — — — — 15 — 15 — — — Write Enable to Output in High-Z(1, 2) Output Active from End-of-Write SEM Flag Write to Read Time SEM Flag Contention Window NOTES: 2944 tbl 13 1. Transition is measured ± 500mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. "X" in part numbers indicates power rating (S or L). 6.39 7 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM (9) CE or SEM (9) tAS(6) R/ tWP(2) tWR(3) W tWZ (7) tOW (4) DATAOUT (4) tDW DATAIN tDH 2944 drw 08 TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE, UB, LB CONTROLLED TIMING(1,5) CE UB LB tWC ADDRESS tAW CE or SEM (9) tAS (6) tEW (2) tWR(3) UB or LB (9) R/ W tDW tDH DATAIN 2944 drw 09 NOTES: 1. R/W or CE or UB & LB must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a Low UB or LB and a Low CE and a Low R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end-of-write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with Output Test Load (Figure 2). 8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIL, and SEM = VIL. tEW must be met for either condition. 6.39 8 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1) tSAA A0-A2 VALID ADDRESS tWR tAW tEW tDW DATAIN VALID tAS tWP tDH VALID ADDRESS tACE tSOP DATAOUT VALID(2) tOH SEM I/O0 R/ W tSWRD tAOE OE Write Cycle Read Cycle 2944 drw 10 NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value. TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4) A0"A"-A2"A" MATCH SIDE(2) “A” R/ W"A" tSPS SEM"A" A0"B"-A2"B" MATCH SIDE(2) “B” R/ W"B" SEM"B" 2944 drw 11 NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH. 2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/W"A" or SEM"A" going High to R/W"B" or SEM"B" going High. 4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag. 6.39 9 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6) Symbol Parameter BUSY TIMING (M/S = VIH) tBAA tBDA tBAC tBDC tAPS tBDD IDT70V25X25 Min. Max. — — — — 5 — 20 0 20 — (1) IDT70V25X35 Min. Max. — — — — 5 — 25 0 25 — — 35 35 35 35 — 35 — — — 60 55 IDT70V25X55 Min. Max. — — — — 5 — 25 0 25 — — 45 45 45 45 — 45 — — — 80 75 Unit ns ns ns ns ns ns ns ns ns ns ns BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Low BUSY Disable Time from Chip High Arbitration Priority Set-up Time (2) 25 25 25 25 — 35 — — — 55 50 BUSY Disable to Valid Data(3) Write Hold After BUSY(5) tWH BUSY TIMING (M/S = VIL) BUSY Input to Write(4) tWB Write Hold After BUSY(5) tWH PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay — 2944 tbl 14 NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 6. "X" is part numbers indicates power rating (S or L). TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUSY (M/S = VIH)(2,4,5) BUSY tWC ADDR"A" MATCH tWP R/ W"A" tDW tDH VALID tAPS (1) DATAIN "A" ADDR"B" tBAA MATCH tBDA tBDD BUSY"B" tWDD DATAOUT "B" tDDD (3) 2944 drw 12 VALID NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A". 6.39 10 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE WITH BUSY BUSY tWP R/ "A" W tWB(3) BUSY"B" tWH (1) R/ "B" NOTES: 1. tWH must be met for both BUSY input (slave) output master. 2. Busy is asserted on port "B" Blocking R/W"B", until BUSY"B" goes High. 3. tWB is only for the slave version. W (2) 2944 drw 13 WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1) CE ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS(2) CE"B" tBAC tBDC 2944 drw 14 BUSY"B" WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING (M/S = VIH)(1) ADDR"A" tAPS ADDR"B" (2) ADDRESS "N" MATCHING ADDRESS "N" tBAA tBDA 2944 drw 15 BUSY"B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 6.39 11 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time Parameter IDT70V25X25 Min. Max. 0 0 — — — — 25 30 IDT70V25X35 Min. Max. 0 0 — — — — 30 35 IDT70V25X55 Min. Max. 0 0 — — — — 40 45 Unit ns ns ns ns 2944 tbl 15 NOTE: 1. "X" in part numbers indicates power rating (S or L). WAVEFORM OF INTERRUPT TIMING(1) tWC ADDR"A" tAS (3) INTERRUPT SET ADDRESS (2) tWR(4) CE"A" R/ W"A" tINS(3) INT"B" 2944 drw 16 tRC ADDR"B" tAS (3) INTERRUPT CLEAR ADDRESS (2) CE"B" OE"B" tINR(3) INT"B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Flag truth table. 3. Timing depends on which enable signal ( CE or R/W ) is asserted last. 4. Timing depends on which enable signal ( CE or R/W ) is de-asserted first. 2944 drw 17 TRUTH TABLES TRUTH TABLE III — INTERRUPT FLAG(1) Left Port R/WL L X X X Right Port A12L-A0L 1FFF X X 1FFE CEL L X X L OEL X X X L INTL X X L(3) H (2) R/WR X X L X CER X L L X OER X L X X A12R-A0R X 1FFF 1FFE X INTR L (2) (3) Function Set Right INTR Flag Set Left INTL Flag Reset Right INTR Flag Reset Left INTL Flag 2944 tbl 16 H X X NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 6.39 12 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE TRUTH TABLE IV — ADDRESS BUSY ARBITRATION Inputs Outputs CEL X H X L CER X X H L A0L-A12L A0R-A12R NO MATCH MATCH MATCH MATCH BUSYL(1) BUSYR(1) H H H (2) H H H (2) Function Normal Normal Normal Write Inhibit(3) NOTES: 2944 tbl 17 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V25 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin. TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2) Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D15 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D15 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Right port has semaphore token Semaphore free 2944 tbl 18 Status NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V25. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2. FUNCTIONAL DESCRIPTION The IDT70V25 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V25 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE High). When a port is enabled, access to the entire memory array is permitted. memory location 1FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 1FFF. The message (16 bits) at 1FFE or 1FFF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table for the interrupt operation. BUSY LOGIC INTERRUPTS If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFE (HEX), where a write is defined as the CER = R/WR = VIL per the Truth Table. The left port clears the interrupt by an address location 1FFE access when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the right port interrupt flag (INTR) is set when the left port writes to Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all 6.39 13 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE MASTER Dual Port RAM CE BUSYR BUSYL SLAVE Dual Port RAM CE BUSYR BUSYL MASTER Dual Port RAM CE BUSYR BUSYL BUSYL SLAVE Dual Port RAM CE BUSYR BUSYR 2944 drw 18 BUSYL Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V25 RAMs. applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. The busy outputs on the IDT 70V25 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the busy indication for the resulting array requires the use of an external AND gate. inhibit signal and corrupted data in the slave. SEMAPHORES The IDT70V25 is an extremely fast Dual-Port 8K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table where CE and SEM are both high. Systems which can best use the IDT70V25 contain multiple processors or controllers and are typically very highspeed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V25's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V25 does not use its semaphore flags to control any resources through WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS When expanding an IDT70V25 RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT70V25 RAM the busy pin is an output if the part is used as a master (M/S pin = H), and the busy pin is an input if the part used as a slave (M/S pin = L) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The busy arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write 6.39 DECODER 14 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. HOW THE SEMAPHORE FLAGS WORK The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V25 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table III). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table III). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay low until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must 6.39 15 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. USING SEMAPHORES—SOME EXAMPLES Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V25’s Dual-Port RAM. Say the 8K x 16 RAM was to be divided into two 4K x 16 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 4K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 4K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 4K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE SEMAPHORE READ D Q R PORT SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ 2944 drw 19 Figure 4. IDT70V25 Semaphore Logic 6.39 16 IDT70V25S/L HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank Commercial (0°C to +70°C) PF G J 100-pin TQFP (PN100-1) 84-pin PGA (G84-3) 84-pin PLCC (J84-1) 25 35 55 Speed in nanoseconds S L Standard Power Low Power 70V25 128K (8K x 16) 3.3V Dual-Port RAM 2944 drw 20 6.39 17