IDT70V631S12PRF

HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM Features ◆ ◆ IDT70V631S ◆ ◆ ◆ ◆ ◆ ◆ Functional Block Diagram UBL LBL True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 12ns (max.) Dual chip enables allow for depth expansion without external logic IDT70V631 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Supports JTAG features compliant to IEEE 1149.1 – Due to limited pin count, JTAG is not supported on the 128-pin TQFP package. LVTTL-compatible, single 3.3V (±150mV) power supply for core LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port Available in a 128-pin Thin Quad Flatpack, 208-ball fine pitch Ball Grid Array, and 256-ball Ball Grid Array Industrial temperature range (–40°C to +85°C) is available for selected speeds UBR LBR R/ WL B E 0 L B E 1 L B E 1 R B E 0 R R/WR CE0L CE1L CE0 R CE1 R OEL Dout0-8_L Dout9-17_L Dout0-8_R Dout9-17_R OER 256K x 18 MEMORY ARRAY I/O0L- I/O17L Din_L Din_R I/O0R - I/O17R A17L A0L Address Decoder ADDR_L ADDR_R Address Decoder A17R A0R OEL CE0L CE1L R/WL BUSYL SEML INTL ARBITRATION INTERRUPT SEMAPHORE LOGIC OER CE0 R CE1 R R/WR BUSYR M/ S SEM R INTR TDI TDO JTAG TMS TCK TRST 5622 drw 01 NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). OCTOBER 2003 DSC-5622/5 1 ©2003 Integrated Device Technology, Inc. IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges The IDT70V631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM. The IDT70V631 is designed to be used as a stand-alone 4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 36-bit-or-more word system. Using the IDT MASTER/ SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, Description address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. The 70V631 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) remains at 3.3V. Pin Configurations(1,2,3,4) 09/30/03 1 I/O9L 2 NC 3 VSS 4 TDO 5 NC 6 A 16L 7 A12L 8 A8 L 9 NC 10 11 VDD 12 INTL 13 14 A4L A0L 15 OPT L 16 17 NC V SS A B C D E F G H J K L M N P R T U SEML A B C D E F G H J K L M N P R T U NC VSS NC TDI A17 L A 13L A 9L NC CE0L VSS BUSYL A5L A1L VSS VDDQR I/O8L NC VDDQ L I/O 9R VDDQ R VDD NC A1 4L A10L UBL CE1L VSS R/WL A6L A2L VDD I/O8R NC VSS NC VSS I/O10L NC A1 5L A 11L A7L LBL VDD OE L NC A 3L VDD NC VDDQ L I/O 7L I/O7R I/O11L NC V DDQ R I/O 10R I/O6L NC VSS NC VDDQ L I/O 11R NC V SS VSS I/O 6R NC VDDQ R NC VSS I/O1 2L NC NC VDDQL I/O5L NC VDD NC VDDQR I/O 12R 70V631BF BF-208(5) 208-Ball BGA Top View(6) VDD NC VSS I/O5R VDDQ L V DD VSS VSS VS S VDD VSS VDDQ R I/O14R VSS I/O13R V SS I/O3R VDDQ L I/O4R VSS NC I/O 14L V DDQ R I/O 13L NC I/O 3L VSS I/O4 L VDDQ L NC I/O15R VSS VSS NC I/O2R VDDQR NC VSS NC I/O 15L I/O1R VDDQ L NC I/O 2L I/O16R I/O 16L V DDQ R NC TRST A 16R A1 2R A8 R NC VDD SEMR INT R A4R NC I/O1L VSS NC VSS NC I/O17R TCK A1 7R A 13R A9R NC CE0R V SS BUSYR R/WR A5R A 1R VSS VDDQL I/O 0R VDDQ R NC I/O17L VDDQL TMS NC A 14R A10R UBR CE1R V SS A6R A 2R VSS NC VSS NC VSS NC VDD NC A15R A11R A7R LB R VDD OER M/S A3R A 0R V DD OPTR NC I/O0 L 5622 tbl 02b NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V) and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground. 4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 2 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3,4,7) (con't.) 09/30/03 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 A13L A12L A11L A10L A9L A8L A7L UBL LBL CE1L CE0L VDD VDD VSS VSS SEML OEL R/WL BUSYL INTL NC A6L A5L A4L A3L A2L A14L A15L A16L A17L IO9L IO 9R VDDQL VSS IO10L IO10R VDDQR VSS IO11L IO11R IO12L IO12R VDD VDD VSS VSS IO13R IO13L IO14R IO14L IO15R IO15L VDDQL VSS IO16R IO16L VDDQR VSS IO17R IO17L A17R A16R A15R A14R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 70V631PRF PK-128(5) 128-Pin TQFP Top View(6) 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 A1L A0L OPTL VSS IO8L IO8R NC VSS VDDQL IO7L IO7R VSS VDDQR IO6L IO6R IO5L IO5R VDD VDD VSS VSS IO4R IO4L IO3R IO3L IO2R IO2L VSS VDDQL IO1R IO1L VSS VDDQR IO0R IO0L OPTR A0R A1R . A13R A12R A11R A10R A9R A8R A7R UBR LBR CE1R CE0R VDD VDD VSS VSS SEMR OER R/WR BUSYR INTR M/S A6R A5R A4R A3R A2R 5622 drw 02a NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V) and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground. 4. Package body is approximately 14mm x 20mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 7. Due to the restricted number of pins, JTAG is not supported in the PK-128 package. 3 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3,4) (con't.) 70V631BC BC-256(5) 256-Pin BGA Top View(6) 09/30/03 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 NC B1 TDI B2 NC B3 A17L B4 A 14L B5 A 11L B6 A 8L B7 NC B8 CE1L B9 OEL B10 INT L B11 A5L B12 A2L B13 A0L B14 NC B15 NC B16 NC C1 NC C2 TDO C3 NC C4 A15L C5 A12L C6 A 9L C7 UBL C8 CE0L R/WL C9 C10 NC C11 A4L C12 A1L C13 NC C14 NC C15 NC C16 NC D1 I/O9L D2 V SS D3 A16L D4 A13L D5 A10L D6 A7L D7 NC D8 LBL D9 SEM L BUSYL D10 D11 A6L D12 A3L D13 OPTL D14 NC D15 I/O 8L D16 NC E1 I/O 9R E2 NC E3 V DD E4 VDDQL VDDQL V DDQR VDDQR VDDQL VDDQL VDDQR VDDQR E5 E6 E7 E8 E9 E10 E11 E12 VDD E13 NC E14 NC E15 I/O 8R E16 I/O10R I/O10L F1 F2 NC F3 V DDQL F4 VDD F5 VDD F6 VSS F7 VSS F8 V SS F9 VSS F10 VDD F11 VDD V DDQR F12 F13 NC F14 I/O7L F15 I/O 7R F16 I/O11L G1 NC G2 I/O11R VDDQL G3 G4 VDD G5 VSS G6 VSS G7 VSS G8 V SS G9 VSS G10 VSS G11 VDD G12 V DDQR I/O6R G13 G14 NC G15 I/O 6L G16 NC H1 NC H2 I/O12L VDDQR H3 H4 V SS H5 VSS H6 VSS H7 VSS H8 V SS H9 VSS H10 VSS H11 VSS H12 VDDQL I/O5L H13 H14 NC H15 NC H16 NC J1 I/O12R J2 NC J3 VDDQR J4 VSS J5 V SS J6 VSS J7 VSS J8 VSS J9 V SS J10 VSS J11 VSS J12 V DDQL J13 NC J14 NC J15 I/O5R J16 I/O 13L I/O14R I/O 13R V DDQL K1 K2 K3 K4 V SS K5 VSS K6 VSS K7 VSS K8 V SS K9 VSS K10 VSS K11 VSS K12 V DDQR I/O 4R I/O 3R K13 K14 K15 I/O 4L K16 NC L1 NC L2 I/O14L V DDQL L3 L4 V SS L5 VSS L6 VSS L7 VSS L8 V SS L9 VSS L10 VSS L11 VSS L12 V DDQR L13 NC L14 NC L15 I/O 3L L16 I/O 15L M1 NC M2 I/O15R VDDQR M3 M4 VDD M5 VSS M6 VSS M7 VSS M8 V SS M9 V SS M10 VSS M11 VDD M12 V DDQL I/O2L M13 M14 NC M15 I/O2R M16 I/O 16R I/O16L N1 N2 NC N3 VDDQR N4 VDD N5 V DD N6 VSS N7 VSS N8 V SS N9 VSS N10 VDD N11 VDD N12 V DDQL I/O1R N13 N14 I/O1L N15 NC N16 NC P1 I/O17R P2 NC P3 VDD P4 V DDQR VDDQR VDDQL VDDQL V DDQR V DDQR VDDQL V DDQL P5 P6 P7 P8 P9 P10 P11 P12 VDD P13 NC P14 I/O 0R P15 NC P16 NC R1 I/O17L TMS R2 R3 A16R R4 A13R R5 A10R R6 A7R R7 NC R8 LBR R9 SEM R BUSYR R10 R11 A6R R12 A3R R13 NC R14 NC R15 I/O0L R16 NC T1 NC T2 TRST T3 NC T4 A15R T5 A 12R T6 A9R T7 UBR T8 CE0R R/W R T9 T10 M/ S T11 A4R T12 A1R T13 OPTR T14 NC T15 NC T16 , NC TCK NC A17R A14R A11R A8R NC CE1R OER INT R A 5R A2R A 0R NC NC 5622 drw 02c NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. , 4 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port CE0L, CE1L R/WL OEL A0L - A17L I/O0L - I/O17L SEML INTL BUSYL UBL LBL VDDQL OPTL M/S VDD VSS TDI TDO TCK TMS TRST Right Port CE0R, CE1R R/ WR OER A0R - A17R I/O0R - I/O17R SEMR INTR BUSYR UBR LBR VDDQR OPTR Chip Enables Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Upper Byte Select Lower Byte Select Power (I/O Bus) (3.3V or 2.5V)(1) Option for selecting VDDQX(1,2) Master or Slave Select Power (3.3V)(1) Ground (0V) Test Data Input Test Data Output Test Logic Clock (10MHz) Test Mode Select Reset (Initialize TAP Controller) 5622 tbl 01 Names NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on I/OX. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 5 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table I—Read/Write and Enable Control(1) OE X X X X X X L L L H SEM H H H H H H H H H H CE0 H X L L L L L L L L CE 1 X L H H H H H H H H UB X X H H L L H L L L LB X X H L H L L H L L R/W X X X L L L H H H X Byte 1 I/O9-17 High-Z High-Z High-Z High-Z DIN DIN High-Z DOUT DOUT High-Z Byte 0 I/O0-8 High-Z High-Z High-Z DIN High-Z DIN DOUT High-Z DOUT High-Z MODE Deselected–Power Down Deselected–Power Down Both Bytes Deselected Write to Byte 0 Only Write to Byte 1 Only Write to Both Bytes Read Byte 0 Only Read Byte 1 Only Read Both Bytes Outputs Disabled 5622 tbl 02 NOTE: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. Truth Table II – Semaphore Read/Write Control(1) Inputs(1) CE H H L R/W H ↑ X OE L X X UB L X X LB L L X SEM L L L Outputs I/O1-17 DATAOUT X ______ I/O0 DATAOUT DATAIN ______ Mode Read Data in Semaphore Flag (3) Write I/O0 into Semaphore Flag Not Allowed 5622 tbl 03 NOTE: 1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A 0-A2. 2. CE = L occurs when CE0 = VIL and CE1 = VIH. 3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = VIL. 6 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage(1) Grade Commercial Industrial Ambient Temperature 0 C to +70 C O O Recommended DC Operating Conditions with VDDQ at 2.5V Symbol Parameter Core Supply Voltage I/O Supply Voltage Ground Input High Voltage (Address & Control Inputs) Input High Voltage - I/O(3) Input Low Voltage (3) (3) Min. 3.15 2.4 0 1.7 1.7 -0.5 (1) Typ. 3.3 2.5 0 ____ Max. 3.45 2.6 0 VDDQ + 100mV (2) Unit V V V V V V 5622 tbl 06 GND 0V 0V VDD 3.3V + 150mV 3.3V + 150mV 5622 tbl 04 VDD VDDQ VSS VIH VIH VIL -40 C to +85 C O O NOTE: 1. This is the parameter TA. This is the "instant on" case temperature. ____ ____ VDDQ + 100mV(2) 0.7 Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 Unit V NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VDDQ + 100mV. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied as indicated above. TBIAS TSTG IOUT -55 to +125 -65 to +150 50 o C C o Recommended DC Operating Conditions with VDDQ at 3.3V Symbol Parameter Core Supply Voltage I/O Supply Voltage Ground Input High Voltage (Address & Control Inputs)(3) Input High Voltage - I/O(3) Input Low Voltage (3) Min. 3.15 3.15 0 2.0 2.0 -0.3 (1) Typ. 3.3 3.3 0 ____ Max. 3.45 3.45 0 VDDQ + 150mV (2) Unit V V V V V V 5622 tbl 07 mA 5622 tbl 05 VDD VDDQ VSS V IH V IH VIL NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV. ____ ____ VDDQ + 150mV (2) 0.8 Capacitance(1) Symbol CIN COUT(3) (TA = +25°C, F = 1.0MHZ) TQFP ONLY Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 8 10.5 Unit pF pF 5622 tbl 08 NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed V DDQ + 150mV. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be supplied as indicated above. NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. 7 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV) 70V631S Symbol |ILI| |ILO | VOL (3.3V) VOH (3.3V) VOL (2.5V) VOH (2.5V) Parameter Input Leakage Current (1) Test Conditions VDDQ = Max., VIN = 0V to V DDQ CE0 = VIH or CE1 = VIL, VOUT = 0V to V DDQ IOL = + 4mA, VDDQ = Min. IOH = -4mA, VDDQ = Min. IOL = + 2mA, VDDQ = Min. IOH = -2mA, VDDQ = Min. Min. ___ ___ ___ Max. 10 10 0.4 ___ Unit µA µA V V V V 5622 tbl 09 Output Leakage Current Output Low Voltage(2) Output High Voltage Output Low Voltage (2) 2.4 ___ (2) (2) 0.4 ___ Output High Voltage 2.0 NOTE: 1. At VDD < - 2.0V input leakages are undefined. 2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV) 70V631S10 Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Test Condition CEL and C ER= VIL, Outputs Disabled, f = fMAX(1) CEL = C ER = VIH f = fMAX(1) CE"A" = VIL and C E"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(1) Version COM'L IND COM'L IND COM'L IND COM'L IND S S S S S S S S S S Typ.(4) 340 ____ 70V631S12 Com'l & Ind Typ.(4) 315 365 90 115 200 225 3 6 195 220 Max. 465 515 125 150 325 365 15 15 320 360 70V631S15 Com'l Typ.(4) 300 ____ Max. 500 ____ Max. 440 ____ Unit mA ISB1 115 ____ 165 ____ 75 ____ 100 ____ mA ISB2 225 ____ 340 ____ 175 ____ 315 ____ mA ISB3 Full Standby Current Both Ports C EL and (Both Ports - CMOS CER > VDD - 0.2V, VIN > VDD - 0.2V Level Inputs) or VIN < 0.2V, f = 0(2) Full Standby Current (One Port - CMOS Level Inputs) 3 ____ 15 ____ 3 ____ 15 ____ mA ISB4 CE"A" < 0.2V and C E"B" > VDD - 0.2V(5) COM'L VIN > VDD - 0.2V or V IN < 0.2V, Active IND Port, Outputs Disable d, f = fMAX(1) 220 ____ 335 ____ 170 ____ 310 ____ mA 5622 tbl 10 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = V IL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V "X" represents "L" for left port or "R" for right port. 8 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions (VDDQ - 3.3V/2.5V) Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V / GND to 2.5V 2ns Max. 1.5V/1.25V 1.5V/1.25V Figures 1 and 2 5622 tbl 11 2.5V 833Ω DATAOUT 770Ω 5pF* Figure 2. Output Test Load , 3.3V 590Ω 50Ω DATAOUT 50Ω 1.5V/1.25 10pF (Tester) , DATAOUT 435Ω 5pF* 5622 drw 03 Figure 1. AC Output Test load. 5622 drw 04 , Figure 2. Output Test Load (For tCKLZ , tCKHZ, tOLZ, and tOHZ). *Including scope and jig. 10.5pF is the I/O capacitance of this device, and 10pF is the AC Test Load Capacitance. 7 6 5 4 ∆tAA (Typical, ns) 3 2 1 • • 20.5 • 30 • 50 80 100 200 , -1 Capacitance (pF) 5622 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load). 9 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(5) 70V631S10 Com'l Only Symbol READ CYCLE tRC tAA tACE tABE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time (3) (3) 70V631S12 Com'l & Ind Min. Max. 70V631S15 Com'l Min. Max. Unit Parameter Min. Max. 10 ____ ____ ____ ____ ____ 12 ____ ____ ____ ____ ____ 15 ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns 5622 tbl 12 10 10 5 5 ____ ____ 12 12 6 6 ____ ____ 15 15 7 7 ____ ____ Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) (1,2) 3 0 0 0 ____ ____ 3 0 0 0 ____ ____ 3 0 0 0 ____ ____ Output High-Z Time 4 ____ 6 ____ 8 ____ Chip Enable to Power Up Time (2) Chip Disable to Power Down Time (2) Semaphore Flag Update Pulse (OE o r SEM) Semaphore Address Access Time 10 4 10 10 6 12 15 8 20 3 3 3 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 70V631S10 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write (3) 70V631S12 Com'l & Ind Min. Max. 70V631S15 Com'l Min. Max. Unit Parameter Min. Max. 10 8 8 0 8 0 6 0 ____ ____ ____ ____ ____ ____ ____ ____ ____ 12 10 10 0 10 0 8 0 ____ ____ ____ ____ ____ ____ ____ ____ ____ 15 12 12 0 12 0 10 0 ____ ____ ____ ____ ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time (4) Write Enable to Output in High-Z(1,2) Output Active from End-of-Write SEM F lag Write to Read Time SEM Flag Contention Window (1,2,4) (3) 4 ____ ____ ____ 4 ____ ____ ____ 4 ____ ____ ____ 0 5 5 0 5 5 0 5 5 5622 tbl 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranted by device characterization, but is not production tested. 3. To access RAM, CE= V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details. 10 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Read Cycles(5) tRC ADDR tAA (4) tACE tAOE OE tABE (4) UB, LB (4) (4) CE (6) R/W tLZ DATAOUT (1) tOH VALID DATA (4) (2) tHZ BUSYOUT tBDD (3,4) 5622 drw 06 NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB or UB . 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD . 5. SEM = VIH. Timing of Power-Up Power-Down CE tPU ICC 50% 50% 5622 drw 07 tPD . ISB 11 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ OE tAW CE or SEM (9) (7) UB, LB (9) tAS (6) R/W tWZ (7) DATAOUT (4) tWP (2) tWR (3) tOW (4) tDW DATAIN tDH 5622 drw 08 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM (9) (6) tAS UB, LB(9) tEW (2) tWR(3) R/W tDW DATAIN 5622 drw 09 tDH NOTES: 1. R/W or CE or BEn = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/ W = VIL for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW . If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 12 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS tAW SEM/UB/LB(1) tEW tOH tDW I/O tAS R/W tSWRD OE Write Cycle VALID ADDRESS tACE tWR tSOP DATA OUT(2) VALID DATAIN VALID tWP tDH tAOE tSOP Read Cycle 5622 drw 10 NOTES: 1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate UB /LB controls. 2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17 ) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" MATCH SIDE (2) "A" R/W"A" SEM"A" tSPS A0"B"-A2"B" MATCH SIDE (2) "B" R/W"B" SEM"B" 5622 drw 11 NOTES: 1. DOR = DOL = VIL, CEL = CER = VIH. Refer also to Truth Table II for appropriate UB/LB controls. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag. 13 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70V631S10 Com'l Only Symbol BUSY TIMING (M/S=VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Enable Low BUSY Disable Time from Chip Enable High Arbitration Priority Set-up Time (2) BUSY Disable to Valid Data Write Hold After BUSY (5) (3) ____ ____ ____ ____ Parameter 70V631S12 Com'l & Ind Min. Max. 70V631S15 Com'l Min. Max. Unit Min. Max. 10 10 10 10 ____ ____ ____ ____ ____ 12 12 12 12 ____ ____ ____ ____ ____ 15 15 15 15 ____ ns ns ns ns ns ns ns 5 ____ 5 ____ 5 ____ 10 ____ 12 ____ 15 ____ 8 10 12 BUSY TIMING (M/S=VIL) tWB tWH BUSY Input to Write(4) Write Hold After BUSY(5) 0 8 ____ ____ 0 10 ____ ____ 0 12 ____ ____ ns ns PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) ____ ____ 22 20 ____ ____ 25 22 ____ ____ 30 25 ns ns 5622 tbl 14 NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 14 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS ADDR"B" tBAA BUSY"B" tWDD DATAOUT "B" tDDD (3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 5622 drw 12 (1) tDH VALID MATCH tBDA tBDD VALID Timing Waveform of Write with BUSY (M/S = VIL) tWP R/W"A" tWB(3) BUSY"B" tWH (1) R/W"B" NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH. 3. tWB is only for the 'slave' version. (2) 5622 drw 13 15 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC BUSY"B" 5622 drw 14 tBDC Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S = VIH)(1) ADDR"A" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA BUSY"B" 5622 drw 15 ADDRESS "N" tBDA NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70V631S10 Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 ____ ____ ____ ____ 70V631S12 Com'l & Ind Min. Max. 70V631S15 Com'l Min. Max. Unit Parameter Min. Max. 0 0 ____ ____ ____ ____ 0 0 ____ ____ ____ ____ ns ns ns ns 5622 tbl 15 10 10 12 12 15 15 16 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1) tWC ADDR"A" tAS(3) CE"A" INTERRUPT SET ADDRESS (2) tWR (4) R/W"A" tINS INT"B" 5622 drw 16 (3) tRC ADDR"B" tAS CE"B" INTERRUPT CLEAR ADDRESS (3) (2) OE"B" tINR (3) INT"B" 5622 drw 17 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. Refer to Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/ W) is de-asserted first. Truth Table III — Interrupt Flag(1,4) Left Port R/WL L X X X CEL L X X L OEL X X X L A17L-A0L 3FFFF X X 3FFFE INTL X X L (3) (2) Right Port R/WR X X L X CER X L L X OER X L X X A17R-A0R X 3FFFF 3FFFE X INTR L(2) H (3) Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag 5622 tbl 16 X X H NOTES: 1. Assumes BUSYL = BUSYR =VIH. 2. If BUSYL = V IL, then no change. 3. If BUSYR = VIL, then no change. 4. INTL and INTR must be initialized at power-up. 17 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table IV — Address BUSY Arbitration Inputs CEL X H X L CER X X H L AOL-A17L AOR-A17R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3) 5622 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V631 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSY R = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D17 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D17 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free 5622 tbl 18 Status NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V631. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 ). These eight semaphores are addressed by A0 - A2. 3. CE = VIH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. The IDT70V631 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V631 has an automatic power down feature controlled by CE. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = HIGH). When a port is enabled, access to the entire memory array is permitted. Functional Description If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 18 Interrupts 3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the Truth Table. The left port clears the interrupt through access of address location 3FFFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 3FFFF. The message (18 bits) at 3FFFE or 3FFFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 3FFFE and 3FFFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT70V631 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. A18 CE0 MASTER Dual Port RAM BUSYL BUSYR CE0 SLAVE Dual Port RAM BUSYL BUSYR CE1 MASTER Dual Port RAM BUSYL BUSYR CE1 SLAVE Dual Port RAM BUSYL BUSYR . 5622 drw 18 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V631 RAMs. Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT70V631 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAMs array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT70V631 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration on a master is based on the chip enable and 19 The IDT70V631 is an extremely fast Dual-Port 256K x 18 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, with both ports being completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. Systems which can best use the IDT70V631 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V631s hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V631 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. Semaphores The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then How the Semaphore Flags Work IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V631 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, R/W and LB/UB) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore, byte select (SEM, LB/UB) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. However, during reads LB and UB function only as an output for semaphore. They do not have any iinfluence on the semaphore control logic. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in 20 question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D Q R PORT SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ Figure 4. IDT70V631 Semaphore Logic SEMAPHORE READ 5622 drw 19 continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges JTAG Timing Specifications tJF TCK tJCL tJCYC tJR tJCH Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO TRST 5622 drw 20 tJH tJDC tJRSR tJCD x tJRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical Characteristics(1,2,3,4) Symbol tJCYC tJCH tJCL tJR tJF tJRST tJRSR tJCD tJDC tJS tJH Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold Min. 100 40 40 ____ ____ Max. ____ ____ ____ Units ns ns ns ns ns ns ns ns ns ns ns 5622 tbl 19 3 (1) 3(1) ____ ____ 50 50 ____ 25 ____ ____ ____ 0 15 15 NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. 21 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) Value 0x0 0x304 0x33 1 Reserved for version number Defines IDT part number Allows unique identification of device vendor as IDT Indicates the presence of an ID register 5622 tbl 20 Description Scan Register Sizes Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) Bit Size 4 1 32 Note (3) 5622 tbl 21 System Interface Parameters Instruction EXTEST BYPASS IDCODE Code 0000 1111 0010 0100 Description Forces contents of the bound ary scan cells onto the device outputs(1). Places the boundary scan register (BSR) between TDI and TDO. Places the bypass registe r (BYR) between TDI and TDO. Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state. Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass registe r (BYR) between TDI and TDO. Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) and outputs(1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. Several combinations are reserved. Do not use codes other than those identified above. 5622 tbl 22 HIGHZ CLAMP SAMPLE/PRELOAD 0011 0001 RESERVED All other codes NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative. 22 IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Blank I(1) BF PRF BC 208-ball fpBGA (BF-208) 128-pin TQFP (PK-128) 256-ball BGA (BC-256) 10 12 15 Commercial Only Commercial & Industrial Commercial Only Speed in nanoseconds S Standard Power 70V631 4608K (256K x 18) 3.3V Asynchronous Dual-Port RAM 5622 drw 21 NOTE: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. Datasheet Document History: 06/01/00: 08/07/00: 06/20/01: 08/08/01: 10/01/03: Initial Public Offering Page 6, 13 & 20 Inserted additional LB and UB information Page 1 Added JTAG information for TQFP package Page 14 Increased BUSY TIMING parameters tBDA, tBAC, tBDC and tBDD for all speeds Page 21 Changed maximum value for JTAG AC Electrical Characteristics for tJCD from 20ns to 25ns Page 3 Corrected pin 4 designation error from A17R to A17L on PK-128 pinout Removed Preliminary status Page 2, 3 & 4 Added date revision for pin configurations Page 8, 10, 14 & 16 Removed I-temp 15ns speed from DC & AC Electrical Characteristics Tables Page 23 Removed I-temp 15ns speed from ordering information Added I-temp footnote to ordering information Page 1 & 23 Replaced TM logo with ® logo CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 23