IDT70V7319S200DDI

HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ IDT70V7319S ◆ ◆ ◆ ◆ ◆ ◆ 256K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 18 banks – 4 megabits of memory on chip Bank access controlled via bank address pins High-speed data access – Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz) (max.) – Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports – 5ns cycle time, 200MHz operation (14Gbps bandwidth) – Fast 3.4ns clock to data out – 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz ◆ ◆ ◆ ◆ ◆ ◆ – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time Separate byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, 3.3V (±150mV) power supply for core LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz Available in a 144-pin Thin Quad Flatpack (TQFP), 208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball Grid Array (BGA) Supports JTAG features compliant with IEEE 1149.1 – Due to limited pin count, JTAG is not supported on the 144-pin TQFP package. Functional Block Diagram PL/FTL OPTL CLKL ADSL CNTENL REPEATL R/WL CE0L CE1L UBL LBL OEL PL/FTR OPTR CLKR ADSR CNTENR REPEATR R/WR CE0R CE1R UBR LBR OER CONTROL LOGIC MUX 4Kx18 MEMORY ARRAY (BANK 0) MUX CONTROL LOGIC I/O0L-17L I/O CONTROL MUX 4Kx18 MEMORY ARRAY (BANK 1) MUX I/O CONTROL I/O0R-17R A11L A0L BA5L BA4L BA3L BA2L BA1L BA0L ADDRESS DECODE ADDRESS DECODE A11R A0R BA5R BA4R BA3R BA2R BA1R BA0R BANK DECODE MUX 4Kx18 MEMORY ARRAY (BANK 63) BANK DECODE NOTE: 1. The Bank-Switchable dual-port uses a true SRAM core instead of the traditional dual-port SRAM core. As a result, it has unique operating characteristics. Please refer to the functional description on page 19 for details. MUX , TDI TDO JTAG TMS TCK TRST 5629 drw 01 DECEMBER 2002 1 DSC 5629/6 ©2002 Integrated Device Technology, Inc. IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V7319 is a high-speed 256Kx18 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM organized into 64 independent 4Kx18 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4Kx18 memory block not alReady accessed by the other port. Accesses by the ports into specific banks are controlled via the bank address pins under the user's direct control. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V7319 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The dual chip enables also facilitate depth expansion. The 70V7319 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device(VDD) remains at 3.3V. Please refer also to the functional description on page 19. Pin Configuration(1,2,3,4) 11/20/01 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 IO9L B1 NC B2 VSS B3 TDO B4 NC B5 BA4L B6 BA0L B7 A8L B8 NC B9 VDD B10 CLKL CNTENL A4L B11 B12 B13 A0L B14 OPTL B15 NC B16 VSS B17 NC C1 VSS C2 NC C3 TDI C4 BA5L C5 BA1L C6 A9L C7 NC C8 CE0L C9 VSS C10 ADSL C11 A5L C12 A1L C13 VSS C14 VDDQR I/O8L C15 C16 NC C17 VDDQL I/O9R VDDQR PL/FTL D1 D2 D3 D4 NC D5 BA2L D6 A10L D7 UBL D8 CE1L D9 VSS D10 R/WL D11 A6L D12 A2L D13 VDD D14 I/O8R D15 NC D16 VSS D17 NC E1 VSS E2 I/O10L E3 NC E4 BA3L A11L A7L LBL VDD OEL REPEATL A3L VDD NC E14 VDDQL I/O7L E15 E16 I/O7R E17 I/O11L F1 NC F2 VDDQR I/O10R F3 F4 I/O6L F14 NC F15 VSS F16 NC F17 VDDQL I/O11R G1 G2 NC G3 VSS G4 VSS G14 I/O6R G15 NC G16 VDDQR G17 NC H1 VSS H2 I/O12L H3 NC H4 NC VDDQL I/O5L H15 H16 NC H17 VDD J1 NC J2 VDDQR I/O12R J3 J4 70V7319BF BF-208(5) 208-Pin fpBGA Top View(6) H14 VDD J14 NC J15 VSS J16 I/O5R J17 VDDQL K1 VDD K2 VSS K3 VSS K4 VSS K14 VDD K15 VSS VDDQR K16 K17 I/O14R L1 VSS L2 I/O13R L3 VSS L4 I/O3R VDDQL I/O4R L14 L15 L16 VSS L17 NC M1 I/O14L VDDQR I/O13L M2 M3 M4 NC M14 I/O3L M15 VSS M16 I/O4L M17 VDDQL N1 NC N2 I/O15R N3 VSS N4 VSS N14 NC N15 I/O2R VDDQR N16 N17 NC P1 VSS P2 NC P3 I/O15L P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 I/O1R VDDQL P14 P15 NC P16 I/O2L P17 I/O16R I/O16L VDDQR R1 R2 R3 NC R4 TRST BA4R BA0R R5 R6 R7 A8R R8 NC R9 VDD R10 CLKR CNTENR A4R R11 R12 R13 NC R14 I/O1L R15 VSS R16 NC R17 VSS T1 NC T2 I/O17R TCK T3 T4 BA5R BA1R T5 T6 A9R T7 NC T8 CE0R T9 VSS T10 ADSR T11 A5R T12 A1R T13 VSS T14 VDDQL I/O0R VDDQR T15 T16 T17 NC U1 I/O17L VDDQL TMS U2 U3 U4 NC U5 BA2R U6 A10R U7 UBR U8 CE1R U9 VSS U10 R/WR A6R U12 A2R U13 VSS U14 NC U15 VSS U16 NC U17 VSS NC PL/FTR NC BA3R A11R A7R LBR VDD OER A3R A0R VDD OPTR NC I/O0L , 5629 drw 02c NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.42 2 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Configuration (1,2,3,4) (con't.) 70V7319BC BC-256(5) 256-Pin BGA Top View(6) 11/20/01 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 NC B1 TDI B2 NC B3 BA5L B4 BA2L B5 A11L B6 A8L B7 NC B8 CE1L B9 OEL CNTENL B10 B11 A5L B12 A2L B13 A0L B14 NC B15 NC B16 NC C1 NC C2 TDO C3 NC C4 BA3L C5 BA0L C6 A9L C7 UBL C8 CE0L R/WL REPEATL C9 C10 C11 A4L C12 A1L C13 VDD C14 NC C15 NC C16 NC D1 I/O9L D2 VSS D3 BA4L D4 BA1L D5 A10L D6 A7L D7 NC D8 LBL D9 CLKL ADSL D10 D11 A6L D12 A3L D13 OPTL D14 NC D15 I/O8L D16 NC E1 I/O9R E2 NC E3 PL/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 NC E14 NC E15 I/O8R E16 I/O10R I/O10L F1 F2 NC F3 VDDQL F4 VDD F5 VDD F6 VSS F7 VSS F8 VSS F9 VSS F10 VDD F11 VDD VDDQR F12 F13 NC F14 I/O7L F15 I/O7R F16 I/O11L G1 NC G2 I/O11R VDDQL G3 G4 VDD G5 VSS G6 VSS G7 VSS G8 VSS G9 VSS G10 VSS G11 VDD VDDQR I/O6R G12 G13 G14 NC G15 I/O6L G16 NC H1 NC H2 I/O12L VDDQR H3 H4 VSS H5 VSS H6 VSS H7 VSS H8 VSS H9 VSS H10 VSS H11 VSS H12 VDDQL I/O5L H13 H14 NC H15 NC H16 NC J1 I/O12R J2 J3 NC VDDQR J4 VSS J5 VSS J6 VSS J7 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VDDQL J13 NC J14 NC J15 I/O5R J16 I/O13L I/O14R I/O13R VDDQL K1 K2 K3 K4 VSS K5 VSS K6 VSS K7 VSS K8 VSS K9 VSS K10 VSS K11 VSS K12 VDDQR I/O4R I/O3R K13 K14 K15 I/O4L K16 NC L1 NC L2 I/O14L VDDQL L3 L4 VSS L5 VSS L6 VSS L7 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VDDQR L13 NC L14 NC L15 I/O3L L16 I/O15L M1 NC M2 I/O15R VDDQR M3 M4 VDD M5 VSS M6 VSS M7 VSS M8 VSS M9 VSS M10 VSS M11 VDD M12 VDDQL I/O2L M13 M14 NC M15 I/O2R M16 I/O16R I/O16L N1 N2 NC N3 VDDQR N4 VDD N5 VDD N6 VSS N7 VSS N8 VSS N9 VSS N10 VDD N11 VDD N12 VDDQL I/O1R N13 N14 I/O1L N15 NC N16 NC P1 I/O17R P2 NC P3 PL/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL P4 P5 P6 P7 P8 P9 P10 P11 P12 VDD P13 NC P14 I/O0R P15 NC P16 NC R1 I/O17L TMS R2 R3 BA4R BA1R R4 R5 A10R R6 A7R R7 NC R8 LBR R9 CLKR ADSR R10 R11 A6R R12 A3R R13 NC R14 NC R15 I/O0L R16 NC T1 NC T2 TRST T3 NC T4 BA3R BA0R T5 T6 A9R T7 UBR T8 CE0R R/WR REPEATR T9 T10 T11 A4R T12 A1R T13 OPTR T14 NC T15 NC T16 , NC TCK NC BA5R BA2R A11R A8R NC CE1R OER CNTENR A5R A2R A0R NC NC 5629 drw 02d NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. , 6.42 3 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Configuration 11/20/01 (1,2,3,4,7) (con't.) 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PL/FTL NC NC NC BA5L BA4L BA3L BA2L BA1L BA0L A11L A10L A9L A8L A7L UBL LBL CE1L CE0L VDD VSS CLKL OEL R/WL ADSL CNTENL REPEATL A6L A5L A4L A3L A2L A1L A0L VDD VSS VSS VDDQR VSS I/O9L I/O9R I/O10L I/O10R I/O11L I/O11R VDDQL VSS I/O12L I/O12R VDDQR VSS VDD VDD VSS VSS VDDQL VSS I/O13R I/O13L I/O14R I/O14L VDDQR VSS I/O15R I/O15L I/O16R I/O16L I/O17R I/O17L VSS VDDQL NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 70V7319DD DD-144(5) 144-Pin TQFP Top View(6) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 OPTL VDDQR VSS I/O8L I/O8R I/O7L I/O7R I/O6L I/O6R VSS VDDQL I/O5L I/O5R VSS VDDQR VDD VDD VSS VSS VSS VDDQL I/O4R I/O4L I/O3R I/O3L VSS VDDQR I/O2R I/O2L I/O1R I/O1L I/O0R I/O0L VSS VDDQL OPTR , PT/FTR NC NC NC BA5R BA4R BA3R BA2R BA1R BA0R A11R A10R A9R A8R A7R UBR LBR CE1R CE0R VDD VSS CLKR OER R/WR ADSR CNTENR REPEATR A6R A5R A4R A3R A2R A1R A0R VDD VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 5629 drw 02a NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 20mm x 20mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 7. Due to the limited pin count, JTAG is not supported in the DD-144 package. 6.42 4 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port CE0L, CE1L R/WL OEL BA0L - BA5L A0L - A11L I/O0L - I/O17L CLKL PL/FTL ADSL CNTENL REPEATL LBL, U BL VDDQL OPTL VDD VSS TDI TDO TCK TMS TRST Right Port CE0R, CE1R R/WR OER BA0R - BA5R A0R - A11R I/O0R - I/O17R CLKR PL/FTR ADSR CNTENR REPEATR LBR, UBR VDDQR OPTR Chip Enables Read/Write Enable Output Enable Bank Address(4) Address Data Input/Output Clock Pipeline/Flow-Through Address Strobe Enable Counter Enable Counter Repeat (3) Names Byte Enables (9-bit bytes) Power (I/O Bus) (3.3V or 2.5V)(1) Option for selecting VDDQX(1,2) Power (3.3V)(1) Ground (0V) Test Data Input Test Data Output Test Logic Clock (10MHz) Test Mode Select Reset (Initialize TAP Controller) 5629 tbl 01 NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and address controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. When REPEATX is asserted, the counter will reset to the last valid address loaded via ADSX. 4. Accesses by the ports into specific banks are controlled by the bank address pins under the user's direct control: each port can access any bank of memory with the shared array that is not currently being accessed by the opposite port (i.e., BA0L - BA5L ≠ BA0R - BA5R). In the event that both ports try to access the same bank at the same time, neither access will be valid, and data at the two specific addresses targeted by the ports within that bank may be corrupted (in the case that either or both ports are writing) or may result in invalid output (in the case that both ports are trying to read). 6.42 5 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table I—Read/Write and Enable Control OE3 X X X X X X L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ X CE0 H X L L L L L L L X CE1 X L H H H H H H H X UB X X H H L L H L L X LB X X H L H L L H L X R/ W X X X L L L H H H X Upper Byte I/O9-17 High-Z High-Z High-Z High-Z DIN DIN High-Z DOUT DOUT High-Z High-Z High-Z High-Z DIN High-Z DIN DOUT High-Z DOUT High-Z (1,2,3,4) Lower Byte I/O0-8 MODE Deselected–Power Down Deselected–Power Down All Bytes Deselected Write to Lower Byte Only Write to Upper Byte Only Write to both Bytes Read Lower Byte Only Read UpperByte Only Read both Bytes Outputs Disabled 5629 tbl 02 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT are set as appropriate for address access. Refer to Truth Table II for details. 3. OE is an asynchronous input signal. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. Truth Table II—Address and Address Counter Control(1,2,7) Address An X X X Previous Address X An An + 1 X Addr Used An An + 1 An + 1 An CLK ↑ ↑ ↑ ↑ ADS L (4) CNTEN X L (5) REPEAT(6) H H H L (4) I/O(3) DI/O (n) DI/O(n+1) DI/O(n+1) DI/O(0) External Address Used MODE H H X Counter Enabled—Internal Address generation External Address Blocked—Counter disabled (An + 1 reused) Counter Set to last valid ADS load 5629 tbl 03 H X NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB/LB and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and UB/LB 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB/LB. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. 7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer to Timing Waveform of Counter Repeat, page 18. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA0L - BA5L ≠ BA0R - BA5R), as this condition will invalidate the access for both ports. Please refer to the functional description on page 19 for details. 6.42 6 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage(1) Grade Commercial Industrial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V VDD 3.3V + 150mV 3.3V + 150mV 5629 tbl 04 Recommended DC Operating Conditions with VDDQ at 2.5V Symbol VDD VDDQ VSS VIH VIH VIL Parameter Core Supply Voltage I/O Supply Voltage Ground Input High Voltage (Address & Control Inputs) Input High Voltage - I/O(3) Input Low Voltage (3) Min. 3.15 2.4 0 1.7 1.7 -0.3 (1) Typ. 3.3 2.5 0 ____ Max. 3.45 2.6 0 VDDQ + 100mV (2) Unit V V V V V V 5629 tb l 05a NOTE: 1. This is the parameter TA. This is the "instant on" case temperature. ____ VDDQ + 100mV(2) 0.7 ____ Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 Unit V NOTES: 1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed. 2. VTERM must not exceed VDDQ + 100mV. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied as indicated above. TBIAS TSTG IOUT -55 to +125 -65 to +150 50 o C C Recommended DC Operating Conditions with VDDQ at 3.3V Symbol Parameter Core Supply Voltage I/O Supply Voltage Ground Input High Voltage (Address & Control Inputs)(3) Input High Voltage - I/O(3) Input Low Voltage (3) Min. 3.15 3.15 0 2.0 2.0 -0.3 (1) Typ. 3.3 3.3 0 ____ Max. 3.45 3.45 0 VDDQ + 150mV (2) Unit V V V V V V 5629 tbl 05b o VDD VDDQ VSS VIH VIH VIL mA 5629 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV. ____ VDDQ + 150mV(2) 0.8 ____ NOTES: 1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed. 2. VTERM must not exceed VDDQ + 150mV. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be supplied as indicated above. 6.42 7 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Capacitance(1) Symbol CIN COUT(3) (TA = +25°C, F = 1.0MHZ) PQFP ONLY Parameter Input Capacitance Output Capacitance Conditions(2) V IN = 3dV VOUT = 3dV Max. 8 10.5 Unit pF pF 5629 tbl 07 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV) 70V7319S Symbol |ILI| |ILO| VOL (3.3V) VOH (3.3V) VOL (2.5V) VOH (2.5V) Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage (2) (1) Test Conditions VDDQ = Max., VIN = 0V to V DDQ CE0 = VIH o r CE1 = VIL, VOUT = 0V to V DDQ IOL = +4mA, VDDQ = Min. IOH = -4mA, VDDQ = Min. IOL = +2mA, VDDQ = Min. IOH = -2mA, VDDQ = Min. Min. ___ Max. 10 10 0.4 ___ Unit µA µA V V V V 5629 tbl 08 ___ ___ Output High Voltage (2) Output Low Voltage (2) (2) 2.4 ___ 0.4 ___ Output High Voltage 2.0 NOTES: 1. At VDD < 2.0V leakages are undefined. 2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details. 6.42 8 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(5) (VDD = 3.3V ± 150mV) 70V7319S200(7) Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) CEL and CER= VIL, Outputs Disabled, f = fMAX(1) CEL = C ER = VIH f = fMAX(1) CE"A" = VIL and C E"B" = VIH(3) Active Port Outputs Disabled, f=fMAX(1) Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and C E"B" > VDD - 0.2V(3) VIN > VDD - 0.2V or VIN < 0.2V Active Port, Outputs Disabled, f = fMAX(1) Test Condition Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND S S S S S S S S S S Typ.(4) 815 ____ 70V7319S166(6) Com'l & Ind Typ. (4) 675 675 275 275 515 515 10 10 515 515 Max. 790 830 340 355 640 660 30 40 640 660 70V7319S133 Com'l & Ind Typ. (4) 550 550 250 250 460 460 10 10 460 460 Max. 645 675 295 310 520 545 30 40 520 545 5629 tbl 09 Max. 950 ____ Unit mA ISB1 340 ____ 410 ____ mA ISB2 690 ____ 770 ____ mA ISB3 10 ____ 30 ____ mA ISB4 690 ____ 770 ____ mA NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6. 166MHz Industrial Temperature not available in BF-208 package. 7. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC-256 package only. 6.42 9 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions (VDDQ - 3.3V/2.5V) Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V/GND to 2.4V GND to 3.0V/GND to 2.4V 2ns 1.5V/1.25V 1.5V/1.25V Figures 1 and 2 5629 tbl 10 2.5V 833Ω DATAOUT 770Ω 5pF* , 3.3V 590Ω 50Ω DATAOUT 50Ω 1.5V/1.25 10pF (Tester) , DATAOUT 435Ω 5pF* 5629 drw 03 Figure 1. AC Output Test load. 5629 drw 04 , Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig. 10.5pF is the I/O capacitance of this device, and 10pF is the AC Test Load Capacitance. 7 6 5 4 ∆tCD (Typical, ns) 3 2 1 • • 20.5 • 30 • 50 80 100 200 , -1 Capacitance (pF) 5629 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load). 6.42 10 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C) 70V7319S200(5) Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRPT tHRPT tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Clock Cycle Time (Flow-Through) Clock Cycle Time (Pipelined) (1) (1) (1) 70V7319S166(3,4) Com'l & Ind Min. 20 6 6 6 2.1 2.1 ____ ____ 70V7319S133(3) Com'l & Ind Min. 25 7.5 7 7 2.6 2.6 ____ ____ Parameter Min. 15 5 5 5 2.0 2.0 ____ ____ Max. ____ Max. ____ Max. ____ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ Clock High Time (Flow-Through) Clock Low Time (Flow-Through)(1) Clock High Time (Pipelined)(2) Clock Low Time (Pipelined)(1) Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS Setup Time ADS Hold Time CNTEN Setup Time CNTEN Hold Time REPEAT Setup Time REPEAT Hold Time Output Enable to Data Valid Output Enable to Output Low-Z Output Enable to Output High-Z Clock to Data Valid (Flow-Through) Clock to Data Valid (Pipelined) (1) (1) ____ ____ ____ ____ ____ ____ ____ ____ ____ 1.5 1.5 ____ 1.5 1.5 ____ 1.5 1.5 ____ 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 ____ 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 ____ 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 4.0 ____ 4.0 ____ 4.2 ____ 0.5 1 ____ 0.5 1 ____ 0.5 1 ____ 3.4 10 3.4 ____ 3.6 12 3.6 ____ 4.2 15 4.2 ____ ____ ____ ____ Data Output Hold After Clock High Clock High to Output High-Z Clock High to Output Low-Z 1 1 0.5 1 1 0.5 1 1 0.5 3.4 ____ 3.6 ____ 4.2 ____ Port-to-Port Delay tCO Clock-to-Clock Offset 5.0 ____ 6.0 ____ 7.5 ____ ns 5629 tbl 11 NOTES: 1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPEX = VIL for that port. 2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPEX. FT/PIPEX should be treated as a DC signal, i.e. steady state during operation. 3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port. 4. 166MHz Industrial Temperature not available in BF-208 package. 5. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC-256 package only. 6.42 11 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Pipelined Operation (ADS Operation) (PL/FT'X' = VIH)(2) tCYC2 tCH2 CLK CE0 tCL2 tSC CE1 tSB UB/LB tHC tSC (3) tHC tHB tSB (5) tHB R/W tSW tSA tHW tHA An + 1 (1 Latency) tCD2 Qn An + 2 tDC Qn + 1 tOHZ tOLZ Qn + 2 (5) ADDRESS (4) An An + 3 DATAOUT tCKLZ (1) (1) OE tOE 5629 drw 06 Timing Waveform of Read Cycle for Flow-through Output (PL/FT"X" = VIL)(2,6) tCYC1 tCH1 CLK CE0 tCL1 tSC CE1 tSB BEn tHC tSC (3) tHC tHB tSB (5) tHB R/W tSW tHW tSA tHA An + 1 tCD1 tDC Qn tCKLZ (1) ADDRESS (4) An An + 2 An + 3 tCKHZ DATAOUT Qn + 1 tOHZ tOLZ Qn + 2 (5) tDC OE tOE NOTES: 1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 2. ADS = VIL, CNTEN and REPEAT = VIH. 3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB/LB = VIH following the next rising edge of the clock. Refer to Truth Table 1. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. If UB/LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 6. "x" denotes Left or Right port. The diagram is with respect to that port. 5629 drw 07 6.42 12 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of a Multi-Device Pipelined Read(1,2) tCH2 CLK tSA ADDRESS(B1) tSC CE0(B1) tCYC2 tCL2 tHA A0 tHC tSC tCD2 tHC tCD2 Q0 tDC Q1 tDC A4 tCKLZ A5 tCKHZ tCD2 Q3 tCKHZ A6 A1 A2 A3 A4 A5 A6 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 A3 tSC CE0(B2) tHC tSC tHC tCD2 tCKHZ Q2 tCKLZ tCKLZ 5629 drw 08 tCD2 Q4 DATAOUT(B2) Timing Waveform of a Multi-Device Flow-Through Read(1,2) tCH1 CLK tSA ADDRESS(B1) tSC tHA A0 tHC tSC tCD1 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 A3 A4 A5 A6 D0 tDC tCD1 D1 tDC tCKLZ (1) tCYC1 tCL1 A1 A2 A3 A4 A5 A6 CE0(B1) tHC tCKHZ (1) tCD1 D3 tCKHZ (1) tCD1 D5 tCKLZ (1) tSC CE0(B2) tSC tHC tHC tCD1 DATAOUT(B2) tCKLZ (1) tCKHZ D2 (1) tCD1 tCKLZ (1) tCKHZ D4 (1) NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V7319 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. UB/LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH. 5629 drw 09 6.42 13 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Port A Write to Pipelined Port B Read(1,2,4) CLK"A" tSW R/W"A" tSA BANK ADDRESS AND ADDRESS"A" An tHW tHA tSD DATAIN"A" Dn tHD tCO(3) CLK"B" tCD2 R/W"B" tSW tSA BANK ADDRESS AND ADDRESS"B" An tHW tHA DATAOUT"B" Dn tDC NOTES: 1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 3. If tCO < minimum specified, then operations from both ports are INVALID. If tCO ≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCO + tCYC2 + tCD2). 4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A". 5629 drw 10 Timing Waveform with Port-to-Port Flow-Through Read(1,2,4) CLK "A" tSW tHW R/W "A" tSA BANK ADDRESS AND ADDRESS "A" DATAIN "A" An tHA tSD Dn tHD tCO(3) CLK "B" tCD1 R/W "B" tSW tSA BANK ADDRESS AND ADDRESS "B" DATAOUT "B" tDC An tHW tHA Dn tDC 5622 drw 11 NOTES: 1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 3. If tCO < minimum specified, then operations from both ports are INVALID. If tCO ≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will be tCO + tCD1). 4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A". 6.42 14 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read tCYC2 (OE = VIL)(2) tCH2 tCL2 CLK CE0 tSC CE1 tSB UB/LB tHC tHB tSW tHW R/W tSW tHW ADDRESS (3) An tSA tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 DATAIN (1) tCD2 Qn tCKHZ tCKLZ tCD2 Qn + 3 DATAOUT READ NOP (4) WRITE READ 5629 drw 12 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, UB/LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2) tCH2 CLK CE0 tCYC2 tCL2 tSC CE1 tSB UB/LB tHC tHB tSW tHW R/W tSW tHW ADDRESS (3) An tSA tHA An +1 An + 2 tSD tHD An + 3 An + 4 An + 5 DATAIN (1) tCD2 Qn tOHZ (4) Dn + 2 Dn + 3 tCKLZ tCD2 Qn + 4 DATAOUT OE 5629 drw 13 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, UB/LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows. READ WRITE READ 6.42 15 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2) tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tSB UB/LB tHC tHB tSW tHW R/W tSW tHW ADDRESS (3) tSA DATAIN (1) An tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 tCD1 Qn tDC READ tCD1 Qn + 1 tCKHZ NOP (4) tCD1 tCD1 Qn + 3 tDC READ 5629 drw 14 DATAOUT tCKLZ WRITE Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2) tCYC1 tCH1 tCL1 CLK CE0 tSC CE1 tSB UB/LB tHC tHB tSW tHW R/W ADDRESS (3) tSW tHW An tSA tHA An +1 An + 2 tSD tHD Dn + 2 (1) An + 3 An + 4 An + 5 DATAIN tCD1 Qn tOHZ OE Dn + 3 tDC tOE tCD1 tCKLZ tCD1 Qn + 4 tDC DATAOUT READ WRITE READ 5629 drw 15 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, UB/LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 16 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2 An tSAD tHAD ADS tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) Qx tDC Qn Qn + 1 Qn + 2(2) Qn + 3 READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 5629 drw 16 Timing Waveform of Flow-Through Read with Address Counter Advance(1) tCH1 CLK tSA ADDRESS tHA tCYC1 tCL1 An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 5629 drw 17 Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 NOTES: 1. CE0, OE, UB/LB = VIL; CE1, R/W, and REPEAT = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 6.42 17 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs)(1,6) tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2 An INTERNAL(3) ADDRESS tSAD tHAD ADS An(5) An + 1 An + 2 An + 3 An + 4 tSCN tHCN CNTEN tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 5629 drw 18 Timing Waveform of Counter Repeat for Flow Through Mode(2,6,7) tCYC2 CLK tSA tHA ADDRESS INTERNAL(3) ADDRESS ADS An An tSAD tHAD tSW tHW An+1 An+2 An+2 An An+1 An+2 An+2 R/W tSCN tHCN CNTEN (4) REPEAT tSRPT tHRPT tSD tHD DATAIN D0 D1 D2 D3 tCD1 DATAOUT WRITE TO ADS ADDRESS An ADVANCE COUNTER WRITE TO An+1 ADVANCE COUNTER WRITE TO An+2 HOLD COUNTER WRITE TO An+2 An REPEAT READ LAST ADS ADDRESS An An+1 ADVANCE COUNTER READ An+1 An+2 , An+2 HOLD COUNTER READ An+2 ADVANCE COUNTER READ An+2 5629 drw 19 NOTES: 1. CE0, UB/LB, and R/W = VIL; CE1 and REPEAT = VIH. 2. CE0, UB/LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid ADS load will be accessed. For more information on REPEAT function refer to Truth Table II. 5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. 6. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. 7. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations. 6.42 18 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Functional Description The IDT70V7319 is a high-speed 256Kx18 (4 Mbit) synchronous Bank-Switchable Dual-Ported SRAM organized into 64 independent 4Kx18 banks. Based on a standard SRAM core instead of a traditional true dual-port memory core, this bank-switchable device offers the benefits of increased density and lower cost-per-bit while retaining many of the features of true dual-ports. These features include simultaneous, random access to the shared array, separate clocks per port, 166 MHz operating speed, full-boundary counters, and pinouts compatible with the IDT70V3319 (256Kx18) dual-port family. The two ports are permitted independent, simultaneous access into separate banks within the shared array. Access by the ports into specific banks are controlled by the bank address pins under the user's direct control: each port can access any bank of memory with the shared array that is not currently being accessed by the opposite port (i.e., BA0L - BA5L ≠ BA0R - BA5R). In the event that both ports try to access the same bank at the same time, neither access will be valid, and data at the two specific addresses targeted by the ports within that bank may be corrupted (in the case that either or both ports are writing) or may result in invalid output (in the case that both ports are trying to read). The IDT70V7319 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal setup and hold times on address, data and all critical control inputs. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry on each port (individually controlled) to reduce static power consumption. Dual chip enables allow easier banking of multiple IDT70V7319s for depth expansion configurations. Two cycles are required with CE0 LOW and CE1 HIGH to read valid data on the outputs. Depth and Width Expansion The IDT70V7319 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70V7319 can also be used in applications requiring expanded width, as indicated in Figure 4. Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 36-bits or wider. BA6(1) IDT70V7319 CE0 CE1 VDD IDT70V7319 CE0 CE1 VDD Control Inputs Control Inputs IDT70V7319 CE1 CE0 IDT70V7319 CE1 CE0 BE, R/W, OE, CLK, ADS, REPEAT, CNTEN Control Inputs Control Inputs 5629 drw 20 , Figure 4. Depth and Width Expansion with IDT70V7319 NOTE: 1. In the case of depth expansion, the additional address pin logically serves as an extension of the bank address. Accesses by the ports into specific banks are controlled by the bank address pins under the user's direct control: each port can access any bank of memory within the shared array that is not currently being accessed by the opposite port (i.e., BA0L - BA6L ≠ BA0R - BA6R). In the event that both ports try to access the same bank at the same time, neither access will be valid, and data at the two specific addresses targeted by the parts within that bank may be corrupted (in the case that either or both parts are writing) or may result in invalid output (in the case that both ports are trying to read). 6.42 19 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges JTAG Timing Specifications tJF TCK tJCL tJCYC tJR tJCH Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO TRST 5629 drw 21 tJH tJDC tJRSR tJCD , tJRST Figure 5. Standard JTAG Timing NOTES: 1. Device inputs = All device inputs except TDI, TMS, TRST, and TCK. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical Characteristics(1,2,3,4) 70V7319 Symbol tJCYC tJCH tJCL tJR tJF tJRST tJRSR tJCD tJDC tJS tJH Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold Min. 100 40 40 ____ ____ Max. ____ Units ns ns ns ns ns ns ns ns ns ns ns 5629 tbl 12 ____ ____ 3 3 (1) (1) 50 50 ____ ____ ____ 25 ____ ____ 0 15 15 ____ NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. 6.42 20 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) Value 0x0 0x309 0x33 1 Reserved for version number Defines IDT part number Allows unique identification of device vendor as IDT Indicates the presence of an ID register 5629 tbl 13 Description Scan Register Sizes Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) Bit Size 4 1 32 Note (3) 5629 tbl 14 System Interface Parameters Instruction EXTEST BYPASS IDCODE Code 0000 1111 0010 0100 Description Forces contents of the bound ary scan cells onto the device outputs (1). Places the boundary scan registe r (BSR) between TDI and TDO. Places the bypass registe r (BYR) between TDI and TDO. Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. Places the bypass register (BYR) be tween TDI and TDO. Forces all device output drivers to a High-Z state. Uses BYR. Forces contents of the bound ary scan cells onto the device outputs. Places the bypass registe r (BYR) between TDI and TDO. Places the boundary scan registe r (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) and outputs(1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the b oundary scan cells via the TDI. Several combinations are reserved. Do not use codes other than those identified above. 5629 tbl 15 HIGHZ CLAMP SAMPLE/PRELOAD 0011 0001 RESERVED All other codes NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, TRST, and TCK. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative. 6.42 21 IDT70V7319S High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank I BF DD BC 200 166 133 S Commercial (0°C to +70°C) Industrial (-40°C to +85°C) 208-pin fpBGA (BF-208) 144-pin TQFP (DD-144) 256-pin BGA (BC-256) Commercial Only(1) Commercial & Industrial(2) Speed in Megahertz Commercial & Industrial Standard Power 70V7319 4Mbit (256K x 18-Bit) Synchronous Bank-Switchable Dual-Port RAM 5629 drw 22 NOTES: 1. Available in BC-256 package only. 2. Industrial Temperature at 166Mhz not available in BF-208 package. Datasheet Document History: 1/5/00: 6/20/01: Initial Public Offering Page 1 Added JTAG information for TQFP package Page 4 & 22 Changed TQFP package from DA to DD Corrected Pin number on TQFP package from 100 to 110 Page 20 Increased tJCD from 20ns to 25ns Page 4 Changed body size for DD package from 22mm x 22mm x1.6mm to 20mm x 20mm x 1.4mm Page 9 Changed ISB3 values for commercial and industrial DC Electrical Characteristics Page 2, 3 & 4 Added date revision for pin configurations Page 11 Changed tOE value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05 Page 1 & 22 Replaced TM logo with ® logo Page 1, 9, 11 & 22 Added 200MHz specification Page 9 Tightened power numbers in DC Electrical Characteristics Page 14 Changed waveforms to show INVALID operation if tCO < minimum specified Page 1 - 22 Removed "Preliminary" status Page 9, 11 & 22 Designated 200Mhz speed grade available in BC-256 package only. 8/6/01: 11/20/01: 3/18/02: 12/4/02: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-5166 fax: 408-492-8674 www.idt.com 6.42 22 for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.