IDT70V9199L6PFI

HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ IDT70V9199/099L ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6/7.5/9/12ns (max.) – Industrial: 9ns (max.) Low-power operation – IDT70V9199/099L Active: 500mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Dual chip enables allow for depth expansion without additional logic ◆ ◆ ◆ ◆ ◆ Counter enable and reset features Full synchronous operation on both ports – 3.5ns setup to clock and 0ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 6.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 10ns cycle time, 100MHz operation in Pipelined output mode LVTTL- compatible, single 3.3V (±0.3V) power supply Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in a 100-pin Thin Quad Flatpack (TQFP) Functional Block Diagram R/WL OEL CE0L CE1L R/WR OER CE0R CE1R 1 0 0/1 1 0 0/1 FT/PIPEL 0/1 1 0 0 1 0/1 FT/PIPER . I/O0L - I/O8L(1) I/O0R - I/O8R(1) I/O Control I/O Control A16L A0L CLKL ADSL CNTENL CNTRSTL NOTE: 1. I/O0X - I/O7X for IDT70V9099. A16R Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR ADSR CNTENR CNTRSTR 4859 drw 01 APRIL 2003 1 ©2003 Integrated Device Technology, Inc. DSC-4859/3 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges The IDT70V9199/099 is a high-speed128K x9/x8 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. Description: With an input data register, the IDT70V9199/099 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 500mW of power. Pin Configuration(1,2,3) 04/02/03 Index NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L A16L VDD NC NC NC NC CE0L CE1L CNTRSTL R/WL OEL FT/PIPEL NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 2 3 73 72 4 71 5 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 70 69 68 67 66 NC NC A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL VSS V SS ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R NC 70V9199PF PN100-1(4) 100-Pin TQFP Top View(5) 65 64 63 62 61 60 59 58 57 56 55 54 53 52 24 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R VSS NC NC NC NC CE0R CE1R . CNTRSTR R/WR OER FT/PIPER GND NC 4859 drw 02 NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. VSS I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L VSS I/O1L I/O0L VDD VSS I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R NC NC 6.42 2 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3)(con't.) 04/04/03 Index NC NC A 7L A 8L A9L A 10L A11L A12L A13L A14L A15L A16L VDD NC NC NC NC CE 0L CE 1L CNTRSTL R/WL OEL FT/PIPEL NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 74 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 NC NC A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL VSS ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R NC NC 70V9099PF PN100-1(4) 100-Pin TQFP Top View(5) 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R VSS NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER VSS NC 4859 drw 02a NOTES: 1. All V DD pins must be connected to power supply. 2. All V SS pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. VSS NC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L VSS I/OIL I/O0L VDD VSS I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R I/O7R NC NC NC 6.42 3 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port CE0L, CE1L R/WL OEL A0L - A16L I/O0L - I/O8L CLKL ADSL CNTENL CNTRSTL FT/PIPEL (1) Right Port CE0R, CE1R R/WR OER A0R - A16R I/O0R - I/O8R CLKR ADSR CNTENR CNTRSTR FT/PIPER VDD VSS (1) Names Chip Enables Read/Write Enable Output Enable Address Data Input/Output Clock Address Strobe Enable Counter Enable Counter Reset Flow-Through / Pipeline Power (3.3V) Ground (0V) 4859 tbl 01 NOTE: 1. I/O0X - I/O7X for IDT70V9099. Truth Table I—Read/Write and Enable Control(1,2,3) OE X X X L H CLK ↑ ↑ ↑ ↑ X CE0 H X L L L CE1 X L H H H R/W X X L H X I/O0-8(4) High-Z High-Z DATAIN DATAOUT High-Z Deselected–Power Down Deselected–Power Down Write Read Outputs Disabled 4859 tbl 02 MODE NOTES: 1. "H" = VIH, "L" = V IL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 4. I/O0 - I/O7 for IDT70V9099. Truth Table II—Address Counter Control(1,2) External Address X An An X Previous Internal Address X X Ap Ap Internal Address Used 0 An Ap Ap + 1 MODE CLK ↑ ↑ ↑ ↑ ADS X L (4) CNTEN X X H L (5) CNTRST L(4) H H H I/O(3) DI/O(0) DI/O(n) DI/O(p) DI/O(p+1) Counter Reset to Address 0 External Address Loaded into Counter External Address Blocked—Counter disabled (Ap reused) Counter Enabled—Internal Address generation 4859 tbl 03 H H NOTES: 1. "H" = VIH, "L" = V IL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0 and CE1. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE 1. 6.42 4 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage(1) Grade Commercial Industrial Ambient Temperature(2) 0OC to +70OC -40OC to +85OC GND 0V 0V VDD 3.3V + 0.3V 3.3V + 0.3V 4859 tbl 04 Recommended DC Operating Conditions Symbol V DD V SS V IH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3 (1) Typ. 3.3 0 ____ ____ Max. 3.6 0 V DD+0.3V 0.8 (2) Unit V V V V 4859 tbl 05 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VDD +0.3V. Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Junction Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 Unit V Capacitance(1) Symbol CIN (TA = +25°C, f = 1.0MHZ) Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF 4859 tbl 07 TBIAS(3) TSTG TJN IOUT -55 to +125 -65 to +150 +150 50 o C C C COUT(3) o o mA 4859 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V. 3. Ambient Temperature Under DC Bias. No AC Conditions. Chip deselect. NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references C I/O. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V) 70V9199/099L Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current (1) Test Conditions VDD = 3.6V, VIN = 0V to VDD CE = VIH o r CE1 = VIL, VOUT = 0V to VDD IOL = +4mA IOH = -4mA Min. ___ ___ ___ Max. 5 5 0.4 ___ Unit µA µA V V 4859 tbl 08 Output Leakage Current Output Low Voltage Output High Voltage 2.4 NOTE: 1. At VDD < 2.0V input leakages are undefined. 6.42 5 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V) 70V9199/099L6 Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) Test Condition CEL and CER= VIL, Outputs Disabled, f = fMAX(1) CEL = CER = VIH f = fMAX(1) Version COM'L IND COM'L IND L L L L L L L L L L ____ ____ ____ ____ 70V9199/099L7 Com'l Only Typ.(4) 200 ____ 70V9199/099L9 Com'l & Ind Typ.(4) 175 180 40 50 110 110 0.4 0.4 100 100 Max. 230 240 65 70 145 155 2 2 140 155 70V9199/099L12 Com'l Only Typ.(4) 150 ____ Typ.(4) 220 ____ Max. 280 ____ Max. 250 ____ Max. 200 ____ Unit mA ISB1 60 ____ 85 ____ 50 ____ 75 ____ 30 ____ 50 ____ mA ISB2 COM'L CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, IND f=fMAX(1) Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) VIN > VDD - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = fMAX(1) COM'L IND COM'L IND 145 ____ 185 ____ 130 ____ 165 ____ 95 ____ 130 ____ mA ISB3 0.4 ____ 2 ____ 0.4 ____ 2 ____ 0.4 ____ 2 ____ mA ISB4 145 180 130 160 90 ____ 125 ____ mA NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. I DD DC(f=0) = 90mA (Typ). 5. CEX = V IL means CE 0X = V IL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 4859 tbl 09 6.42 6 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1, 2, and 3 4859 tbl 10 3.3V 590Ω DATAOUT 435Ω 30pF DATAOUT 435Ω 3.3V 590Ω 5pF* 4859 drw 03 4859 drw 04 Figure 1. AC Output Test load. Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig. 8 7 6 5 tCD1, tCD2 (Typical, ns) 4 3 2 1 0 -1 - 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 4859 drw 05 . Figure 3. Typical Output Derating (Lumped Capacitive Load). 6.42 7 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C) 70V9199/099L6 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Clock Cycle Time (Flow-Through) Clock Cycle Time (Pipelined) (2) (2) 70V9199/099L7 Com'l Only Min. 22 12 7.5 7.5 5 5 ____ ____ 70V9199/099L9 Com'l & Ind Min. 25 15 12 12 6 6 ____ ____ 70V9199/099L12 Com'l Only Min. 30 20 12 12 8 8 ____ ____ Parameter (2) Min. 19 10 6.5 6.5 4 4 ____ ____ Max. ____ ____ ____ ____ ____ ____ Max. ____ ____ ____ ____ ____ ____ Max. ____ ____ ____ ____ ____ ____ Max. ____ ____ ____ ____ ____ ____ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock High Time (Flow-Through) Clock Low Time (Flow-Through) Clock High Time (Pipelined) Clock Low Time (Pipelined) Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS S etup Time ADS Hold Time CNTEN S etup Time CNTEN Hold Time CNTRST Setup Time CNTRST Hold Time Output Enable to Data Valid Output Enable to Output Low-Z (2) (2) (2) 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 ____ 4 0 4 0 4 0 4 0 4 0 4 0 4 0 ____ 4 1 4 1 4 1 4 1 4 1 4 1 4 1 ____ 4 1 4 1 4 1 4 1 4 1 4 1 4 1 ____ 6.5 ____ 7.5 ____ 9 ____ 12 ____ (1) (1) (2) 2 1 ____ ____ 2 1 ____ ____ 2 1 ____ ____ 2 1 ____ ____ Output Enable to Output High-Z 7 15 6.5 ____ 7 18 7.5 ____ 7 20 9 ____ 7 25 12 ____ Clock to Data Valid (Flow-Through) Clock to Data Valid (Pipelined) (2) Data Output Hold After Clock High Clock High to Output High-Z(1) Clock High to Output Low-Z(1) 2 2 2 2 2 2 2 2 2 2 2 2 9 ____ 9 ____ 9 ____ 9 ____ Port-to-Port Delay tCWDD tCCS Write Port Clock High to Read Data Delay Clock-to-Clock Setup Time ____ ____ 24 8 ____ ____ 28 10 ____ ____ 35 15 ____ ____ 40 15 ns ns 4859 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL. 6.42 8 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,6) tCYC1 tCH1 CLK CE0 tCL1 tSC CE1 tHC tSC tHC R/W tSW tHW tSA tHA An + 1 tCD1 tDC Qn tCKLZ (1) ADDRESS (5) An An + 2 An + 3 tCKHZ (1) DATAOUT Qn + 1 (1) Qn + 2 tOLZ (1) tOHZ tDC OE (2) tOE .. 4859 drw 06 Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH)(3,6) tCYC2 tCH2 CLK CE0 tCL2 tSC CE1 tHC tSC (4) tHC R/W tSW tSA tHW tHA An + 1 (1 Latency) tCD2 Qn tCKLZ(1) An + 2 tDC Qn + 1 tOHZ(1) tOLZ(1) Qn + 2(6) An + 3 ADDRESS (5) An DATAOUT OE (2) tOE 4859 drw 07 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. 'X' here denotes Left or Right port. The diagram is with respect to that port. 6.42 9 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of a Bank Select Pipelined Read(1,2) tCH2 CLK tSA ADDRESS(B1) tSC CE0(B1) tCYC2 tCL2 tHA A0 tHC tSC tCD2 tHC tCD2 Q0 tDC tCKHZ(3) Q1 tDC A3 A4 tCD2 Q3 tCKLZ (3) A1 A2 A3 A4 A5 A6 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 tCKHZ (3) A5 A6 A2 tSC tHC CE0(B2) tSC tHC tCD2 tCKHZ Q2 (3) tCD2 tCKLZ (3) 4859 drw 08 DATAOUT(B2) tCKLZ(3) Q4 Timing Waveform with Port-to-Port Flow-Through Read(4,5,7) CLK "A" tSW tHW R/W "A" tSA ADDRESS "A" tHA NO MATCH MATCH tSD DATAIN "A" VALID tHD tCCS CLK "B" (6) tCD1 R/W "B" tSW tSA ADDRESS "B" tHW tHA NO MATCH MATCH tCWDD DATAOUT "B" tDC (6) tCD1 VALID VALID tDC 4859 drw 09 NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9199/099 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. OE and ADS = VIL; CE1(B1) , CE1(B2) , R/W, CNTEN , and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + t CD1. tCWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A". 6.42 10 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW ADDRESS (4) An tSA tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 DATAIN (2) tCD2 Qn READ tCKHZ (1) tCKLZ (1) tCD2 Qn + 3 DATAOUT NOP (5) WRITE READ 4859 drw 10 Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3) tCH2 CLK CE0 tCYC2 tCL2 tSC CE1 tHC tSW tHW R/W tSW tHW ADDRESS (4) An tSA tHA An +1 An + 2 tSD tHD An + 3 An + 4 An + 5 DATAIN (2) tCD2 Qn tOHZ(1) Dn + 2 Dn + 3 tCKLZ(1) tCD2 Qn + 4 DATAOUT OE READ WRITE READ 4859 drw 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0 and ADS = VIL; CE1, CNTEN , and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 11 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3) tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tHC tSW tHW R/W tSW tHW ADDRESS (4) tSA DATAIN (2) An tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 tCD1 Qn tDC READ tCD1 Qn + 1 tCKHZ NOP (5) (1) tCD1 tCD1 Qn + 3 tDC 4859 drw 12 DATAOUT tCKLZ WRITE (1) READ Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W ADDRESS (4) tSW tHW An tSA tHA An +1 An + 2 tSD tHD Dn + 2 (2) An + 3 An + 4 An + 5 DATAIN tCD1 Qn tOHZ OE (1) Dn + 3 tDC tOE tCD1 (1) tCD1 Qn + 4 tDC DATAOUT tCKLZ READ WRITE READ 4859 drw 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0 and ADS = VIL; CE1, CNTEN , and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 12 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 CLK tSA ADDRESS An tSAD tHAD ADS tCYC2 tCL2 tHA tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) Qx tDC Qn Qn + 1 Qn + 2(2) Qn + 3 READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 4859 drw 14 Timing Waveform of Flow-Through Read with Address Counter Advance(1) tCH1 CLK tSA ADDRESS tHA tCYC1 tCL1 An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 4859 drw 15 Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 NOTES: 1. CE0 and OE = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 6.42 13 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1) tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2 An INTERNAL(3) ADDRESS tSAD tHAD ADS An(7) An + 1 An + 2 An + 3 An + 4 CNTEN(7) tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 4856 drw 16 Timing Waveform of Counter Reset (Pipelined Outputs)(2) tCH2 CLK tSA tHA ADDRESS(4) INTERNAL(3) ADDRESS R/W ADS CNTEN tCYC2 tCL2 An Ax (6) tSW tHW An + 1 An + 2 0 1 An An + 1 tSAD tHAD tSCN tHCN tSRST tHRST CNTRST tSD tHD D0 Q0 Q1 READ ADDRESS n READ ADDRESS n+1 4856 drw 17 DATAIN DATAOUT(5) COUNTER RESET (6) Qn WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 NOTES: 1. CE0 and R/W = VIL; CE 1 and CNTRST = VIH. 2. CE0 = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written to during this cycle. 6.42 14 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Functional Description The IDT70V9199/099 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to staff the operation of the address counters for fast interleaved memory applications. CE0 = VIL and CE1 = VIH for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70V9199/099's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 = VIH or CE1 = VIL to re-activate the outputs. Depth and Width Expansion The IDT70V9199/099 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the varioius chip enables in order to expand two devices in depth. The IDT70V9199/099 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 18/16-bit or wider applications. A17 IDT70V9199/099 CE0 CE1 VDD IDT70V9199/099 CE0 CE1 VDD Control Inputs Control Inputs IDT70V9199/099 CE1 CE0 IDT70V9199/099 CE1 CE0 CNTRST CLK ADS CNTEN R/W OE Control Inputs Control Inputs 4859 drw 18 Figure 4. Depth and Width Expansion with IDT70V9199/099 6.42 15 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 99 Speed A Package A Process/ Temperature Range Blank I (1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PF 100-pin TQFP (PN100-1) 6 7 9 12 L Commercial Only Commercial Only Commercial & Industrial Commercial Only Low Power Speed in nanoseconds . 70V9199 1152K (128K x 9-Bit) Synchronous Dual-Port RAM 70V9099 1024K (128K x 8-Bit) Synchronous Dual-Port RAM 4859 drw 19 NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. IDT Clock Solution for IDT70V9199/099 Dual-Port Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage I/O Input Capacitance Dual-Port Clock Specifications Input Duty Cycle Requirement Maximum Frequency Jitter Tolerance IDT PLL Clock Devices IDT2305 IDT2308 IDT2309 IDT Non-PLL Clock Devices FCT3805 FCT3805D/E FCT3807 FCT3807D/E 4859 tbl12 70V9199/099 3.3 LVTTL 9pF 40% 100 150ps 6.42 16 IDT70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History 9/30/99: 11/12/99: 01/10/01: Initial Public Release Replaced IDT logo Page 3 Changed information in Truth Table II Page 4 Increased storage temperature parameters Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes Removed Preliminary status Consolidate multiple devices into one datasheet Changed naming conventions from VCC to VDD and from GND to VSS Page 2 & 3 Added date revision to pin configurations Page 5 Added junction temperature to Absolute Maximum Ratings Table Added Ambient Temperature footnote Page 1, 6 & 16 Added 6ns speed grade Page 6 Added updated DC power numbers to the DC Electrical Characteristics Table Page 8 Added 6ns speed AC timing numbers and changed tOE to be equal to tCD2 in the AC Electrical CharacteristicsTable Page 16 Added IDT Clock Solution Table 04/09/03: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 17