IDT70V9279L7PRFI

HIGH-SPEED 3.3V 32/16K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM Features: ◆ ◆ IDT70V9279/69S/L ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12/15ns (max.) – Industrial: 7.5ns (max.) Low-power operation – IDT70V9279/69S Active: 429mW (typ.) Standby: 3.3mW (typ.) – IDT70V9279/69L Active: 429mW (typ.) Standby: 1.32mW (typ.) Flow-through or Pipelined output mode on either port via the FT/PIPE pin Counter enable and reset features ◆ ◆ ◆ ◆ ◆ ◆ Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 6.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 10ns cycle time, 100MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±0.3V) power supply Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in a 128-pin Thin Quad Flatpack (TQFP) package Functional Block Diagram R/WL UBL CE0L R/WR UBR CE0R CE1L LBL OEL 1 0 0/1 1 0 0/1 CE1R LBR OER FT/PIPEL 0/1 1b 0bb a 1a 0a 0a 1a a 0b 1b b 0/1 FT/PIPER , I/O8L-I/O15L I/O Control I/O0L-I/O7L I/O Control I/O8R-I/O15R I/O0R-I/O7R A14L(1) A0L CLKL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A14R(1) A0R CLKR ADSL CNTEN L CNTRSTL ADSR CNTENR CNTRSTR 3743 drw 01 NOTE: 1. A14X is a NC for IDT70V9269. MAY 2004 1 ©2004 Integrated Device Technology, Inc. DSC 3743/8 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges The IDT70V9279/69 is a high-speed 32/16K x 16 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. Description: With an input data register, the IDT70V9279/69 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 429mW of power. A10R A11R A12R A13R A14R(1) N/C N/C N/C LBR UBR CE0R CE1R CNTRSTR VDD VSS R/WR OER N/C N/C N/C N/C A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R N/C CNTENR CLKR ADSR VSS VDD ADSL CLKL CNTENL N/C A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L N/C N/C N/C N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 I/O11R 01/15/04 FT/PIPER Vss I/O15R I/O14R I/O13R I/O12R VDD VDD Pin Configuration(2,3,4) 70V9279/69PRF PK-128(5) 128-Pin TQFP Top View(6) 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 I/O10R I/O9R VSS N/C I/O8R N/C N/C I/O7R VDD I/O6R I/O5R I/O4R VSS I/O3R VDD I/O2R I/O1R I/O0R VSS VDD I/O0L I/O1L VSS I/O2L I/O3L VSS I/O4L I/O5L I/O6L I/O7L VDD N/C N/C I/O8L N/C VDD I/O9L I/O10L 3743 drw 02 NOTES: 1. A14X is a NC for IDT70V9269. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground. 4. Package body is approximately 14mm x 20mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. A14L(1) N/C N/C N/C LBL UBL CE0L CE1L CNTRSTL VDD VSS R/WL OEL FT/PIPEL VSS I/O15L I/O14L I/O13L I/O12L VDD VSS I/O11L A10L A11L A12L A13L 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 6.42 2 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port CE0L, CE1L R/ WL OEL A0L - A14L(1) I/O0L - I/O15L CLKL UBL LBL ADSL CNTENL CNTRSTL FT/PIPEL Right Port CE0R, CE1R R/WR OER A0R - A14R(1) I/O0R - I/O15R CLKR UBR LBR ADSR CNTENR CNTRSTR FT/PIPER VDD VSS Names Chip Enables (3) Read/Write Enable Output Enable Address Data Input/Output Clock Upper Byte Select(2) Lower Byte Select(2) Address Strobe Enable Counter Enable Counter Reset Flow-Through / Pipeline Power (3.3V) Ground (0V) 3743 tbl 01 NOTES: 1. Address A14X is a NC for IDT70V9269. 2. LB and UB are single buffered regardless of state of FT/PIPE. 3. CE0 and CE1 are single buffered when FT/PIPE = VIL, CE0 and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. Truth Table I—Read/Write and Enable Control(1,2,3) OE X X X X X X L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ CE0(5) H X L L L L L L L L CE 1(5) X L H H H H H H H H UB(4) X X H L H L L H L L LB(4) X X H H L L H L L L R/W X X X L L L H H H X Upper Byte I/O8-15 High-Z High-Z High-Z DIN High-Z DATA IN DATAOUT High-Z DATAOUT High-Z Lower Byte I/O0-7 High-Z High-Z High-Z High-Z DATA IN DATA IN High-Z DATAOUT DATAOUT High-Z Deselected–Power Down Deselected–Power Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled 3743 tbl 02 MODE NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 4 LB and UB are single buffered regardless of state of FT/PIPE. 5. CE o and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. 6.42 3 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Truth Table II—Address Counter Control(1,2,3) External Address An X X X Previous Internal Address X An An + 1 X Internal Address Used An An + 1 An + 1 A0 CLK ↑ ↑ ↑ ↑ ADS L(4) H H X CNTEN X L (5) CNTRST H H H L(4) I/O(3) DI/O (n) DI/O(n+1) DI/O(n+1) DI/O(0) External Address Used MODE Counter Enabled—Internal Address generation External Address Blocked—Counter disabled (An + 1 reused) Counter Reset to Address 0 3743 tbl 03 H X NOTES: 1. "H" = VIH, "L" = V IL, "X" = Don't Care. 2. CE 0, LB, UB, and OE = VIL; CE1 and R/ W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB. Recommended Operating Temperature and Supply Voltage(1,2) Grade Commercial Industrial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V VDD 3.3V + 0.3V 3.3V + 0.3V Recommended DC Operating Conditions Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.2 -0.3(1) Typ. 3.3 0 ____ ____ Max. 3.6 0 VDD+0.3V(2) 0.8 Unit V V V V 3743 tbl 05 3743 tbl 04 NOTES: 1. Industrial temperature: for specific speeds, packages and powers contact your sales office. 2. This is the parameter TA. This is the "instant on" case temperature. NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VDD + 0.3V. Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias StorageTemperature Junction Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 Unit V Capacitance(1) Symbol CIN COUT (3) (TA = +25°C, f = 1.0MHZ) Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF 3743 tbl 07 TBIAS(3) TSTG TJN IOUT -55 to +125 -65 to +150 +150 50 o o o C C C mA 3743 tbl 06 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references C I/O. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V. 3. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected. 6.42 4 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V) 70V9279/69S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current (1) 70V9279/69L Min. ___ ___ ___ Test Conditions VDD = 3.6V, VIN = 0V to VDD CE0 = VIH o r CE 1 = VIL, VOUT = 0V to VDD IOL = +4mA IOH = -4mA Min. ___ ___ ___ Max. 10 10 0.4 ___ Max. 5 5 0.4 ___ Unit µA µA V V 3743 tbl 08 Output Leakage Current Output Low Voltage Output High Voltage 2.4 2.4 NOTE: 1. At VDD < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(3,6) (VDD = 3.3V ± 0.3V) 70V9279/69X6 Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) Test Condition CEL and CER= VIL, Outputs Disabled, f = fMAX(1) Version COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ.(4) 220 220 ____ ____ 70V9279/69X7 Com'l Only Typ.(4) 200 200 ____ ____ 70V9279/69X9 Com'l & Ind Typ.(4) 180 180 180 180 50 50 50 50 110 110 110 110 1.0 0.4 1.0 0.4 100 100 100 100 Max. 260 225 270 235 75 65 85 75 170 150 180 160 5 3 5 3 160 140 170 150 3743 tbl 09a Max. 395 350 ____ ____ Max. 335 290 ____ ____ Unit mA ISB1 CEL = CER = VIH f = fMAX(1) 70 70 ____ ____ 145 130 ____ ____ 60 60 ____ ____ 115 100 ____ ____ mA ISB2 COM'L CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, IND f=fMAX(1) Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) VIN > VDD - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = fMAX(1) COM'L IND COM'L IND 150 150 ____ ____ 280 250 ____ ____ 130 130 ____ ____ 240 210 ____ ____ mA ISB3 1.0 0.4 ____ ____ 5 3 ____ ____ 1.0 0.4 ____ ____ 5 3 ____ ____ mA ISB4 140 140 ____ ____ 270 240 ____ ____ 120 120 ____ ____ 230 200 ____ ____ mA NOTES: 1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of VSS to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ). 5. CE X = VIL means CE0X = VIL and CE1X = VIH CE X = VIH means CE0X = VIH or CE1X = V IL CE X < 0.2V means CE 0X < 0.2V and CE1X > VDD - 0.2V CE X > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V 'X' represents "L" for left port or "R" for right port. 6. 'X' in part numbers indicate power rating (S or L). 6.42 5 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(3,6) (VDD = 3.3V ± 0.3V)(Cont'd) 70V9279/69X12 Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) Test Condition CEL and CER= VIL, Outputs Disabled, f = fMAX(1) Version COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ. (4) 150 150 ____ ____ 70V9279/69X15 Com'l Only Typ. (4) 130 130 ____ ____ Max. 240 205 ____ ____ Max. 220 185 ____ ____ Unit mA ISB1 CEL = CER = VIH f = fMAX(1) 40 40 ____ ____ 65 50 ____ ____ 30 30 ____ ____ 55 35 ____ ____ mA ISB2 COM'L CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, IND f=fMAX(1) Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) VIN > VDD - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = fMAX(1) COM'L IND COM'L IND 100 100 ____ ____ 160 140 ____ ____ 90 90 ____ ____ 150 130 ____ ____ mA ISB3 1.0 0.4 ____ ____ 5 3 ____ ____ 1.0 0.4 ____ ____ 5 3 ____ ____ mA ISB4 90 90 ____ ____ 150 130 ____ ____ 80 80 ____ ____ 140 120 ____ ____ mA NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS" at input levels of VSS to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ). 5. CEX = V IL means CE 0X = V IL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V 'X' represents "L" for left port or "R" for right port. 6. 'X' in part numbers indicate power rating (S or L). 3743 tbl 09b 6.42 6 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V Figures 1, 2, and 3 7343 tbl 10 3.3V 590Ω DATAOUT 435Ω 30pF DATAOUT 435Ω 3.3V 590Ω 5pF* 3743 drw 03 3743 drw 04 Figure 1. AC Output Test load. Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig. 8 7 6 tCD1, tCD2 (Typical, ns) 5 4 3 2 1 0 -1 - 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 3743 drw 05 , Figure 3. Typical Output Derating (Lumped Capacitive Load). 6.42 7 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C) 70V9279/69X6 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Clock Cycle Time (Flow-Through) Clock Cycle Time (Pipelined) (2) 70V9279/69X7 Com'l Only Min. 22 12 7.5 7.5 5 5 ____ ____ 70V9279/69X9 Com'l & Ind Min. 25 15 12 12 6 6 ____ ____ Parameter (2) Min. 19 10 6.5 6.5 4 4 ____ ____ Max. ____ ____ ____ ____ ____ ____ Max. ____ ____ ____ ____ ____ ____ Max. ____ ____ ____ ____ ____ ____ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock High Time (Flow-Through)(2) Clock Low Time (Flow-Through) Clock High Time (Pipelined) Clock Low Time (Pipelined) Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS S etup Time ADS Hold Time CNTEN S etup Time CNTEN Hold Time CNTRST Setup Time CNTRST Hold Time Output Enable to Data Valid Output Enable to Output Low-Z (1) (1) (2) (2) (2) 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 ____ 4 0 4 0 4 0 4 0 4 0 4 0 4 0 ____ 4 1 4 1 4 1 4 1 4 1 4 1 4 1 ____ 6.5 ____ 7.5 ____ 9 ____ 2 1 ____ ____ 2 1 ____ ____ 2 1 ____ ____ Output Enable to Output High-Z 7 15 6.5 ____ 7 18 7.5 ____ 7 20 9 ____ Clock to Data Valid (Flow-Through)(2) Clock to Data Valid (Pipelined)(2) Data Output Hold After Clock High Clock High to Output High-Z Clock High to Output Low-Z (1) 2 2 2 2 2 2 2 2 2 9 ____ 9 ____ 9 ____ (1) Port-to-Port Delay tCWDD tCCS Write Port Clock High to Read Data Delay Clock-to-Clock Setup Time ____ ____ 24 9 ____ ____ 28 10 ____ ____ 35 15 ns ns 3743 tbl 11a NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = V IH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC signal, i.e. steady state during operation. 4. 'X' in part number indicates power rating (S or L). 6.42 8 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)(Cont'd) 70V9279/69X12 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Clock Cycle Time (Flow-Through) Clock Cycle Time (Pipelined) (2) (2) 70V9279/69X15 Com'l Only Min. 35 25 12 12 10 10 ____ ____ Parameter (2) Min. 30 20 12 12 8 8 ____ ____ Max. ____ ____ ____ ____ ____ ____ Max. ____ ____ ____ ____ ____ ____ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock High Time (Flow-Through) Clock Low Time (Flow-Through) Clock High Time (Pipelined)(2) Clock Low Time (Pipelined) Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS Setup Time ADS Hold Time CNTEN Setup Time CNTEN Hold Time CNTRST Setup Time CNTRST Hold Time Output Enable to Data Valid Output Enable to Output Low-Z (2) (2) 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 4 1 4 1 4 1 4 1 4 1 4 1 4 1 ____ 4 1 4 1 4 1 4 1 4 1 4 1 4 1 ____ 12 ____ 15 ____ (1) (1) 2 1 ____ ____ 2 1 ____ ____ Output Enable to Output High-Z 7 25 12 ____ 7 30 15 ____ Clock to Data Valid (Flow-Through)(2) Clock to Data Valid (Pipelined) (2) Data Output Hold After Clock High Clock High to Output High-Z Clock High to Output Low-Z (1) 2 2 2 2 2 2 9 ____ 9 ____ (1) Port-to-Port Delay tCWDD tCCS Write Port Clock High to Read Data Delay Clock-to-Clock Setup Time ____ ____ 40 15 ____ ____ 50 20 ns ns 3743 tbl 11b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = V IH. Flow-through parameters (tCYC1, tCD1) apply when FT /PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC signal, i.e. steady state during operation. 4. 'X' in part number indicates power rating (S or L). 6.42 9 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow-through Output (FT/PIPE"X" = VIL)(3,7) tCYC1 tCH1 CLK CE0 tCL1 tSC CE1 tSB UB, LB tHC tSC tHC tHB tSB tHB R/W tSW tHW tSA tHA An + 1 tCD1 tDC Qn tCKLZ (1) ADDRESS (5) An An + 2 An + 3 tCKHZ (1) DATAOUT Qn + 1 (1) Qn + 2 tOLZ (1) tOHZ tDC OE (2) tOE 3743 drw 06 Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE"X" = VIH)(3,7) tCYC2 tCH2 CLK CE0 tCL2 tSC CE1 tSB UB, LB tHC tSC (4) tHC tHB tSB (6) tHB R/W tSW tSA tHW tHA An + 1 (1 Latency) tCD2 Qn tCKLZ (1) ADDRESS (5) An An + 2 tDC Qn + 1 An + 3 DATAOUT Qn + 2 tOLZ(1) (6) tOHZ(1) OE (2) NOTES: 3743 drw 07 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE 0 = V IH o r CE 1 = V IL f ollowing the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 7. "X" denotes Left or Right port. The diagram is with respect to that port. tOE 6.42 10 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of a Bank Select Pipelined Read(1,2) tCH2 CLK tSA ADDRESS(B1) tHA A0 tSC tHC CE0(B1) tCYC2 tCL2 A1 A2 A3 A4 A5 A6 tSC tCD2 tHC tCD2 tCKHZ(3) Q1 tDC A3 A4 tCD2 Q3 tCKLZ (3) DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 Q0 tDC tCKHZ(3) A5 A6 A2 tSC tHC CE0(B2) tSC tHC tCD2 tCKHZ(3) Q2 tCD2 tCKLZ (3) Q4 DATAOUT(B2) tCKLZ(3) 3743 drw 08 Timing Waveform of a Bank Select Flow-Through Read(6) tCH1 CLK tSA ADDRESS(B1) tSC tHA A0 tHC tSC tCD1 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 A3 A4 A5 A6 D0 tDC tCD1 D1 tDC tCKLZ (1) tCYC1 tCL1 A1 A2 A3 A4 A5 A6 CE0(B1) tHC tCKHZ (1) tCD1 D3 tCKHZ (1) tCD1 D5 tCKLZ (1) tSC CE0(B2) tSC tHC tHC tCD1 DATAOUT(B2) tCKLZ (1) tCKHZ D2 (1) tCD1 tCKLZ (1) tCKHZ D4 (1) 3743 drw 08a NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9279/69 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. UB , LB, OE, and ADS = VIL; CE1(B1) , CE1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE 0, UB , LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH . 5. OE = V IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If t CCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If t CCS > maximum specified, then data from right port READ is not valid until tCCS + t CD1. tCWDD does not apply in this case. 6.42 11 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform with Port-to-Port Flow-Through Read(1,2,3,5) CLK "A" tSW R/W "A" tSA ADDRESS "A" tHA NO MATCH tHW MATCH tSD DATAIN "A" tHD VALID tCCS CLK "B" (4) tCD1 R/W "B" tSW tSA ADDRESS "B" tHW tHA NO MATCH MATCH tCWDD DATAOUT "B" tDC (4) tCD1 VALID VALID tDC 3743 drw 09 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH. 3. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + t CD1. tCWDD does not apply in this case. 5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A". 6.42 12 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC CE1 tSB UB, LB tHC tHB tSW tHW R/W tSW tHW ADDRESS (4) An tSA tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 DATAIN (2) tCD2 Qn READ tCKHZ (1) tCKLZ (1) tCD2 Qn + 3 DATAOUT NOP (5) WRITE READ 3743 drw 10 Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3) tCH2 CLK CE0 tCYC2 tCL2 tSC CE1 tSB UB, LB tHC tHB tSW tHW R/W tSW tHW ADDRESS DATAIN (4) An tSA tHA An +1 An + 2 tSD tHD An + 3 An + 4 An + 5 (2) tCD2 Qn tOHZ(1) Dn + 2 Dn + 3 tCKLZ(1) tCD2 Qn + 4 DATAOUT OE READ WRITE READ 3743 drw 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 13 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3) tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tSB UB, LB tHC tHB tSW tHW R/W tSW tHW ADDRESS (4) tSA DATAIN (2) An tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 tCD1 Qn tDC READ tCD1 Qn + 1 tCKHZ NOP (5) (1) tCD1 tCD1 Qn + 3 tDC 3743 drw 12 DATAOUT tCKLZ WRITE (1) READ Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC CE1 tSB UB, LB tHC tHB tSW tHW R/W ADDRESS (4) tSW tHW An tSA tHA An +1 An + 2 tSD tHD Dn + 2 (2) An + 3 An + 4 An + 5 DATAIN tCD1 Qn tOHZ OE (1) Dn + 3 tDC tOE tCD1 (1) tCD1 Qn + 4 tDC DATAOUT tCKLZ READ WRITE READ 3743 drw 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 14 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 CLK tSA ADDRESS An tSAD tHAD ADS tCYC2 tCL2 tHA tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) Qx tDC Qn Qn + 1 Qn + 2(2) Qn + 3 READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 3743 drw 14 Timing Waveform of Flow-Through Read with Address Counter Advance(1) tCH1 CLK tSA ADDRESS tHA tCYC1 tCL1 An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 3743 drw 15 Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 NOTES: 1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = V IH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 6.42 15 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1) tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2 An INTERNAL(3) ADDRESS tSAD tHAD ADS An(7) An + 1 An + 2 An + 3 An + 4 CNTEN(7) tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 3743 drw 16 Timing Waveform of Counter Reset (Pipelined Outputs)(2) tCH2 CLK tSA tHA (4) tCYC2 tCL2 ADDRESS INTERNAL(3) ADDRESS R/W ADS CNTEN An Ax (6) An + 1 An + 2 0 tSW tHW 1 An An + 1 tSAD tHAD tSCN tHCN tSRST tHRST CNTRST tSD tHD D0 DATAIN (5) DATAOUT COUNTER RESET (6) Q0 WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS n Q1 READ ADDRESS n+1 Qn 3743 drw 17 NOTES: 1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0, UB, LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. 6.42 16 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Functional Description The IDT70V9279/69 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to staff the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70V9279/69's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 LOW and CE1 HIGH to re-activate the outputs. Depth and Width Expansion The IDT70V9279/69 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the varioius chip enables in order to expand two devices in depth. The IDT70V9279/69 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 32-bit or wider applications. A15/A14(1) IDT70V9279/69 CE0 CE1 VDD IDT70V9279/69 CE0 CE1 VDD Control Inputs Control Inputs IDT70V9279/69 CE1 CE0 IDT70V9279/69 CE1 CE0 , Control Inputs Control Inputs 3743 drw 18 Figure 4. Depth and Width Expansion with IDT70V9279/69 CNTRST CLK ADS CNTEN R/W LB, UB OE NOTE: 1. A15 is for IDT70V9279. A14 is for IDT70V9269. 6.42 17 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 99 Speed A Package A Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PRF 6 7 9 12 15 S L 128-pin TQFP (PK128-1) Commercial Only Commercial Only Commercial & Industrial Commercial Only Commercial Only Standard Power Low Power Speed in nanoseconds 70V9279 512K (32K x 16-Bit) Synchronous Dual-Port RAM 70V9269 256K (16K x 16-Bit) Synchronous Dual-Port RAM 3743 drw 19 Ordering Information for Flow-through Devices Old Flow-through Part 70V927S/L25 70V927S/L30 New Combined Part 70V9279S/L12 70V9279S/L15 3743 tbl 12 IDT Clock Solution for IDT70V9279/69 Dual-Port Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage I/O Input Capacitance Clock Specifications Input Duty Cycle Requirement Maximum Frequency Jitter Tolerance IDT PLL Clock Device IDT Non-PLL Clock Device 49FCT3805 49FCT3805D/E 74FCT3807 74FCT3807D/E 3743 tbl 13 70V9279/69 3.3 LVTTL 9pF 40% 100 150ps 2305 2308 2309 6.42 18 IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History 1/12/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 14 Added Depth & Width Expansion section Page 4 Deleted note 6 for Table II Page 7 Corrected typo in heading Replaced IDT logo Combined Pipelined 70V9279/69 family and Flow-through 70V927 family offerings into one data sheet Changed ±200mV in waveform notes to 0mV Added corresponding part chart with ordering information Page 4 Changed information in Truth Table II Increased storage temperature parameters Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Removed Preliminary status Consolidated multiple devices into one datasheet Changed naming conventions from VCC to VDD and from GND to Vss Page 2 Added date revision for pin configuration Page 3 Added footnotes for UB, LB, CE0 and CE1 buffer conditions when FT or PIPE Page 4 Added junction temperature to Absolute Maximum Ratings Table Added Ambient Temperature footnote Page 5 Added I-temp numbers for 9ns speed to DC Electrical Characteristics Table Added 6ns speed DC power numbers to the DC Electrical Characteristics Table Page 7 Added I-temp for 9ns speed to AC Electrical CharacteristicsTable Added 6ns speed AC timing numbers to the AC Electrical Characteristics Table Page 18 Added 6ns speed grade and 9ns I-temp to ordering information Added IDT Clock Solution Table Page 1 & 19 Updated IDT logo, replaced IDTTM logo with IDT® logo Page 1 & 18 Added 7ns speed grade to ordering information Page 5 Added 7ns speed DC power numbers to the DC Electrical Characteristics Table Page 8 Added 7ns speed AC timing numbers to the AC Electrical Characteristics Table 6/15/99: 9/29/99: 11/10/99: 3/31/00: 1/17/01: 02/25/04: 05/04/04: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6.42 19 for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.