IDT7133SA35F

HIGH SPEED 2K X 16 DUAL-PORT SRAM Features x x x x x x IDT7133SA/LA IDT7143SA/LA x x x x High-speed access – Military: 25/35/45/55/70/90ns (max.) – Industrial: 25/35/55ns (max.) – Commercial: 20/25/35/45/55/70/90ns (max.) Low-power operation – IDT7133/43SA Active: 1150mW (typ.) Standby: 5mW (typ.) – IDT7133/43LA Active: 1050mW (typ.) Standby: 1mW (typ.) Versatile control for write: separate write control for lower and upper byte of each port MASTER IDT7133 easily expands data bus width to 32 bits or more using SLAVE IDT7143 On-chip port arbitration logic (IDT7133 only) x x BUSY output flag on IDT7133; BUSY input on IDT7143 Fully asynchronous operation from either port Battery backup operation–2V data retention TTL-compatible; single 5V (±10%) power supply Available in 68-pin ceramic PGA, Flatpack, PLCC and 100pin TQFP Military product compliant to MIL-PRF-38535 QML Industrial temperature range (–40°C to +85°C) is available for selected speeds Description The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs. The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM together with the IDT7143 “SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider Functional Block Diagram R/WLUB CEL R/WRUB CER R/WLLB OE L R/WRLB OER I/O8L - I/O15L I/O0L - I/O7L BUSYL (1) A10L A0L ADDRESS DECODER 11 I/O CONTROL I/O CONTROL I/O8R - I/O15R I/O0R - I/O 7R BUSYR (1) MEMORY ARRAY ADDRESS DECODER 11 A10R A0R CEL ARBITRATION LOGIC (IDT7133 ONLY) CER 2746 drw 01 NOTE: 1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor. IDT7143 (SLAVE): BUSY is input. JUNE 2000 1 ©2000 Integrated Device Technology, Inc. DSC 2746/11 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 1,150mW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200µW for a 2V battery. The IDT7133/7143 devices have identical pinouts. Each is packed in a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. Pin Configurations(1,2,3) INDEX I/O9L I/O10L I/O11L I/O12L I/O13L I/O14L I/O15L VCC(1) GND(2) I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L I/O1L I/O0L VCC(1) R/WLUB R/WLLB OEL A10L A9L A8L A7L 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 IDT7133/43 J68-1 / F68-1(4) 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 68-Pin PLCC/Flatpack Top View(5) 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A6L A5L A4L A3L A2L A1L A0L BUSYL CEL CER BUSYR A0R A1R A2R A3R A4R A5R 2746 drw 02 I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND(2) R/WRUB R/WRLB OER A10R A9R A8R A7R A6R Index 6.42 2 I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R OER R/WRLB GND N/C CER R/WRUB N/C N/C N/C A10R A9R A8R A7R A6R A5R NOTES: 1. Both VCC pins must be connected to the power supply to ensure reliable operation. 2. Both GND pins must be connected to the ground supply to ensure reliable operation. 3. J68-Package body is approximately 0.95 in x 0.95 in x 0.17 in. F68-Package body is approximately 1.18 in x 1.18 in x 0.16 in. PN100-Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C 1 2 3 4 5 6 7 8 9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WLLB N/C CEL R/WLUB N/C N/C N/C A10L A9L A8L A7L A6L 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 IDT7133/43PF PN100-1(4) 100-Pin TQFP Top View(5) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L N/C BUSYL GND N/C BUSYR N/C A0R A1R A2R A3R A4R N/C N/C N/C N/C 2746 drw 03 , IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't.) 51 50 48 46 44 42 40 38 36 11 53 A6L 52 A5L 49 A3L 47 A1L 45 BUSYL 43 CER 41 A0R 39 A2R 37 A4R 35 34 10 55 A8L 54 A7L A4L A2L A0L CEL BUSYR A1R A3R A5R 32 A6R 33 09 A10L 57 56 A9L A8R 30 A7R 31 08 R/WLLB 59 OEL 58 A10R 28 A9R 29 07 VCC(1) R/WLUB 61 60 R/WRLB OER 27 IDT7133/43G GU68-1(4) 68-Pin PGA Top View(5) 26 06 I/O1L 63 I/O0L 62 GND(2) R/WRUB 24 25 05 I/O3L 65 I/O2L 64 I/O14R 22 I/O15R 23 04 I/O5L 67 I/O4L 66 I/O12R 20 I/O13R 21 03 I/O7L 68 1 I/O6L 3 5 7 9 11 13 15 I/O10R 18 I/O11R 19 02 I/O8L 2 I/O9L 4 I/O11L 6 I/O13L 8 I/O15L GND(2) 10 I/O1R 12 I/O3R 14 I/O5R 16 I/O8R 17 I/O9R 01 Pin 1 Designator A I/O10L B I/O12L C I/O14L D VCC(1) E I/O0R F I/O2R G I/O4R H I/O6R J I/O7R K L 2746 drw 04 NOTES: 1. Both VCC pins must be connected to the power supply to ensure reliable operation. 2. Both GND pins must be connected to the ground supply to ensure reliable operation. 3. Package body is approximately 1.18 in x 1.18 in x 0.16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Pin Names Left Port CEL R/WLUB R/WLLB OEL A0L - A10L I/O0L - I/O15L BUSYL Right Port CER R/WRUB R/WRLB OER A0R - A10R I/O0R - I/O15R BUSYR VCC GND Chip Enable Upper Byte Read/Write Enable Lower Byte Read/Write Enable Output Enable Address Data Input/Output Busy Flag Power Ground 2746 tbl 01 Names 3 6.42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Commercial & Industrial -0.5 to +7.0 Military -0.5 to +7.0 Unit V Maximum Operating Temperature and Supply Voltage(1,2) Grade Military Ambient Temperature -55OC to +125OC 0 C to +70 C -40 C to +85 C O O O O GND 0V 0V 0V Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10% 2746 tbl 04 TBIAS TSTG PT(3) IOUT -55 to +125 -65 to +150 2.0 50 -65 to +135 -65 to +150 2.0 50 o C C Commercial Industrial o W mA 2746 tbl 02 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Recommended DC Operating Conditions Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5 (1) Typ. 5.0 0 ____ ____ Max. 5.5 0 6.0 (2) Unit V V V V 2746 tbl 05 0.8 Capacitance (TA = +25°C, f = 1.0mhz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 11 11 Unit pF pF 2746 tbl 03 NOTES: 1. VIL (min.) = -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (Either port, VCC = 5.0V ± 10%) 7133SA 7143SA Symbol |ILI| |ILO| VOL VOL VOH Parameter Input Leakage Current (1) 7133LA 7143LA Min. ___ Test Conditions VCC = 5.5V, VIN = 0V to VCC CE = VIH, VOUT = 0V to V CC IOL = 4mA IOL = 16mA IOH = -4mA Min. ___ Max. 10 10 0.4 0.5 ___ Max. 5 5 0.4 0.5 ___ Unit µA µA V V V 2746 tbl 06 Output Leakage Current Output Low Voltage (I/O0-I/O15) Open Drain Output Low Voltage (BUSY) Output High Voltage ___ ___ ___ ___ ___ ___ 2.4 2.4 NOTE: 1. At Vcc < 2.0V, input leakages are undefined. 6.42 4 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Operating Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%) 7133X20 7143X20 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL , Outputs Disabled f = fMAX (3) 7133X25 7143X25 Com'l, Ind & Military Typ. (1) 250 230 250 230 25 25 25 25 140 100 140 100 1.0 0.2 1.0 0.2 140 120 140 120 Max. 300 270 330 300 80 70 90 80 200 170 230 190 15 4 30 10 190 170 220 200 7133X35 7143X35 Com'l, Ind & Military Typ. (1) 240 210 240 220 25 25 25 25 120 100 120 100 1.0 0.2 1.0 0.2 120 100 120 100 Max. 295 250 325 295 70 60 75 65 180 160 200 180 15 4 30 10 170 150 190 170 2746 tbl 07a Version COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND S L S L S L S L S L S L S L S L S L S L Typ. (1) 250 230 ____ ____ Max. 310 280 ____ ____ Unit mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL and C ER = VIH f = fMAX(3) 25 25 ____ ____ 80 70 ____ ____ mA ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and C E"B" = VIH(4) f=fMAX(3) Active Port Outputs Disabled 140 120 ____ ____ 200 180 ____ ____ mA ISB3 Full Standby Current (Both Ports CMOS Level Inputs) Both Ports C EL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) 1.0 0.2 ____ ____ 15 5 ____ ____ mA ISB4 Full Standby Current (One Port CMOS Level Inputs) 140 120 ____ ____ 190 170 ____ ____ mA 7133X45 7143X45 Com'l & Military Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Disabled f = fMAX(3) Version COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND S L S L S L S L S L S L S L S L S L S L Typ. (1) 230 210 230 210 25 25 25 25 120 100 120 100 1.0 0.2 1.0 0.2 120 100 120 100 Max. 290 250 320 290 75 65 80 70 190 170 210 190 15 4 30 10 180 160 200 180 7133X55 7143X55 Com'l, Ind & Military Typ. (1) 230 210 230 210 25 25 25 25 120 100 120 100 1.0 0.2 1.0 0.2 120 100 120 100 Max. 285 250 315 285 70 60 80 70 180 160 210 190 15 4 30 10 170 150 200 180 7133X70/90 7143X70/90 Com'l & Military Typ. (1) 230 210 230 210 25 25 25 25 120 100 120 100 1.0 0.2 1.0 0.2 120 100 120 100 Max. 280 250 310 280 70 60 75 65 180 160 200 180 15 4 30 10 170 150 190 170 2746 tbl 07b Unit mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL and C ER = VIH f = fMAX (3) mA ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and C E"B" = VIH(4) f=fMAX(3) Active Port Outputs Disabled mA ISB3 Full Standby Current (Both Ports CMOS Level Inputs) Both Ports C EL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) mA ISB4 Full Standby Current (One Port CMOS Level Inputs) mA NOTES: 1. VCC = 5V, T A = +25°C for Typ., and are not production tested. ICCDC = 180mA (typ.) 2. 'X' in part number indicates power rating (SA or LA) 3. At f = fMAX , address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 5 6.42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Data Retention Characteristics (LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V 7133LA/7143LA Symbol VDR ICCDR Parameter VCC for Data Retention Data Retention Current VCC = 2V CE > VHC VIN > VHC or < VLC tCDR tR(3) (3) Test Condition Min. 2.0 Typ.(1) ___ Max. ___ Unit V µA MIL. & IND. COM'L. ___ 100 100 ___ 4000 1500 ___ ___ Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC(2) V V 2746 tbl 08 ___ ___ NOTES: 1. Vcc = 2V, TA = +25°C, and are not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed by device characterization but is not production tested. Data Retention Waveform DATA RETENTION MODE VCC tCDR CE VDR VIH VIH 2746 drw 05 4.5V VDR > 2V 4.5V tR AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns Max. 1.5V 1.5V Figures 1, 2 and 3 2746 tbl 09 5V 1250Ω DATAOUT 775Ω 30pF Figure 1. AC Output Test Load 5V 1250Ω DATAOUT 775Ω 5pF* BUSY 5V 270Ω 30pF 2746 drw 06 Figure 2. Output Load (for tLZ, t HZ, tWZ, tOW ) *Including scope and jig Figure 3. BUSY Output Load (IDT7133 only) 6.42 6 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(3) 7133X20 7143X20 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) 7133X25 7143X25 Com'l, Ind & Military Min. Max. 7133X35 7143X35 Com'l, Ind & Military Min. Max. Unit Parameter Min. Max. 20 ____ ____ 25 ____ ____ 35 ____ ____ ns ns ns ns ns ns ns ns ns 2746 tbl 10a 20 20 12 ____ 25 25 15 ____ 35 35 20 ____ ____ ____ ____ ____ ____ ____ 0 0 ____ 0 0 ____ 0 0 ____ ____ ____ ____ Output High-Z Time (1,2) Chip Enable to Power Up Time (2) Chip Disable to Power Down Time (2) 12 ____ 15 ____ 20 ____ 0 ____ 0 ____ 0 ____ 20 50 50 7133X45 7143X45 Com'l & Military Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) Output High-Z Time (1,2) 7133X55 7143X55 Com'l, Ind & Military Min. Max. 7133X70/90 7143X70/90 Com'l & Military Min. Max. Unit Parameter Min. Max. 45 ____ ____ 55 ____ ____ 70/90 ____ ____ ns ns ns ns ns ns ns ns ns 2746 tbl 10b 45 45 25 ____ 55 55 30 ____ 70/90 70/90 40/40 ____ ____ ____ ____ ____ ____ ____ 0 0 ____ 0 5 ____ 0/0 5/5 ____ ____ ____ ____ 20 ____ 20 ____ 25/25 ____ Chip Enable to Power Up Time (2) Chip Disable to Power Down Time (2) 0 ____ 0 ____ 0/0 ____ 50 50 50/50 NOTES: 1. Transition is measured 0mV fromLow or High-impedance voltage with load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. 'X' in part number indicates power rating (SA or LA). 7 6.42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(5) tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID tOH DATA VALID BUSYOUT tBDD (3,4) 2746 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5) tACE CE tAOE OE tLZ DATAOUT tPU CURRENT ICC 50% ISB 50% 2746 drw 08 (1) (4) (4) tHZ (2) tHZ (2) VALID DATA tPD tLZ (1) NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is deasserted first, OE or CE. 3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no relationship to valid output data. 4. Start of valid data depends on which timing becomes effective last, t AOE, tACE, tAA, or tBDD. 5. R/W = VIH, and the address is valid prior to or coincidental with CE transition LOW. 6.42 8 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 7133X20 7143X20 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time(3) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time(1,2) Data Hold Time(4) Write Enable to Output in High-Z Output Active from End-of-Write (1,2) 7133X25 7143X25 Com'l, Ind & Military Min. Max. 7133X35 7143X35 Com'l, Ind & Military Min. Max. Unit Parameter Min. Max. 20 15 15 0 15 0 15 ____ ____ 25 20 20 0 20 0 15 ____ ____ 35 25 25 0 25 0 20 ____ ____ ns ns ns ns ns ns ns ns ns ns ns 2746 tbl 11a ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 12 ____ 15 ____ 20 ____ 0 ____ 0 ____ 0 ____ 12 ____ 15 ____ 20 ____ (1,2,4) 0 0 0 7133X45 7143X45 Com'l & Military Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time(3) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (4) (1,2) (1,2) 7133X55 7143X55 Com'l, Ind & Military Min. Max. 7133X70/90 7143X70/90 Com'l & Military Min. Max. Unit Parameter Min. Max. 45 30 30 0 30 0 20 ____ ____ 55 40 40 0 40 0 25 ____ ____ 70/90 50/50 50/50 0/0 50/50 0/0 30/30 ____ ____ ns ns ns ns ns ns ns ns ns ns ns 2746 tbl 11b ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 20 ____ 20 ____ 25/25 ____ 5 ____ 5 ____ 5/5 ____ Write Enable to Output in High-Z 20 ____ 20 ____ 25/25 ____ Output Active from End-of-Write (1,2,4) 5 5 5/5 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage from the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but not production tested. 3. For MASTER/SLAVE combination, tWC = tBAA + tWR + tWP , since R/W = VIL must occur after tBAA. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will very over voltage and temperature, the actual tDH will always be smaller than the actual t OW. 5. 'X' in part number indicates power rating (SA or LA). 9 6.42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(6) 7133X20 7143X20 Com'l Only Symbol BUSY TIMING (For MASTER 71V33) tBAA tBDA tBAC tBDC tWDD tDDD tBDD tAPS tWH BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay BUSY Disable to Valid Data (2) (1) ____ 7133X25 7143X25 Com'l, Ind & Military Min. Max. 7133X35 7143X35 Com'l, Ind & Military Min. Max. Unit Parameter Min. Max. 20 20 20 17 40 30 25 ____ ____ ____ 20 20 20 20 50 35 30 ____ ____ ____ 30 30 25 25 60 45 35 ____ ____ ns ns ns ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ Arbitration Priority Set-up Time (3) Write Hold After BUSY (5) 5 20 5 20 5 25 BUSY INPUT TIMING (For SLAVE 71V43) tWB tWH tWDD tDDD BUSY Input to Write (4) Write Hold After BUSY (5) 0 20 ____ ____ ____ ____ 0 20 ____ ____ ____ ____ 0 25 ____ ____ ____ ____ ns ns ns ns 2746 tbl 12a Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) 40 30 50 35 60 45 7133X45 7143X45 Com'l & Military Symbol BUSY TIMING (For MASTER 71V33) tBAA tBDA tBAC tBDC tWDD tDDD tBDD tAPS tWH BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Pulse to Data Delay (1) (1) ____ 7133X55 7143X55 Com'l, Ind & Military Min. Max. 7133X70/90 7143X70/90 Com'l & Military Min. Max. Unit Parameter Min. Max. 40 40 30 25 80 55 40 ____ ____ ____ 40 40 35 30 80 55 40 ____ ____ ____ 45/45 45/45 35/35 30/30 90/90 70/70 40/40 ____ ____ ns ns ns ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ Write Data Valid to Read Data Delay BUSY Disable to Valid Data(2) Arbitration Priority Set-up Time Write Hold After BUSY (5) (3) 5 30 5 30 5/5 30/30 BUSY INPUT TIMING (For SLAVE 71V43) tWB tWH tWDD tDDD BUSY Input to Write (4) Write Hold After BUSY (5) 0 30 ____ ____ ____ 0 30 ____ ____ ____ ____ 0/0 30/30 ____ ____ ____ ____ ns ns ns ns 2746 tbl 12b Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) 80 55 80 55 90/90 70/70 ____ NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy". 2. tBDD is calculated parameter and is greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual). 3. To ensure that the earlier of the two ports wins. 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part number indicates power rating (SA or LA). 610 .42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1 (R/W Controlled Timing)(1,5,8) tWC ADDRESS tAS (6) OE tAW CE tWP (2) R/W (9) tWR(3) (7) tHZ tLZ DATAOUT (4) tWZ (7) tOW (4) tHZ (7) tDW DATAIN tDH 2746 drw 09 Write Cycle No. 2 (CE Controlled Timing)(1,5) tWC ADDRESS tAW CE tAS(6) R/W (9) tEW (2) tWR tDW DATAIN tDH 2746 drw 10 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/ W) is asserted last. 7. Timing depends on which enable signal is de-asserted first, CE or OE. 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. R/W for either upper or lower byte. 611 .42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN"A" tAPS ADDR"B" (1) tDH VALID MATCH tBDA tBDD BUSY"B" tWDD DATAOUT "B" tDDD NOTES: 1. To ensure that the earlier of the two ports wins, t APS is ignored for Slave (IDT7143). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". (4) 2746 drw 11 VALID Timing Waveform of Write with BUSY(3) tWP R/W"A" tWB BUSY"B" tWH (1) R/W"B" (2) , 2746 drw 12 NOTES: 1. tWH must be met for both BUSY input (IDT7143, slave) and output (IDT7133, master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY "B" goes HIGH. 3. All timing is the same for left and right ports. Port " A" may be either left or right port. Port "B" is the opposite from port " A". 612 .42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of BUSY Arbitration Controlled by CE Timing(1) ADDR"A" AND "B" ADDRESSES MATCH CE"A" tAPS(2) CE"B" tBAC BUSY"B" tBDC 2746 drw 13 Timing Waveform of BUSY Arbitration Controlled by Addresses(1) tRC OR ADDR "A" tWC ADDRESSES DO NOT MATCH ADDRESSES MATCH tAPS(2) ADDR "B" tBAA BUSY "B" 2746 drw 14 tBDA NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port " A". 2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (IDT7133 only). 613 .42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Functional Description The IDT7133/43 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7133/43 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Non-contention READ/WRITE conditions are illustrated in Truth Table 1. LEFT R/W BUSY 270Ω R/W BUSY IDT7133 MASTER R/W BUSY 270Ω RIGHT R/W BUSY VCC VCC Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by using the IDT7143 (SLAVE). In the IDT7143, the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT 7133 RAM are open drain and require pullup resistors. R/W BUSY IDT7143 SLAVE R/W BUSY 2746 drw 15 Figure 4. Busy and chip enable routing for both width and depth expansion with the IDT7133 (MASTER) and the IDT7143 (SLAVE). Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT7133/43 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7133 RAM the BUSY pin is an output and on the IDT7143 RAM, the BUSY pin is an input (see Figure 3). Expanding the data bus width to 32 bits or more in a Dual-Port RAM system implies that several chips will be active at the same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one will activate its BUSYL while another activates its BUSYR signal. Both sides are now BUSY and the CPUs will await indefinitely for their port to become free. To avoid the “Busy Lock-Out” problem, IDT has developed a MASTER/SLAVE approach where only one hardware arbitrator, in the MASTER, is used. The SLAVE has BUSY inputs which allow an interface to the MASTER with no external components and with a speed advantage over other systems. When expanding Dual-Port RAMs in width, the writing of the SLAVE RAMs must be delayed until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a contention situation. Conversely, the write pulse must extend a hold time past BUSY to ensure that a write cycle takes place after the contention is resolved. This timing is inherent in all Dual-Port memory systems where more than one chip is active at the same time. The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs, the write to the SLAVE will be inhibited due to BUSY from the MASTER. 614 .42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Truth Table I – Non-Contention Read/Write Control(4) LEFT OR RIGHT PORT(1) R/ WLB X X L L H L H H H R/WUB X X L H L H L H H CE H H L L L L L L L OE X X X L L H H L H I/O0-7 Z Z DATAIN DATAIN DATAOUT DATAIN Z DATAOUT Z I/O8-15 Z Z DATAIN DATAOUT DATAIN Z DATAIN DATAOUT Z Function Port Disabled and in Power Down Mode, ISB2, ISB4 CER = CEL = VIH, Power Down Mode, ISB1 or ISB3 Data on Lower Byte and Upper Byte Written into Memory (2) Data on Lower Byte Written into Memory (2), Data in Memory Output on Upper Byte (3) Data in Memory Output on Lower Byte (3), Data on Upper Byte Written into Memory (2) Data on Lower Byte Written into Memory (2) Data on Upper Byte Written into Memory (2) Data in Memory Output on Lower Byte and Upper Byte High Impedance Outputs 2746 tbl 13 NOTES: 1. A0L - A10L≠A0R - A10R 2. If BUSY = LOW, data is not written. 3. If BUSY = LOW, data may not be valid, see tWDD and tDDD timing. 4. "H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte Truth Table II — Address BUSY Arbitration Inputs CEL X H X L CER X X H L A0L-A10L A0R-A10R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3) 2746 tbl 14 NOTES: 1. Pins BUSY L and BUSYR are both outputs on the IDT7133 (MASTER). Both are inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. “H” if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = VIL will result BUSYL and BUSY R outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 615 .42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Ordering Information IDT XXXX Device Type XX Power XX Speed X Package X Process/ Temperature Range Blank I B Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Military (-55°C to +125°C) Compliant to MIL-PRF-38535 QML 68-pin PLCC (J68-1) 68-pin PGA (GU68-1) 68-pin Flatplack (F68-1) 100-pin TQFP (PN100-1) Commercial Only Commercial, Industrial & Military Commercial, Industrial & Military Commercial & Military Commercial, Industrial & Military Commercial & Military Commercial & Military Low Power Standard Power 32K (2K x 16-Bit) MASTER Dual-Port RAM 32K (2K x 16-Bit) SLAVE Dual-Port RAM 2746 drw 16 J G F PF 20 25 35 45 55 70 90 LA SA 7133 7143 Speed in nanoseconds Datasheet Document History 12/18/98: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 2 corrected PN100 pinout Corrected PF ordering code Cosmetic and typographical corrections Changed drawing format Added Industrial Temperature Ranges and removed corresponding notes Replaced IDT logo Changed ±500mV to 0mV in notes Page 2 Fixed overbar in pinout Page 4 Increased storage temperature parameters Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" 2/17/99: 3/9/99: 6/9/99: 10/1/99: 11/10/99: 4/1/00: 6/26/00: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 616 .42 for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.