IDT7134SA70J

HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM Features High-speed access – Military: 25/35/45/55/70ns (max.) – Industrial: 55ns (max.) – Commercial: 20/25/35/45/55/70ns (max.) Low-power operation – IDT7134SA Active: 700mW (typ.) Standby: 5mW (typ.) – IDT7134LA Active: 700mW (typ.) Standby: 1mW (typ.) Fully asynchronous operation from either port Battery backup operation—2V data retention TTL-compatible; single 5V (±10%) power supply Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC Military product compliant to MIL-PRF-38535 QML Industrial temperature range (–40°C to +85°C) is available for selected speeds IDT7134SA/LA Description x x x x x x x x The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when both sides simultaneously access the same Dual-Port RAM location. The IDT7134 provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user’s responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these Dual-Port typically operate on only 700mW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200µW from a 2V battery. The IDT7134 is packaged on either a sidebraze or plastic 48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade product is manufactured in compliance with the latest revision of MILPRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. Functional Block Diagram R/WL CEL R/WR CER OEL I/O0L- I/O7L COLUMN I/O COLUMN I/O OER I/O0R- I/O7R A0L- A11L LEFT SIDE ADDRESS DECODE LOGIC MEMORY ARRAY RIGHT SIDE ADDRESS DECODE LOGIC A0R- A11R 2720 drw 01 JUNE 1999 1 DSC-2720/9 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) R/WL CEL R/WR N/C A11R I/O5L N/C GND I/O0R I/O1R I/O2R I/O4R I/O5R I/O3R I/O6R I/O4L I/O6L I/O7L CEL R/WL A11L A10L OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O 0L I/O 1L I/O 2L I/O 3L I/O 4L I/O 5L I/O 6L I/O 7L GND 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 IDT7134P or C 41 P48-1(4) 9 40 & 10 39 (4) 11 C48-2 38 48-Pin 12 37 Top 13 View(5) 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 VCC CER R/WR A11R A10R OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R , 2720 drw 02 INDEX 765 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20 43 2 1 52 51 50 49 48 47 46 45 44 43 42 A10R A10L A11L A0L OEL VCC CER N/C OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/O7R IDT7134J J52-1(4) 52-Pin PLCC 41 40 39 38 37 36 Top View(5) 35 34 21 22 23 24 25 26 27 28 29 30 31 32 33 2720 drw 03 A11L R/WL CEL R/WR INDEX 65 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. P48-1 package body is approximately .55 in x .61 in x .19 in. C48-2 package body is approximately .62 in x 2.43 in x .15 in. J52-1 package body is approximately .75 in x .75 in x .17 in. L48-1 package body is approximately .57 in x .57 in x .68 in. F48-1 package body is approxiamtely .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of actual part-marking. 43 2 7 8 9 10 11 12 13 14 15 16 17 1 48 47 46 45 44 43 42 41 40 39 A10R OER A11R VCC CER A10L A0L OEL A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R , IDT7134L48 or F L48-1(4) & F48-1(4) 48-Pin LCC/Flatpack Top View(5) 38 37 36 35 34 33 32 I/O2L 31 18 19 20 21 22 23 24 25 26 27 28 29 30 I/O4R I/O5R GND I/O0R I/O1R 2 I/O2R I/O3R I/O3L I/O4L I/O6L I/O7L I/O5L 2720 drw 04 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Commercial & Industrial -0.5 to +7.0 Military -0.5 to +7.0 Unit V Recommended Operating Temperature and Supply Voltage(1,2) Grade Military Ambient Temperature -55OC to +125OC 0OC to +70OC -40OC to +85OC GND 0V 0V 0V Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10% 2720 tbl 03 TBIAS TSTG PT(3) IOUT -55 to +125 -55 to +125 1.5 50 -65 to +135 -65 to +150 1.5 50 o C C Commercial Industrial o W mA 2720 tbl 01 NOTES: 1. This is the parameter TA. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25%of the cycle time or 10 ns maximum, and is limited to < 20mA for the period of VTERM > Vcc +10%. 3. VTERM = 5.5V. Recommended DC Operating Conditions Symbol VCC GND VIH Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5 (1) Typ. 5.0 0 ____ ____ Max. 5.5 0 6.0(2) 0.8 Unit V V V V 2720 tbl 04 Capacitance (1) (T A = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions (2) VIN = 3dV V OUT = 3dV Max. 11 11 Unit pF pF 2720 tbl 02 VIL NOTES: 1. VIL (min.) > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V and from 3V to 0V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5V ± 10%) 7134SA Symbol |ILI| |ILO| V OL Parameter Input Leakage Current (1) 7134LA Min. ___ ___ ___ ___ Test Conditions V CC = 5.5V, VIN = 0V to V CC CE - VIH, VOUT = 0V to V CC IOL = 6mA IOL = 8mA Min. ___ ___ ___ ___ Max. 10 10 0.4 0.5 ___ Max. 5 5 0.4 0.5 ___ Unit µA µA V V V 2720 tbl 05 Output Leakage Current Output Low Voltage V OH Output High Voltage IOH = -4mA 2.4 2.4 NOTES: 1. At Vcc < 2.0V input leakages are undefined. 3 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2,4) (VCC = 5.0V ± 10%) 7134X20 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) CE = VIL Outputs Open f = fMAX(3) Test Condition Version COM'L MIL & IND COM'L MIL & IND CE"A" = VIL and CE"B" = VIH Active Port Outputs Open, f=fMAX(3) COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ. 170 170 ____ ____ 7134X25 Com'l & Military Typ. 160 160 160 160 25 25 25 25 95 95 95 95 1.0 0.2 1.0 0.2 95 95 95 95 Max. 280 220 310 260 80 50 100 80 180 140 210 170 15 4.0 30 10 170 120 210 150 7134X35 Com'l & Military Typ. 150 150 150 150 25 25 25 25 85 85 85 85 1.0 0.2 1.0 0.2 85 85 85 85 Max. 260 210 300 250 75 45 75 55 170 130 200 160 15 4.0 30 10 160 110 190 130 2720 tbl 06a Max. 280 240 ____ ____ Unit mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL and CER = VIH f = fMAX(3) 25 25 ____ ____ 100 80 ____ ____ mA ISB2 Standby Current (One Port - TTL Level Inputs) 105 105 ____ ____ 180 150 ____ ____ mA ISB3 Full Standby Current (Both Ports CMOS Level Inputs) Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) One Port CE"A" o r CE"B" > V CC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Open, f = fMAX(3) 1.0 0.2 ____ ____ 15 4.5 ____ ____ mA ISB4 Full Standby Current (One Port CMOS Level Inputs) 105 105 ____ ____ 170 130 ____ ____ mA 7134X45 Com'l & Military Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) CE = VIL Outputs Open f = fMAX(3) Test Condition Version COM'L MIL & IND COM'L MIL & IND CE"A" = VIL and CE"B" = VIH Active Port Outputs Open, f=fMAX(3) COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ. 140 140 140 140 25 25 25 25 75 75 75 75 1.0 0.2 1.0 0.2 75 75 75 75 Max. 240 200 280 240 70 40 70 50 160 130 190 150 15 4.0 30 10 150 100 180 120 7134X55 Com'l, Ind & Military Typ. 140 140 140 140 25 25 25 25 75 75 75 75 1.0 0.2 1.0 0.2 75 75 75 75 Max. 240 200 270 220 70 40 70 50 160 130 180 150 15 4.0 30 10 150 100 170 120 7134X70 Com'l & Military Typ. 140 140 140 140 25 25 25 25 75 75 75 75 1.0 0.2 1.0 0.2 75 75 75 75 Max. 240 200 270 220 70 40 70 50 160 130 180 150 15 4.0 30 10 150 100 170 120 2720 tbl 06b Unit mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL and CER = VIH f = fMAX(3) mA ISB2 Standby Current (One Port - TTL Level Inputs) mA ISB3 Full Standby Current (Both Ports CMOS Level Inputs) Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) One Port CE"A" o r CE"B" > V CC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Open, f = fMAX(3) mA ISB4 Full Standby Current (One Port CMOS Level Inputs) mA NOTES: 1. 'X' in part number indicates power rating (SA or LA). 2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested. 3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3. 4. Industrial temperature: for other speeds, packages and powers contact your sales office. 4 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Data Retention Characteristics Over All Temperature Ranges (LA Version Only) V LC = 0.2V, VHC = VCC - 0.2V Symbol VDR ICCDR Parameter VCC for Data Retention Data Retention Current VCC = 2V CE > V HC VIN > V HC o r < V LC tCDR (3) tR(3) Chip Dese lect to Data Retention Time Operation Recovery Time MIL. & IND. COM'L. Test Condition Min. 2.0 ___ ___ Typ. (1) ___ Max. ___ Unit V µA 100 100 ___ ___ 4000 1500 ___ ___ 0 tRC(2) ns ns 2720 tbl 07 NOTES: 1. VCC = 2V, TA = +25°C, and are not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but not production tested. Data Retention Waveform DATA RETENTION MODE VCC 4.5V tCDR CE VIH VDR VDR ≥ 2V 4.5V tR VIH 2720 drw 05 AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1 and 2 2720 tbl 08 +5V 1250Ω DATAOUT 775Ω 30pF 2720 drw 06 , +5V 1250Ω DATAOUT 775Ω 5pF * 2720 drw 07 , Figure 1. AC Output Test Load Figure 2. Output Test Load (for tLZ , tHZ, t WZ, tOW) *Including scope and jig 5 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(3,4) 7134X20 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) (1,2) (2) 7134X25 Com'l & Military Min. Max. 7134X35 Com'l & Military Min. Max. Unit Parameter Min. Max. 20 ____ ____ ____ ____ 25 ____ ____ ____ ____ 35 ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns 2720 tbl 09a 20 20 15 ____ ____ 25 25 15 ____ ____ 35 35 20 ____ ____ 0 0 ____ 0 0 ____ 0 0 ____ Output High-Z Time 15 ____ 15 ____ 20 ____ Chip Enable to Power Up Time 0 ____ 0 ____ 0 ____ Chip Disable to Power Down Time (2) 20 25 35 7134X45 Com'l & Military Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) (1,2) (2) 7134X55 Com'l, Ind & Military Min. Max. 7134X70 Com'l & Military Min. Max. Unit Parameter Min. Max. 45 ____ ____ ____ ____ 55 ____ ____ ____ ____ 70 ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns 2720 tbl 09b 45 45 25 ____ ____ 55 55 30 ____ ____ 70 70 40 ____ ____ 0 5 ____ 0 5 ____ 0 5 ____ Output High-Z Time 20 ____ 25 ____ 30 ____ Chip Enable to Power Up Time 0 ____ 0 ____ 0 ____ Chip Disable to Power Down Time (2) 45 50 50 NOTES: 1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. 'X' in part number indicates power rating (SA or LA). 4. Industrial temperature: for other speeds, packages and powers contact your sales office. 6 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle No. 1, Either Side(1,2,4) tRC ADDRESS tAA(5) tOH DATAOUT PREVIOUS DATA VALID tOH DATA VALID 2720 drw 08 Timing Waveform of Read Cycle No. 2, Either Side(1,3) tACE CE tAOE(4) OE tLZ(1) DATAOUT tLZ(1) ICC CURRENT ISB tPU 50% tPD 50% 2720 drw 09 tHZ(2) tHZ(2) VALID DATA(4) NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/W = VIH. 4. Start of valid data depends on which timing becomes effective, tAOE, tACE or tAA 5. tAA for RAM Address Access and tSAA for Semaphore Address Access. 7 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5,7) 7134X20 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tWDD tDDD Write Cycle Time Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (3) (1,2) (1,2) 7134X25 Com'l & Military Min. Max. 7134X35 Com'l & Military Min. Max. Unit Parameter Min. Max. 20 15 15 0 15 0 15 ____ ____ ____ ____ ____ ____ ____ ____ 25 20 20 0 20 0 15 ____ ____ ____ ____ ____ ____ ____ ____ 35 30 30 0 25 0 20 ____ ____ ____ ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns ns 2720 tbl 10a 15 ____ 15 ____ 20 ____ 0 ____ 0 ____ 3 ____ Write Enable to Output in High-Z Output Active from End-of-Write Write Pulse to Data Delay (4) 15 ____ 15 ____ 20 ____ (1,2,3) 3 ____ 3 ____ ____ 3 ____ ____ 40 30 7134X45 Com'l & Military 50 30 60 35 7134X70 Com'l & Military Write Data Valid to Read Data Delay (4,6) ____ 7134X55 Com'l, Ind & Military Min. Max. Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tWDD tDDD Write Cycle Time Parameter Min. Max. Min. Max. Unit 45 40 40 0 40 0 20 ____ ____ ____ ____ ____ ____ ____ ____ 55 50 50 0 50 0 25 ____ ____ ____ ____ ____ ____ ____ ____ 70 60 60 0 60 0 30 ____ ____ ____ ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns ns 2720 tbl 10b Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (3) (1,2) (1,2) 20 ____ 25 ____ 30 ____ 3 ____ 3 ____ 3 ____ Write Enable to Output in High-Z Output Active from End-of-Write Write Pulse to Data Delay (4) 20 ____ 25 ____ 30 ____ (1,2,3) 3 ____ 3 ____ ____ 3 ____ ____ 70 45 80 55 90 70 Write Data Valid to Read Data Delay (4,6) ____ NOTES: 1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and t OW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”. 5. 'X' in part number indicates power rating (SA or LA). 6. tDDD = 35ns for military temperature range. 7. Industrial temperature: for other speeds, packages and powers contact your sales office. 8 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read(1,2,3) tWC ADDR "A" MATCH tWP R/W "A" (1) tAW tDW DATAIN "A" VALID ADDR "B" MATCH tWDD DATAOUT "B" NOTES: 1. Write cycle parameters should be adhered to, in order to ensure proper writing. 2. CEL = CER = VIL. OE"B" = VIL. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". VALID tDDD 2720 drw 10 Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tAS(6) tAW CE tWP(2) R/W tLZ DATAOUT (7) OE tWR(3) tHZ (7) tWZ (7) tOW (4) tHZ(7) (4) tDW DATAIN tDH NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP ) of a CE =V IL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/ W) is asserted last. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 2720 drw 11 9 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,4) tWC ADDRESS tAW CE tAS(5) R/W tDW DATAIN 2720 drw 12 tEW(2) tWR(3) tDH NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP ) of a CE =V IL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle. 4. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 5. Timing depends on which enable signal (CE or R/ W) is asserted last. The IDT7134 provides two ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port’s OE turns on the output drivers when set LOW. Non-contention READ/WRITE conditions are illustrated in the table below. Functional Description Truth Table I – Read/Write Control Left or Right Port(1) R/ W X X L H X CE H H L L X OE X X X L H D0-7 Z Z DATAIN DATAOUT Z Function Port Deselected and in Power-Down Mode, ISB2 o r ISB4 CER = C EL = H, Power Down Mode ISB1 o r ISB3 Data on port written into memory Data in memory output on port High impedance outputs 2720 tbl 11 NOTE: 1. A0L - A11L ≠ A0R - A11R "H" = VIH, "L" = VIL, "X" = Don’t Care, and "Z" = High Impedance 10 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Ordering Information IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank I(1) B P C J L48 F 20 25 35 45 55 70 LA SA 7134 Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Military (-55°C to +125°C) Compliant to MIL-PRF-38535 QML 48-pin Plastic DIP (P48-1) 48-pin Ceramic DIP (C48-2) 52-pin PLCC (J52-1) 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1) Commercial Only Commercial & Military Commercial & Military Commercial & Military Commercial, Industrial & Military Commercial & Military Low Power Standard Power 32K (4K x 8-Bit) Dual-Port RAM 2720 drw 13 Speed in nanoseconds NOTE: 1. Industrial temperature is available for PLCC packages in standard power. For other speeds, packages and powers contact your sales office. Datasheet Document History 3/25/99 Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 Added additional notes to pin configurations Changed drawing format 6/9/99: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-5166 fax: 408-492-8674 www.idt.com 11 for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.