IDT71V016SA15BF8

3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Features x x IDT71V016SA Description The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71V016 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA. x x x x x x 64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times — Commercial: 10/12/15/20ns — Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Single 3.3V power supply Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball Plastic FBGA packages Functional Block Diagram Output Enable Buffer OE A0 – A15 Address Buffers Row / Column Decoders I/O15 Chip Enable Buffer Sense Amps and Write Drivers 8 Low Byte I/O Buffer 8 8 High Byte I/O Buffer 8 CS I/O8 WE Write Enable Buffer 64K x 16 Memory Array 16 I/O7 I/O0 BHE Byte Enable Buffers BLE 3834 drw 01 JUNE 2002 1 ©2000 Integrated Device Technology, Inc. DSC-3834/06 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Pin Configurations A4 A3 A2 A1 A0 CS I/O0 I/O1 I/O2 I/O3 VDD VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SO44-1 SO44-2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 1 A B C D E F G H BLE I/O8 I/O9 VSS VDD I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 I/O12 I/O13 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CS I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VDD VSS I/O6 I/O7 NC 3834 tbl 02a FBGA (BF48-1) Top View Pin Description A0 – A15 CS WE OE BHE BLE I/O0 – I/O15 VDD VSS Address Inputs Chip Select Write Enable Output Enable High Byte Enable Low Byte Enable Data Input/Output 3.3V Power Ground 3834 drw 02 Input Input Input Input Input Input I/O Power Gnd 3834 tbl 01 SOJ/TSOP Top View Truth Table(1) CS H L L L L L L L L OE X L L L X X X H X WE X H H H L L L H X BLE X L H L L L H X H BHE X H L L L H L X H I/O0-I/O7 High-Z DATAOUT High-Z DATAOUT DATAIN DATAIN High-Z High-Z High-Z I/O8-I/O15 High-Z High-Z DATAOUT DATAOUT DATAIN High-Z DATAIN High-Z High-Z Function Deselected – Standby Low Byte Read High Byte Read Word Read Word Write Low Byte Write High Byte Write Outputs Disabled Outputs Disabled NOTE: 1. H = VIH, L = VIL, X = Don't care. 3834 tbl 02 6.42 2 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Symbol VDD VIN, VOUT TBIAS TSTG PT IOUT Rating Supply Voltage Relative to VSS Terminal Voltage Relative to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value –0.5 to +4.6 –0.5 to VDD+0.5 –55 to +125 –55 to +125 1.25 50 Unit V V Recommended Operating Temperature and Supply Voltage Grade Commercial Industrial Temperature 0°C to +70°C -40°C to +85°C VSS 0V 0V VDD See Below See Below 3834 tbl 04 o o C C W mA Recommended DC Operating Conditions Symbol VDD VDD (1) (2) Parameter Supply Voltage Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.15 3.0 0 2.0 –0.3(4) Typ. 3.3 3.3 0 ____ ____ Max. 3.6 3.6 0 VDD+0.3(3) 0.8 Unit V V V V V 3834 tbl 05 3834 tbl 03 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Vss VIH VIL Capacitance (TA = +25°C, f = 1.0MHz, SOJ package) Symbol CIN CI/O Parameter (1) Conditions VIN = 3dV VOUT = 3dV Max. 6 7 Unit pF pF Input Capacitance I/O Capacitance NOTES: 1. For 71V016SA10 only. 2. For all speed grades except 71V016SA10. 3. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 4. VIL (min.) = –2V for pulse width less than 5ns, once per cycle. 3834 tbl 06 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. DC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) IDT71V016SA Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VDD = M ax., VIN = VSS to VDD VDD = M ax., CS = VIH, VOUT = VSS to VDD IOL = 8mA, VDD = M in. IOH = –4mA, VDD = M in. Min. ___ ___ ___ Max. 5 5 0.4 ___ Unit µA µA V V 3834 tbl 07 2.4 DC Electrical Characteristics(1,2) (VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V) 71V016SA10 Symbol ICC Parameter Dynamic Operating Current CS ≤ VLC, Outputs Open, VDD = M ax., f = fMAX(3) Dynamic Standby Power Supply Current CS ≥ VHC, Outputs Open, VDD = M ax., f = fMAX(3) Full Standby Power Supply Current (static) CS ≥ VHC, Outputs Open, VDD = Max., f = 0(3) Max. Typ. (4) 71V016SA12 Com'l 150 120 40 10 Ind 160 -45 10 71V016SA15 Com'l 130 110 35 10 Ind 130 -35 10 71V016SA20 Com'l 120 110 30 10 Ind 120 -30 10 mA mA 3834 tbl 08 Com'l Only 160 125 45 10 Unit mA ISB ISB1 NOTES: 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD – 0.2V (High). 3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing . 4. Typical values are measured at 3.3V, 25°C and with equal read and write cycles. 6.42 3 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 1.5ns 1.5V 1.5V See Figure 1, 2 and 3 3834 tbl 09 AC Test Loads 3.3V +1.5V 50Ω I/O Z0 = 50Ω 30pF 3834 drw 03 320Ω DATA OUT 5pF* 350Ω 3834 drw 04 *Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 7 ∆tAA, tACS (Typical, ns) 5 4 3 • • • 6 2 1 · • • • 8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF) 3834 drw 05 Figure 3. Output Capacitive Derating 6.42 4 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics Symbol READ CYCLE tRC tAA tACS tCLZ(1) tCHZ(1) tOE tOLZ(1) tOHZ(1) tOH tBE tBLZ(1) tBHZ(1) Read Cycle Time Address Access Time Chip Select Access Time Chip Select Low to Output in Low-Z Chip Select High to Output in High-Z Output Enable Low to Output Valid Output Enable Low to Output in Low-Z Output Enable High to Output in High-Z Output Hold from Address Change Byte Enable Low to Output Valid Byte Enable Low to Output in Low-Z Byte Enable High to Output in High-Z Parameter (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) 71V016SA10(2) Min. Max. 71V016SA12 Min. Max. 71V016SA15 Min. Max. 71V016SA20 Min. Max. Unit 10 ____ ____ ____ 12 ____ ____ ____ 15 ____ ____ ____ 20 ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns 10 10 ____ 12 12 ____ 15 15 ____ 20 20 ____ 4 ____ 4 ____ 5 ____ 5 ____ 5 5 ____ 6 6 ____ 6 7 ____ 8 8 ____ ____ ____ ____ ____ 0 ____ 0 ____ 0 ____ 0 ____ 5 — 5 ____ 6 — 6 ____ 6 — 7 ____ 8 — 8 ____ 4 — 0 ____ 4 — 0 ____ 4 — 0 ____ 4 ____ 0 ____ 5 6 6 8 WRITE CYCLE tWC tAW tCW tBW tAS tWR tWP tDW tDH tOW(1) tWHZ(1) Write Cycle Time Address Valid to End of Write Chip Select Lo w to End of Write Byte Enable Lo w to End of Write Address Set-up Time Address Hold from End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Enable High to Output in Low-Z Write Enable Low to Output in High-Z 10 7 7 7 0 0 7 5 0 3 ____ ____ ____ 12 8 8 8 0 0 8 6 0 3 ____ ____ ____ 15 10 10 10 0 0 10 7 0 3 ____ ____ ____ 20 12 12 12 0 0 12 9 0 3 ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns 3834 tbl 10 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 5 6 6 8 NOTES: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 2. 0°C to +70°C temperature range only. Timing Waveform of Read Cycle No. 1(1,2,3) tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID 3834 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW. 6.42 5 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 2(1) tRC ADDRESS tAA OE tOE CS tCLZ BHE, BLE tBE tBLZ DATAOUT (3) (2) (3) tOH tOHZ (3) tOLZ tACS (2) (3) tCHZ (3) tBHZ (3) DATA OUT VALID 3834 drw 07 NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured ±200mV from steady state. Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tCW BHE , BLE tWR WE tAS (3) (5) (2) tCHZ (5) tBW (5) tBHZ tWP tWHZ DATAOUT PREVIOUS DATA VALID tOW tDW DATAIN DATAIN VALID tDH (5) DATA VALID 3834 drw 08 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6.42 6 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS tAS tBW BHE, BLE tWP WE tWR tCW (2) DATAOUT tDW DATAIN tDH DATAIN VALID 3834 drw 09 Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4) tWC ADDRESS tAW CS tCW tAS BHE, BLE tWP WE tWR (2) tBW DATAOUT tDW DATAIN DATAIN VALID 3834 drw 10 tDH NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6.42 7 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Ordering Information IDT 71V016 Device Type SA Power XX Speed XXX Package X Process/ Temperature Range X Tape & Reel 8 Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Y PH BF 400-mil SOJ (SO44-1) 400-mil TSOP Type II (SO44-2) 7.0 x 7.0 mm FBGA (BF48-1) 10** 12 15 20 Speed in nanoseconds ** Commercial temperature range only. 3834 drw 11 6.42 8 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges Datasheet Document History 1/7/00 Pp. 1, 3, 5, 8 Pg. 2 Pg. 6 Pg. 7 Pg. 9 Pg. 3 Pg. 5 Pg. 8 Pg. 8 Updated to new format Added Industrial Temperature range offerings Numbered I/Os and address pins on FBGA Top View Revised footnotes on Write Cycle No. 1 diagram Revised footnotes on Write Cycle No. 2 and No. 3 diagrams Added Datasheet Document History Tighten ICC and ISB. Tighten tCLZ, tCHZ, tOHZ, tBHZ and tWHZ Removed footnote "available in 15ns and 20ns only" Added tape and reel field to ordering information 08/30/00 08/22/01 06/20/02 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 9 for Tech Support: sramhelp@idt.com 800-544-7726, x4033 The IDT logo is a registered trademark of Integrated Device Technology, Inc.