IDT71V67903S80BQ

256K X 36, 512K X 18 IDT71V67703 3.3V Synchronous SRAMs IDT71V67903 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect Features x x x x x x x x 256K x 36, 512K x 18 memory configurations Supports fast access times: – 7.5ns up to 117MHz clock frequency – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA). Description The IDT71V67703/7903 are high-speed SRAMs organized as 256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V67703/7903 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71V67703/7903 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). Pin Description Summary A0-A18 Address Inputs Chip Enable Chip Selects Output Enable Global Write Enable Byte Write Enable Individual Byte Write Selects Clock Burst Address Advance Address Status (Cache Controller) Address Status (Processor) Linear / Interleaved Burst Order Sleep Mode Data Input / Output Core Power, I/O Power Ground Input Input Input Input Input Input Input Input Input Input Input Input Input I/O Supply Supply Synchronous Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Synchronous Synchronous DC Asynchronous Synchronous N/A N/A 5309 tbl 01 CE CS0, C S1 OE GW BWE BW1, BW2, BW3, BW4(1) CLK ADV ADSC ADSP LBO ZZ I/O0-I/O31, I/OP1-I/OP4 VDD, VDDQ VSS NOTE: 1. BW3 and BW4 are not applicable for the IDT71V67903. DECEMBER 2003 1 ©2002 Integrated Device Technology, Inc. DSC-5309/05 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Pin Definitions(1) Symbol A 0-A18 Pin Function Address Inputs Address Status (Cache Controller) Address Status (Processor) Burst Address Advance Byte Write Enable I/O I I I I Active N/A LOW LOW LOW Description Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK and ADSC Low or ADSP Low and C E Low. Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the address registers with new addresses. Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address registers with new addresses. ADSP is gated by C E. Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not incremented; that is, there is no address advance. Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle. Synchronous byte write enables. BW1 c ontrols I/O0-7, I/OP1, BW2 c ontrols I/O8-15, I/OP2, etc. Any active byte write causes all outputs to be disabled. Synchronous chip enable. C E is used with CS 0 and C S1 to enable the IDT71V67703/7903. CE also gates ADSP. This is the clock input. All timing references for the device are made with respect to this input. Synchronous active HIGH chip select. CS 0 is used with C E and C S1 to enable the chip. Synchrono us active LOW chip select. C S1 is used with C E and CS0 to enable the chip. Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of CLK. GW s upersedes individual byte write enables. Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data output path is flow-through (no output register). Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state while the device is operating. Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a highimpedance state. 3.3V core power supply. 3.3V I/O Supply. Ground. NC pins are not electrically connected to the device. Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V67703/7903 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. 5309 tbl 02 ADSC ADSP ADV BWE I LOW BW1-BW4 CE CLK CS0 Individual Byte Write Enables Chip Enable Clock Chip Select 0 Chip Select 1 Global Write Enable Data Input/Output Linear Burst Order I I I I I I I/O I LOW LOW N/A HIGH LOW LOW N/A LOW CS1 GW I/O0-I/O31 I/OP1-I/OP4 LBO OE Output Enable I LOW V DD VDDQ V SS NC ZZ Power Supply Power Supply Ground No Connect Sleep Mode N/A N/A N/A N/A 1 N/A N/A N/A N/A HIGH NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.42 2 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Functional Block Diagram LBO AD V CEN Burst Sequence INTERNAL ADDRESS CLK AD SC ADSP CLK EN ADDRESS REGISTER Byte 1 Write Register Binary Counter CLR 2 Burst Logic 18/19 A0* A1* Q0 Q1 256K x 36/ 512K x 18BIT MEMORY ARRAY 2 18/19 A0,A1 A2 - A18 36/18 36/18 A0–A17/18 GW BW E BW 1 Byte 1 Write Driver 9 Byte 2 Write Register Byte 2 Write Driver BW 2 Byte 3 Write Register 9 Byte 3 Write Driver BW 3 Byte 4 Write Register 9 Byte 4 Write Driver BW 4 9 CE CS0 CS 1 D Q Enable Register DATA INPUT REGISTER CLK EN ZZ Powerdown OE OE I/O0–I/O31 I/OP1–I/OP4 36/18 OUTPUT BUFFER , 5309 drw 01 6.42 3 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Symbol VTERM (2) Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Commercial -0.5 to +4.6 -0.5 to VDD -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 -0 to +70 -55 to +125 -55 to +125 2.0 50 Unit V V V V o Recommended Operating Temperature Supply Voltage Grade Commercial Industrial Temperature(1) 0°C to +70°C -40°C to +85°C VSS 0V 0V VDD 3.3V±5% 3.3V±5% V DDQ 3.3V±5% 3.3V±5% 5309 tbl 04 VTERM(3,6) VTERM(4,6) VTERM(5,6) TA (7) NOTE: 1. TA is the "instant on" case temperature. C C C Recommended DC Operating Conditions Symbol Parameter Core Supply Voltage I/O Supply Voltage Supply Voltage Input High Voltage - Inputs Input High Voltage - I/O Input Low Voltage Min. 3.135 3.135 0 2.0 2.0 -0.3 (1) Typ. 3.3 3.3 0 ____ Max. 3.465 3.465 0 VDD +0.3 VDDQ +0.3 0.8 Unit V V V V V V 5309 tbl 05 TBIAS TSTG PT IOUT o VDD V DDQ VSS o W mA 5309 tbl 03 VIH VIH VIL ____ ____ NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supplies have ramped up. Power supply sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed V DDQ during power supply ramp up. 7. TA is the "instant on" case temperature. NOTE: 1. VIL (min) = -1.0V for pulse width less than t CYC/2, once per cycle. 100-Pin TQFP Capacitance (TA = +25° C, f = 1.0MHz) Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 5 7 Unit pF pF 5309 tbl 07 165 fBGA Capacitance (TA = +25° C, f = 1.0MHz) Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 7 7 Unit pF pF 5309 tbl 07b 119 BGA Capacitance (TA = +25° C, f = 1.0MHz) Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 7 7 Unit pF pF 5309 tbl 07a NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 6.42 4 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Pin Configuration – 256K x 36, 100-Pin TQFP A6 A7 CE CS0 BW4 BW3 BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VSS(1) VDD NC VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/OP2 I/O15 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS NC VDD ZZ(2) I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1 5309 drw 02a , LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD Top View NOTES: 1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL. 2. Pin 64 can be left unconnected and the device will always remain in active mode. 6.42 5 NC A17 A10 A11 A12 A13 A14 A15 A16 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Pin Configuration – 512K x 18, 100-Pin TQFP A6 A7 CE CS0 NC NC BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC VDDQ VSS NC NC I/O8 I/O9 VSS VDDQ I/O10 I/O11 VSS(1) VDD NC VSS I/O12 I/O13 VDDQ VSS I/O14 I/O15 I/OP2 NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 NC NC VDDQ VSS NC I/OP1 I/O7 I/O6 VSS VDDQ I/O5 I/O4 VSS NC VDD ZZ(2) I/O3 I/O2 VDDQ VSS I/O1 I/O0 NC NC VSS VDDQ NC NC NC 5309 drw 02b , NOTES: 1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL. 2. Pin 64 can be left unconnected and the device will always remain in active mode. LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC A18 A11 A12 A13 A14 A15 A16 A17 Top View 6.42 6 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Pin Configuration – 256K x 36, 119 BGA 1 A B C D E F G H J K L M N P R T U VDDQ NC NC I/O16 I/O17 VDDQ I/O20 I/O22 VDDQ I/O24 I/O25 VDDQ I/O29 I/O31 NC NC VDDQ 2 A6 CS0(4) A7 I/OP3 I/O18 I/O19 I/O21 I/O23 V DD I/O26 I/O27 I/O28 I/O30 I/OP4 A5 NC DNU(3) 3 A4 A3 A2 VSS VSS VSS BW3 VSS NC VSS BW4 VSS VSS VSS LBO A 10 DNU(3) 4 ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 A0 VDD A11 DNU(3) 5 A8 A9 A12 VSS VSS VSS BW2 VSS NC VSS BW1 VSS VSS VSS VSS(1) A14 DNU(3) 6 A16 A17 A15 I/OP2 I/O13 I/O12 I/O11 I/O9 VDD I/O6 I/O4 I/O3 I/O2 I/OP1 A13 NC DNU(3) 7 VDDQ NC NC I/O15 I/O14 VDDQ I/O10 I/O8 VDDQ I/O7 I/O5 VDDQ I/O1 I/O 0 NC ZZ(2) VDDQ 5309 drw 02c Top View Pin Configuration – 512K x 18, 119 BGA 1 A B C D E F G H J K L M N P R T U VDDQ NC NC I/O8 NC VDDQ NC I/O11 VDDQ NC I/O13 VDDQ I/O15 NC NC NC VDDQ 2 A6 CS0 A7 NC I/O9 NC I/O10 NC V DD I/O12 NC I/O14 NC I/OP2 A5 A10 DNU(3) (4) 3 A4 A3 A2 VSS VSS VSS BW2 VSS NC VSS VSS VSS VSS VSS LBO A 15 DNU(3) 4 ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 A0 VDD NC DNU(3) 5 A8 A9 A13 VSS VSS VSS VSS VSS NC VSS BW1 VSS VSS VSS VSS(1) A14 DNU(3) 6 A16 A18 A17 I/OP1 NC I/O6 NC I/O4 VDD NC I/O2 NC I/O1 NC A12 A11 DNU(3) 7 VDDQ NC NC NC I/O7 VDDQ I/O5 NC VDDQ I/O3 NC VDDQ NC I/O0 NC ZZ (2) VDDQ 5309 drw 02d , Top View NOTES: 1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL. 2. T7 can be left unconnected and the device will always remain in active mode. 3. DNU= Do not use; these signals can either be left unconnected or tied to Vss. 4. On future 18M devices CS0 will be removed, B2 will be used for address expansion. 6.42 7 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Pin Configuration – 256K x 36, 165 fBGA 1 A B C D E F G H J K L M N P R NC (3) 2 A7 A6 NC I/O16 I/O18 I/O20 I/O22 NC I/O24 I/O26 I/O28 I/O30 NC NC (3) 3 4 5 6 7 8 9 10 A8 A9 NC I/O15 I/O13 I/O11 I/O9 NC I/O7 I/O5 I/O3 I/O1 NC A14 A15 11 NC NC(3) I/OP2 I/O14 I/O12 I/O10 I/O8 ZZ(2) I/O6 I/O4 I/O2 I/O0 I/OP1 A17 A16 5309tbl 17a CE CS0 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A5 A4 BW3 BW4 V SS V DD V DD V DD V DD V DD V DD V DD V DD V DD V SS A2 A3 BW2 BW1 V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS NC DNU (4) CS1 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC(3) A1 A0 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC DNU (4) ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A10 A11 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A13 A12 NC I/OP3 I/O17 I/O19 I/O21 I/O23 VSS (1) I/O25 I/O27 I/O29 I/O31 I/OP4 NC LBO NC(3) DNU(4) DNU(4) Pin Configuration – 512K x 18, 165 fBGA 1 A B C D E F G H J K L M N P R NC(3) NC NC NC NC NC NC VSS(1) I/O12 I/O13 I/O14 I/O15 I/OP2 NC 2 A7 A6 NC I/O8 I/O9 I/O10 I/O11 NC NC NC NC NC NC NC (3) 3 4 5 NC 6 7 8 9 10 A8 A9 NC NC NC NC NC NC I/O3 I/O2 I/O1 I/O0 NC A15 A16 11 A10 NC(3) I/OP1 I/O7 I/O6 I/O5 I/O4 ZZ(2) NC NC NC NC NC A18 A17 5309 tbl 17b CE CS 0 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A5 A4 BW2 NC V SS V DD V DD V DD V DD V DD V DD V DD V DD V DD V SS A2 A3 CS1 CLK V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS NC (3) BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC DNU (4) ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A11 A12 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A14 A13 BW1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC DNU (4) A1 A0 LBO NC(3) DNU(4) DNU(4) NOTES: 1. H1 does not have to be directly connected to V SS, as long as the input voltage is < VIL. 2. H11 can be left unconnected and the device will always remain in active mode. 3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively. 4. DNU= Do not use; these signals can either be left unconnected or tied to Vss. 6.42 8 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 5%) Symbol |ILI| |ILI| |ILO| VOL VOH Parameter Input Leakage Current Test Conditions VDD = Max., VIN = 0V to V DD VDD = Max., VIN = 0V to V DD VOUT = 0V to V CC IOL = +8mA, VDD = Min. IOH = -8mA, VDD = Min. Min. ___ Max. 5 30 5 0.4 ___ Unit µA µA µA V V 5309 tbl 08 LBO Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage ___ ___ ___ 2.4 NOTE: 1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ in will be internally pulled to V SS if not actively driven. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1) 7.5ns Symbol IDD ISB1 ISB2 IZZ Parameter Operating Power Supply Current Test Conditions Device Se lected, Outputs Open, V DD = Max., VDDQ = Max., VIN > VIH o r < VIL, f = fMAX(2) Com'l 265 50 145 50 Ind 285 70 165 70 8ns Com'l 210 50 140 50 Ind 230 70 160 70 8.5ns Unit Com'l 190 50 135 50 Ind mA 210 mA 70 mA 155 70 mA 5309 tbl 09 CMOS Standby Power Supply Current Device Deselected, Outputs Open, VDD = Max., VDDQ = Max., VIN > VHD o r < VLD, f = 0(2,3) Clock Running Power Supply Current Full Sleep Mode Supply Current Device Deselected, Outputs Open, V DD = Max., VDDQ = Max., VIN > VHD o r < VLD, f = fMAX (2,.3) ZZ > VHD, VDD = Max. NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing. 3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V. AC Test Conditions (VDDQ = 3.3V/2.5V) Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC Test Load 0 to 3V AC Test Load 2ns 1.5V 1.5V See Figure 1 5309 tbl 10 VDDQ/2 50Ω I/O Z0 = 50Ω 5309 drw 03 , 6 5 4 ∆tCD 3 (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200 5309 drw 05 Figure 1. AC Test Load , Figure 2. Lumped Capacitive Load, Typical Derating 6.42 9 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Synchronous Truth Table (1,3) Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. OE is an asynchronous input. 3. ZZ - low for the table. Address Used None None None None None External External External External External External External Next Next Next Next Next Next Next Next Next Next Next Next Current Current Current Current Current Current Current Current Current Current Current Current CE H L L L L L L L L L L L X X X X H H H H X X H H X X X X H H H H X X H H CS0 X X L X L H H H H H H H X X X X X X X X X X X X X X X X X X X X X X X X CS 1 X H X H X L L L L L L L X X X X X X X X X X X X X X X X X X X X X X X X ADSP X L L X X L L H H H H H H H H H X X X X H H X X H H H H X X X X H H X X ADSC L X X L L X X L L L L L H H H H H H H H H H H H H H H H H H H H H H H H ADV X X X X X X X X X X X X L L L L L L L L L L L L H H H H H H H H H H H H GW X X X X X X X H H H H L H H H H H H H H H L H L H H H H H H H H H L H L BWE X X X X X X X H L L L X H H X X H H X X L X L X H H X X H H X X L X L X BWx X X X X X X X X H H L X X X H H X X H H L X L X X X H H X X H H L X L X OE (2) X X X X X L H L L H X X L H L H L H L H X X X X L H L H L H L H X X X X CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ I/O HI-Z HI-Z HI-Z HI-Z HI-Z DOUT HI-Z DOUT DOUT HI-Z DIN DIN DOUT HI-Z DOUT HI-Z DOUT HI-Z DOUT HI-Z DIN DIN DIN DIN DOUT HI-Z DOUT HI-Z DOUT HI-Z DOUT HI-Z DIN DIN DIN DIN 5309 tbl 11 6.42 10 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Synchronous Write Function Truth Table (1, 2) Operation Read Read Write all Bytes Write all Bytes Write Byte 1(3) Write Byte 2(3) Write Byte 3(3) Write Byte 4(3) GW H H L H H H H H BWE H L X L L L L L BW 1 X H X L L H H H BW 2 X H X L H L H H BW 3 X H X L H H L H BW 4 X H X L H H H L 5309 tbl 12 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. BW3 and BW4 are not applicable for the IDT71V67903. 3. Multiple bytes may be selected during the same cycle. Asynchronous Truth Table (1) Operation(2) Read Read Write Deselected Sleep Mode OE L H X X X ZZ L L L L H I/O Status Data Out High-Z High-Z – Data In High-Z High-Z Power Active Active Active Standby Sleep 5309 tbl 13 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements. Interleaved Burst Sequence Table ( LBO=VDD) Sequence 1 A1 First Address Second Address Third Address Fourth Address(1) 0 0 1 1 A0 0 1 0 1 Sequence 2 A1 0 0 1 1 A0 1 0 1 0 Sequence 3 A1 1 1 0 0 A0 0 1 0 1 Sequence 4 A1 1 1 0 0 A0 1 0 1 0 5309 tbl 14 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. Linear Burst Sequence Table ( LBO=VSS) Sequence 1 A1 First Address Second Address Third Address Fourth Address(1) 0 0 1 1 A0 0 1 0 1 Sequence 2 A1 0 1 1 0 A0 1 0 1 0 Sequence 3 A1 1 1 0 0 A0 0 1 0 1 Sequence 4 A1 1 0 0 1 A0 1 0 1 0 5309 tbl 15 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. 6.42 11 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges) 7.5ns Symbol Parameter Min. Max. Min. 8ns Max. 8.5ns Min. Max. Unit Clock Parameter tCYC tCH(1) tCL(1) Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width 8.5 3 3 ____ 10 4 4 ____ 11.5 4.5 4.5 ____ ns ns ns ____ ____ ____ ____ ____ ____ Output Parameters tCD tCDC tCLZ(2) tCHZ(2) tOE tOLZ(2) tOHZ(2) Clock High to Valid Data Clock High to Data Change Clock High to Output Active Clock High to Data High-Z Output Enable Access Time Output Enable Low to Output Active Output Enable High to Output High-Z ____ 7.5 ____ ____ 8 ____ ____ 8.5 ____ ns ns ns ns ns ns ns 2 0 2 ____ 2 0 2 ____ 2 0 2 ____ ____ ____ ____ 3.5 3.5 ____ 3.5 3.5 ____ 3.5 3.5 ____ 0 ____ 0 ____ 0 ____ 3.5 3.5 3.5 Set Up Times tSA tSS tSD tSW tSAV tSC Address Setup Time Address Status Setup Time Data In Setup Time Write Setup Time Address Advance Setup Time Chip Enable/Select Setup Time 1.5 1.5 1.5 1.5 1.5 1.5 ____ 2 2 2 2 2 2 ____ 2 2 2 2 2 2 ____ ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ Hold Times tHA tHS tHD tHW tHAV tHC Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Address Advance Hold Time Chip Enable/Select Hold Time 0.5 0.5 0.5 0.5 0.5 0.5 ____ 0.5 0.5 0.5 0.5 0.5 0.5 ____ 0.5 0.5 0.5 0.5 0.5 0.5 ____ ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ Sleep Mode and Configuration Parameters tZZPW tZZR(3) tCFG(4) ZZ Pulse Width ZZ Recovery Time Configuration Set-up Time 100 100 34 ____ 100 100 40 ____ 100 100 50 ____ ns ns ns 5309 tbl 16 ____ ____ ____ ____ ____ ____ NOTES: 1. Measured as HIGH above VIH and LOW below VIL. 2. Transition is measured ±200mV from steady-state. 3. Device must be deselected when powered-up from sleep mode. 4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation. 6.42 12 tCYC CLK tCH tCL tSS tHS AD SP (1) ADSC tHA Ax tSW tHW Ay tSA ADDRESS G W , BW E , BW x tHC tSAV tHAV tSC C E , CS 1 (Note 3) Timing Waveform of Flow-Through Read Cycle (1,2) IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 13 tOE tCD tOHZ tOLZ O1(Ax) O1(Ay) O2(Ay) ADV HIGH suspends burst AD V OE tCDC (Burst wraps around to its initial state) tCHZ O3(Ay) O4(Ay) O1(Ay) O2(Ay) DATAOUT Output Disabled Flow-through Read Burst Flow-through Read 5309 drw 06 NOTES: 1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. , tCYC CLK tCH tCL (2) tSS tHS ADSP tSA tHA Ax Ay tSW tHW Az ADDRESS GW ADV OE tSD tHD tOE tCD tOLZ tOHZ O1(Ax) tCD Write I1(Ay) tCLZ Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3) IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 14 DATAIN tCDC O1(Az) O2(Az) O3(Az) O4(Az) DATAOUT Single Read Flow-through Burst Read 5309 drw 07 NOTES: 1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. , tCYC CLK tCH tCL tSS tHS ADSP (1) ADSC tSA tHA Ax G W is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge ADDRESS Ay Az tHW tSW GW tSC tHC CE , CS 1 tSAV tHAV (Note 3) Timing Waveform of Write Cycle No. 1 - GW Controlled IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 15 (ADV suspends burst) ADV OE tSD I1(Ax) tOHZ I1(Ay) I2(Ay) I2(Ay) (2) tHD DATAIN I3(Ay) I4(Ay) I1(Az) I2(Az) I3(Az) DATAOUT O3(Aw) O4(Aw) 5309 drw 08 (1,2,3) NOTES: 1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle. 2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. , tCYC CLK tCH tCL tSS tHS ADSP ADSC tSA tHA Ax BW E is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge ADDRESS Ay Az tHW tSW BWE BW x is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge tHW tSW BWx tSC tHC CE, CS1 tSAV (Note 3) Timing Waveform of Write Cycle No. 2 - Byte Controlled IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 16 (AD V HIGH suspends burst) ADV OE tSD I1(Ax) tOHZ I1(Ay) I2(Ay) I2(Ay) I3(Ay) I4(Ay) I1(Az) tHD DATAIN I2(Az) I3(Az) DATAOUT Single Write O3(Aw) O4(Aw) Burst Write Extended Burst Write 5309 drw 09 Burst Read (1,2,3) NOTES: 1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle. 2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. , tCYC CLK tCH tCL tSS tHS ADSP ADSC tHA Ax Az tSA ADDRESS GW tHC tSC CE,CS 1 (Note 4) ADV tOE Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3) IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 17 O1(Ax) tZZPW OE tOLZ DATAOUT tZZR ZZ Single Read Snooze Mode 5309 drw 13 , NOTES: 1. Device must power up in deselected Mode. 2. LBO is Don't Care for this cycle. 3. It is not necessary to retain the state of the input registers throughout the Power-down cycle. 4. CS0 timing transitions are identical but inverted to the CE and CS1 signaals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Non-Burst Read Cycle Timing Waveform CLK AD SP AD SC ADDRESS Av Aw Ax Ay Az G W , BW E , BW x CE , CS 1 CS0 OE DATAOUT (Av) (Aw) (Ax) (Ay) 5309 drw 10 NOTES: 1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. 3. For read cycles, ADSP and ADSC function identically and are therefore interchangable. , Non-Burst Write Cycle Timing Waveform CLK AD SP ADSC ADDRESS Av Aw Ax Ay Az GW CE , CS 1 CS0 DATAIN (Av) (Aw) (Ax) (Ay) (Az) 5309 drw 11 , NOTES: 1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. 3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW. 4. For write cycles, ADSP and ADSC have different limitations. 6.42 18 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline 6.42 19 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 119 Ball Grid Array (BGA) Package Diagram Outline 6.42 20 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline 6.42 21 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Ordering Information IDT XXX Device Type S Power X Speed XX Package X Process/ Temperature Rance Commercial (0°C to +70°C) Industrial (-40°C to +85°C) 100-Pin Plastic Thin Quad Flatpack (TQFP) 119 Ball Grid Array (BGA) 165 fine pitch Ball Grid Array (fBGA) Blank I PF BG BQ 75 80 85 Access Time in Tenths of Nanoseconds 71V67703 71V67903 256K x 36 Flow-Through Burst Synchronous SRAM 512K x 18 Flow-Through Burst Synchronous SRAM 5309 drw 12 , 6.42 22 IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Datasheet Document History 12/31/99 04/26/00 Pg. 4 Pg. 7 Pg. 18 05/24/00 Pg. 1,4,8,21 22 Pg. 5,6,7,8 Pg. 20 Pg. 5,6,8 Pg. 7 Pg. 20 Pg. 9 Pg. 1,2 Pg. 7 Pg. 8 Pg. 9 Pg. 1-23 Pg. 4,9,12, 22 Pg. 4 Pg. 7 Created Datasheet from 71V677 and 71V679 Datasheets For 2.5V I/O offering, see 71V67702 AND 71V67902 Datasheets. Add capacitance for BGA package; Insert clarification note to Absolute Max Ratings and Recommended Operating Temperature tables. Replace Pin U6 with TRST pin in BGA pin configuration; Add pin description note in pinout Inserted 100 pin TQFP Package Diagram Outline Add new package offering, 13 x 15 fBGA Correct note 2 on BGA and TQFP pin configuration Correction in the 119 BGA Package Diagram Outline Remove note from TQFP and BQ165 pinouts Add/Remove note from BG119 pinout Update BG 119 pinout Updated ISB2 levels for 7.5-8.5ns. Remove JTAG pins Changed U2-U6 pins to DNU. Changed P5,P7,R5 & R7 to DNU pins. Raised specs by 10mA on 7.5ns, 8ns and 8.5ns. Changed datasheet from Advanced to Final Release. Added I temp to datasheet. Updated 165 fBGA table from TBD to 7. Updated 119BGS pin configurations- reordered I/O signals on P6, P7 (128K x 36) and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18). 07/12/00 12/18/00 10/29/01 10/22/02 04/15/03 12/20/03 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: sramhelp@idt.com 800-544-7726 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 23