IDT72V70840_08

3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 .EATURES: • • • • • • • • • • • • • • • • • IDT72V70840 32 serial input and output streams 4,096 x 4,096 channel non-blocking switching at 8.192 Mb/s Accepts data streams at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s Per-channel Variable Delay Mode for low-latency applications Per-channel Constant Delay Mode for frame integrity applications Automatic identification of ST-BUS® and GCI serial streams Automatic frame offset delay measurement Per-stream frame delay offset programming Per-channel high impedance output control Per-channel processor mode to allow microprocessor writes to TX streams Direct microprocessor access to all internal memories Memory block programming for quick set-up IEEE-1149.1 (JTAG) Test Port Internal Loopback for testing Available in 144-pin Thin Quad Flatpack (TQFP) and 144-pin Ball Grid Array (BGA) packages Operating Temperature Range -40°C to +85°C 3.3V I/O with 5V tolerant inputs and TTL compatible outputs DESCRIPTION: The IDT72V70840 has a non-blocking switch capacity of 1,024 x 1,024 channels at 2.048 Mb/s, 2,048 x 2,048 channels at 4.096 Mb/s, and 4,096 x 4,096 channels at 8.192 Mb/s. With 32 inputs and 32 outputs, programmable per stream control, and a variety of operating modes the IDT72V70840 is designed for the TDM time slot interchange function in either voice or data applications. Some of the main features of the IDT72V70840 are low power 3.3 Volt operation, automatic ST-BUS®/GCI sensing, memory block programming, simple microprocessor interface, one cycle direct internal memory accesses, .UNCTIONAL BLOCK DIAGRAM Vcc GND RESET TMS TDI TDO TCK TRST ODE Test Port RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16 RX17 RX18 RX19 RX20 RX21 RX22 RX23 RX24 RX25 RX26 RX27 RX28 RX29 RX30 RX31 Loopback Output MUX Data Memory Receive Serial Data Streams Transmit Serial Data Streams Internal Registers Connection Memory TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 TX8 TX9 TX10 TX11 TX12 TX13 TX14 TX15 TX16 TX17 TX18 TX19 TX20 TX21 TX22 TX23 TX24 TX25 TX26 TX27 TX28 TX29 TX30 TX31 Timing Unit Microprocessor Interface 5715 drw01 CLK F0i FE/ WFPS HCLK DS CS R/W A0-A13 DTA D0-D15 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp. October 2008 DSC-5715/4 1  2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE PIN CON.IGURATIONS RX16 RX17 RX18 RX19 RX20 RX21 RX22 RX23 GND TX16 TX17 TX12 TX13 GND TX18 TX19 GND ODE RESET GND CLK FOi FE/HCLK WFPS V CC TMS TDI TDO TCK TRST GND DS CS R/W V CC A0 A1 A2 A3 A4 A5 GND A6 A7 A8 A9 A10 A11 A12 A13 GND DTA V CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 TX11 TX10 GND TX9 TX8 V CC RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 GND TX7 TX6 V CC TX5 TX4 GND TX3 TX2 V CC TX1 TX0 GND RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 V CC 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TX22 TX23 GND TX14 TX15 TX20 TX21 V CC RX24 RX25 RX26 RX27 RX28 RX29 RX30 RX31 V CC V CC V CC 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 V CC TX24 TX25 GND TX26 TX27 V CC TX28 TX29 GND TX30 TX31 V CC D0 D1 GND D2 D3 V CC D4 D5 GND D6 D7 V CC D08 D09 GND D10 D11 V CC D12 D13 GND D14 D15 5715 drw 03 NOTE: 1. All I/O pins are 5V tolerant except for TMS, TDI and TRST. TQFP: 0.50mm pitch, 20mm x 20mm (DA144, order code: DA; DAG 144, order code: DAG) TOP VIEW 2 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION SYMBOL GND VCC TX0-31 RX0-31 F0i NAME Ground. VCC TX Output 0 to 31 (Three-state Outputs) RX Input 0 to 31 Frame Pulse I/O DESCRIPTION Ground Rail. +3.3 Volt Power Supply. Serial data output stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s. O I I Serial data input stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s. This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS® and GCI specifications. FE/HCLK Frame Evaluation/ I When LOW, this pin is the frame measurement input. When HIGH, the HCLK (4.096 MHZ clock) is required for frame alignment in the wide frame pulse (WFP) mode. There is no internal pull-up or pull-down. HCLK Clock If this pin is unused, an external pull-up or pull-down must be provided. CLK Clock I Serial clock for shifting data in/out on the serial streams (RX/TX 0-31). This input accepts a 4.096 MHz clock when data streams @ 2.048 Mb/s, a 8.192 MHz clock when data streams @ 4.096 Mb/s, a 16.384 MHz clock when data streams @ 8.192 Mb/s. TMS Test Mode Select I JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-up when not driven. TDI Test Serial Data In I JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up when not driven. TDO Test Serial Data Out O JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when JTAG scan is not enabled. TCK Test Clock I Provides the clock to the JTAG test logic. TRST Test Reset I Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure that the IDT72V70840 is in the normal functional mode. RESET Device Reset I This input (active LOW) puts the IDT72V70840 in its reset state that clears the device internal counters, (Schmitt Trigger Input) registers and brings TX0-31 and microport data outputs to a high-impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held LOW for a minimum of 100ns to reset the device. WFPS Wide Frame Pulse Select I When 1, enables the wide frame pulse (SFP) Frame Alignment interface. When 0, the device operates in ST-BUS® /GCI mode. DS Data Strobe I This active LOW input works in conjunction with CS to enable the read and write operations. R/W Read/Write I This input controls the direction of the data bus lines during a microprocessor access. CS Chip Select I Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70840. A0-13 Address Bus 0 to 13 I These pins allow direct access to Connection Memory, Data Memory and internal control registers. D0-15 Data Bus 0-15 I/O These pins are the data bits of the microprocessor port. DTA Data Transfer O This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin Acknowledgment drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is in high-impedance. ODE Output Drive Enable I This is the output enable control for the TX0-31 serial outputs. When ODE input is LOW and the OSB bit of the CR register is LOW, TX0-31 are in a high-impedance state. If this input is HIGH, the TX0-31 output drivers are enabled. However, each channel may still be put into a high-impedance state by using the per channel control bit in the connection memory. 3 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE DECRIPTION (CONTINUED) JTAG Test Access Port (TAP) and per stream programmable input offset delay, variable or constant throughput modes, internal loopback, output enable, and Processor Mode. The IDT72V70840 is capable of switching up to 4,096 x 4,096 channels without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the device maintains frame integrity in data applications and minimizes throughput delay for voice applications on a per channel basis. The 32 serial input streams (RX) of the IDT72V70840 can be run up to 8.192 Mb/s allowing 128 channels per 125µs frame. The data rates on the output streams (TX) are identical to those on the input stream. With two main operating modes, Processor Mode and Connection Mode, the IDT72V70840 can easily switch data from incoming serial streams (Data Memory) or from the controlling microprocessor (Connection Memory). As control and status information is critical in data transmission, the Processor Mode is especially useful when there are multiple devices sharing the input and output streams. With data coming from multiple sources and through different paths, data entering the device is often delayed. To handle this problem, the IDT72V70840 has a frame evaluation feature to allow individual streams to be offset from the frame pulse in half clock-cycle intervals up to +4.5 clock cycles. The IDT72V70840 also provides a JTAG test access port, an internal loopback feature, memory block programming, a simple microprocessor interface and automatic ST-BUS®/GCI sensing to shorten setup time, aid in debugging and ease use of the device without sacrificing capabilities. SERIAL DATA INTERFACE TIMING The master clock frequency must always be twice the data rate, e.g. for a serial data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz. The input and output stream data rates will always be identical. See control register bits DR1-0 description (Table 5) for data and clock rate selections. The IDT72V70840 provides two different interface timing modes, ST-BUS® or GCI. The IDT72V70840 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS® or GCI. In ST-BUS® format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of CLK, three quarters of the way into the bit cell. In GCI format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell. INPUT FRAME OFFSET SELECTION Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. F0i). Although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. Because data is often delayed this feature is useful in compensating for the skew between clocks. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +4 master clock (CLK) periods forward with a resolution of 1/2 clock period. The output frame offset cannot be offset or adjusted. SERIAL INPUT FRAME ALIGNMENT EVALUATION The IDT72V70840 provides the frame evaluation (FE) input to determine different data input delays with respect to the frame pulse F0i. A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. When the SFE bit in the Control Register is changed from low to high, the evaluation starts. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR register. The SFE bit must be set to zero before a new measurement cycle is started. In ST-BUS® mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the ST-BUS® frame pulse. In GCI mode, the rising edge of FE is evaluated against the rising edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of the frame alignment register. MEMORY BLOCK PROGRAMMING The IDT72V70840 provides users with the capability of initializing the entire connection memory block in two frames. To set bits 12 to 15 of every connection memory location, first program the desired pattern in bits 5 to 8 of the Control Register. The block programming mode is enabled by setting the memory block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the Control Register is set to high, the block programming data will be loaded into the bits 12 to 15 of every connection memory location. The other connection memory bits (bit 0 to bit 11) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero. .UNCTIONAL DESCRIPTION DATA AND CONNECTION MEMORY All data that comes in through the RX inputs go through a serial-to-parallel conversion before being stored into internal Data Memory. The 8 KHz frame pulse (F0i) is used to mark the 125µs frame boundaries and to sequentially address the input channels in Data Memory. Data output on the TX streams may come from either the Serial Input Streams (Data Memory) or from the microprocessor (Connection Memory). In the case that RX input data is to be output, the addresses in connection memory are used to specify a stream and channel of the input. The connection memory is setup in such a way that each location corresponds to an output channel for each particular stream. In that way, more than one channel can output the same data. In Processor Mode, the microprocessor writes data to the connection memory locations corresponding to the stream and channel that is to be output. The lower half (8 least significant bits) of the connection memory is output every frame until the microprocessor changes the data or mode of the channel. By using this Processor Mode capability, the microprocessor can access input and output time-slots on a per channel basis. The four most significant bits of the connection memory are used to control per channel functions of the out put streams. Specifically, there are bits for Processor or Connection mode, Constant or Variable delay, enables or disables of output drivers, and controls for the Loopback function. If the per channel OE is set to zero, only that particular channel (8-bits) will be in the high-impedance state. If however, the ODE input pin is low or the Output Standby Bit (OSB) in the Control Register is low, all of the outputs will be in a high-impedance state even if a particular channel in connection memory has enabled the output for that channel. In other words, the ODE pin and OSB control bit are master output enables for the device (Table 3). 4 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE LOOPBACK CONTROL The loopback control (LPBK) bit of each connection memory location allows the TX output data to be looped backed internally to the RX input for diagnostic purposes. If the LPBK bit is high, the associated TX output channel data is internally looped back to the RX input channel (i.e., data from TXn channel m routes to the RXn channel m internally); if the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero. DELAY THROUGH THE IDT72V70840 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, variable throughput delay is best as it ensure minimum delay between input and output data. In wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. The delay through the device varies according to the type of throughput delay selected in the V/C bit of the connection memory. VARIABLE DELAY MODE (V/C BIT = 0) In this mode, the delay is dependent only on the combination of source and destination channels and is independent of input and output streams. The minimum delay achievable in the IDT72V70840 is three time-slots. If the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). The same is true if the input channel n is switched to output channel n+1 or n+2. If the input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. Table 2 shows the possible delays for the IDT72V70840 in the variable delay mode. CONSTANT DELAY MODE (V/C BIT = 1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the IDT72V70840, the minimum throughput delay achievable in the constant delay mode will be one frame. For example, when input time-slot 31 is switched to output time-slot 0. The maximum delay of 94 time-slots of delay occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. MEMORY MAPPING The address bus on the microprocessor interface selects the internal registers and memories of the IDT72V70840. The two most significant bits of the address select between the registers, Data Memory, and Connection Memory. If A13 and A12 are HIGH, A11-A0 are used to address the Data Memory. If A13 is HIGH and A12 is LOW, A11-A0 are used to address Connection Memory. If A13 is LOW and A12 is HIGH A11-A0 are used to select the Control Register, Frame Alignment Register, and Frame Offset Registers. See Table 4 for mappings. As explained in the Serial Data Interface Timing and Switching Configurations sections, after system power-up, the Control Register should be programmed immediately to establish the desired switching configuration. The data in the Control Register consists of the Memory Block Programming bit (MBP), the Block Programming Data (BPE) bits, the Begin Block Programming Enable (BPE), the Output Stand By, Start Frame Evaluation, and Data Rate Select bits. As explained in the Memory Block Programming section, the BPE begins the programming if the MBP bit is enabled. This allows the entire connection memory block to be programmed with the Block Programming Data bits. If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all TX output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all TX output drivers are enabled. CONNECTION MEMORY CONTROL If the ODE pin or the OSB bit is high, the OE bit of each connection memory location controls the output drivers-enables (if high) or disables (if low). See Table 3 for detail. The Processor Channel (PC) bit of the Connection Memory selects between Processor Mode and Connection Mode. If high, the contents of the Connection Memory are output on the TX streams. If low, the Stream Address Bit (SAB) and the Channel Address Bit (CAB) of the Connection Memory defines the source information (stream and channel) of the time-slot that will be switched to the output from Data Memory. Also in the Connection Memory is the V/C (Variable/Constant Delay) bit. Each Connection Memory location allows the per-channel selection between variable and constant throughput delay modes. If the LPBK bit is high, the associated TX output channel data is internally looped back to the RX input channel (i.e., RXn channel m data comes from the TXn channel m). If the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of the frame delay offset registers must be set to zero. MICROPROCESSOR INTER.ACE The IDT72V70840’s microprocessor interface looks like a standard RAM interface to improve integration into a system. With a 12-bit address bus and a 16-bit data bus, read and writes are mapped directly into Data and Connection memories and require only one cycle to access. By allowing the internal memories to be randomly accessed in one cycle, the controlling microprocessor has more time to manage other peripheral devices and can more easily and quickly gather information and setup the switch paths. Table 4 shows the mapping of the addresses into internal memory blocks and Table 5 shows the Control Register information. INITIALIZATION O. THE IDT72V70840 After power up, the state of the connection memory is unknown. As such, the outputs should be put in high impedance by holding the ODE low. While the ODE is low, the microprocessor can initialize the device, program the active paths, and disable unused outputs by programming the OE bit in connection memory. Once the device is configured, the ODE pin (or OSB bit depending on initialization) can be switched. 5 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 1 — CONSTANT THROUGHPUT DELAY VALUE Input Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Delay for Constant Throughput Delay Mode (m – output channel number) (n – input channel number) 32 + (32 – n) +m time-slots 64 + (64 – n) +m time-slots 128 + (128 – n) +m time-slots TABLE 2 — VARIABLE THROUGHPUT DELAY VALUE Input Rate m n+2 (m-n) time-slots (m-n) time-slots (m-n) time-slots TABLE 3 — OUTPUT HIGH IMPEDANCE CONTROL OE bit in Connection Memory 0 1 1 1 1 ODE pin Don’t Care 0 0 1 1 OSB bit in CR Register Don’t Care 0 1 0 1 TX Stream Output Status Per Channel High-Impedance High-Impedance Enable Enable Enable TABLE 4 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING A13 1 1 0 0 0 0 0 0 0 0 0 0 A12 1 0 1 1 1 1 1 1 1 1 1 1 A11 STA4 STA4 0 0 0 0 0 0 0 0 1 1 A10 STA3 STA3 0 0 0 0 1 1 1 1 0 0 A9 STA2 STA2 0 0 1 1 0 0 1 1 0 0 A8 STA1 STA1 0 1 0 1 0 1 0 1 0 1 A7 STA0 STA0 x x x x x x x x x x A6 CH6 CH6 x x x x x x x x x x A5 CH5 CH5 x x x x x x x x x x 6 A4 CH4 CH4 x x x x x x x x x x A3 CH3 CH3 x x x x x x x x x x A2 CH2 CH2 x x x x x x x x x x A1 CH1 CH1 x x x x x x x x x x A0 CH0 CH0 x x x x x x x x x x R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Location Data Memory Connect. Memory Control Register Frame Align Register FOR0 FOR1 FOR2 FOR3 FOR4 FOR5 FOR6 FOR7 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 5 — CONTROL REGISTER (CR) BITS Reset Value: 15 0 14 0 13 0 0000H. 12 0 11 0 10 0 9 MBP 8 BPD3 7 BPD2 6 BPD1 5 BPD0 4 BPE 3 OSB 2 SFE 1 DR1 0 DR0 Bit 15-10 9 8-5 Name Unused MBP (Memory Block Program) BPD3-0 (Block Programming Data) BPE (Begin Block Programming Enable) Description Must be zero for normal operation. When 1, the connection memory block programming feature is ready for the programming of Connection Memory high bits, bit 11 to bit 15. When 0, this feature is disabled. These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD3-0 are loaded into bit 15 and 12 of the connection memory. Bit 11 to bit 0 of the connection memory are set to 0. A zero to one transition of this bit enables the memory block programming function. The BPE and BPD4-0 bits in the CR register have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort to ensure proper operation. When BPE = 1, the other bit in the CR register must not be changed for two frames to ensure proper operation. When ODE = 0 and OSB = 0, the output drivers of TX0 to TX31 are in high impedance mode. When ODE = 0 and OSB = 1, the output driver of TX0 to TX31 function normally. When ODE = 1, TX0 to TX31 output drivers function normally. A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from zero to one, the evaluation procedure stops. To start another fame evaluation cycle, set this bit to zero for at least one frame. DR1 0 0 1 1 DR0 0 1 0 1 Data Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Reserved Master Clock 4.096 MHz 8.192 MHz 16.384 MHz Reserved 4 3 2 1-0 OSB (Output Stand By) SFE (Start Frame Evaluation) DR1-0 (Data Rate Select) TABLE 6 — CONNECTION MEMORY BITS 15 LPBK Bit 15 14 13 14 V/C Name LPBK (Per Channel Loopback) V/C (Variable/Constant Throughput Delay) PC (Processor Channel) OE (Output Enable) SAB4-0 (Source Stream Address Bits) CAB6-0 (Source Channel Address Bits) 13 PC 12 OE 11 SAB4 10 SAB3 9 SAB2 8 SAB1 7 SAB0 6 CAB6 5 CAB5 4 CAB4 3 CAB3 2 CAB2 1 CAB1 0 CAB0 Description When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode. This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a per-channel basis. When 1, the contents of the connection memory are output on the corresponding output channel and stream. Only the lower byte (bit 7 – bit 0) will be output to the TX output pins. When 0, the contents of the connection memory are the data memory address of the switched input channel and stream. This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions normally. When 0, the output driver is in a high-impedance state. The binary value is the number of the data stream for the source of the connection. The binary value is the number of the channel for the source of the connection. 12 11-7 6-0 7 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 7 — .RAME ALIGNMENT REGISTER (.AR) BITS Reset Value: 15 0 14 0 13 0 0000H. 12 CFE 11 FD11 10 FD10 9 FD9 8 FD8 7 FD7 6 FD6 5 FD5 4 FD4 3 FD3 2 FD2 1 FD1 0 FD0 Bit 15-13 12 11 10-0 Name Unused CFE (Complete Frame Evaluation) Description Must be zero for normal operation When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when SFE bit in the CR register is changed from 1 to 0. FD11 The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase (Frame Delay Bit 11) (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle. FD10-0 (Frame Delay Bits) The binary value expressed in these bits refers to the measured input offset value. These bits are rest to zero when the SFE bit of the CR register changes from 1 to 0. (FD10 – MSB, FD0 – LSB) ST-BUS Frame CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FE Input (FD[10:0] = 06H) (FD11 = 0, sample at CLK LOW phase) GCI Frame CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FE Input (FD[10:0] = 09H) (FD11 = 1, sample at CLK HIGH phase) Figure 1. Example for Frame Alignment Measurement 8 5715 drw 04 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 8 — .RAME INPUT O..SET REGISTER (.OR) BITS Reset Value: 0000H for all FOR registers. 15 OF32 14 OF31 13 OF30 12 DLE3 11 OF22 10 OF21 9 OF20 8 DLE2 7 OF12 6 OF11 5 OF10 4 DLE1 3 OF02 2 OF01 1 OF00 0 DLE0 FOR0 Register 15 OF72 14 OF71 13 OF70 12 DLE7 11 OF62 10 OF61 9 OF60 8 DLE6 7 OF52 6 OF51 5 OF50 4 DLE5 3 OF42 2 OF41 1 OF40 0 DLE4 FOR1 Register 15 OF112 14 OF111 13 OF110 12 DLE11 11 OF102 10 OF101 9 OF100 8 DLE10 7 OF92 6 OF91 5 OF90 4 DLE9 3 OF82 2 OF81 1 OF80 0 DLE8 FOR2 Register 15 OF312 14 OF311 13 OF310 12 DLE31 11 OF142 10 OF141 9 OF140 8 DLE14 7 OF132 6 OF131 5 OF130 4 DLE13 3 OF122 2 OF121 1 OF120 0 DLE12 FOR3 Register 15 OF192 14 OF191 13 OF190 12 DLE19 11 OF182 10 OF181 9 OF180 8 DLE18 7 OF172 6 OF171 5 OF170 4 DLE17 3 OD162 2 OD161 1 OF160 0 DLE16 FOR4 Register 15 OF232 14 OF231 13 OF230 12 DLE23 11 OF222 10 OF221 9 OF220 8 DLE22 7 OF212 6 OF211 5 OF210 4 DLE21 3 OF202 2 OF201 1 OF200 0 DLE20 FOR5 Register 15 OF272 14 OF271 13 OF270 12 DLE27 11 OF262 10 OF261 9 OF260 8 DLE26 7 OF252 6 OF251 5 OF250 4 DLE25 3 OF242 2 OF241 1 OF240 0 DLE24 FOR6 Register 15 OF312 14 OF311 13 OF310 12 DLE31 11 OF302 10 OF301 9 OF300 8 DLE30 7 OF292 6 OF291 5 OF290 4 DLE29 3 OF282 2 OF281 1 OF280 0 DLE28 FOR7 Register Name(1) OFn2, OFn1, OFn0 (Offset Bits 2, 1 & 0) DLEn Description These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse input signal is applied to the F0i input of the device. See Figure 1. ST-BUS® mode: (Data Latch Edge) GCI mode: NOTE: 1. n denotes an input stream number from 0 to 31. DLEn = 0, if clock rising edge is at the ¾ point of the bit cell. DLEn = 1, if when clock falling edge is at the ¾ of the bit cell. DLEn = 0, if clock falling edge is at the ¾ point of the bit cell. DLEn = 1, if when clock rising edge is at the ¾ of the bit cell. 9 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 9 — O..SET BITS (O.n2, O.n1, O.n0, DLEn) & .RAME DELAY BITS (.D11, .D2-0) Measurement Result from Input Stream Offset FD11 No clock period shift (Default) + 0.5 clock period shift + 1.0 clock period shift + 1.5 clock period shift + 2.0 clock period shift + 2.5 clock period shift + 3.0 clock period shift + 3.5 clock period shift + 4.0 clock period shift + 4.5 clock period shift 1 0 1 0 1 0 1 0 1 0 FD2 0 0 0 0 0 0 0 0 1 1 FD1 0 0 0 0 1 1 1 1 0 0 FD0 0 0 1 1 0 0 1 1 0 0 OFn2 0 0 0 0 0 0 0 0 1 1 OFn1 0 0 0 0 1 1 1 1 0 0 OFn0 0 0 1 1 0 0 1 1 0 0 DLEn 0 1 0 1 0 1 0 1 0 1 Frame Delay Bits Corresponding Offset Bits ST-BUS F0i CLK RX Stream Bit 7 offset = 0, DLE = 0 RX Stream Bit 7 offset = 1, DLE = 0 RX Stream Bit 7 offset = 0, DLE = 1 RX Stream Bit 7 offset = 1, DLE = 1 denotes the 3/4 point of the bit cell GCI F0i CLK RX Stream Bit 0 offset = 0, DLE = 0 RX Stream Bit 0 offset = 1, DLE = 0 RX Stream Bit 0 offset = 0, DLE = 1 RX Stream Bit 0 offset = 1, DLE = 1 denotes the 3/4 point of the bit cell 5715 drw 05 Figure 2. Examples for Input Offset Delay Timing 10 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE JTAG SUPPORT The IDT72V70840 JTAG interface conforms to the Boundary-Scan standard IEEE-1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. TEST ACCESS PORT (TAP) The Test Access Port (TAP) provides access to the test functions of the IDT72V70840. It consists of three input pins and one output pin. •Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. •Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VCC when it is not driven from an external source. •Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VCC when it is not driven from an external source. •Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state. •Test Reset (TRST) Reset the JTAG scan structure. This pin is internally pulled to VCC. INSTRUCTION REGISTER In accordance with the IEEE-1149.1 standard, the IDT72V70840 uses public instructions. The IDT72V70840 JTAG Interface contains a two-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. See Table below for Instruction decoding. Value 11 10 01 00 Instruction Bypass Sample/Preload Sample/Preload EXTEST Function Select Bypass Register Select Boundary Scan Register Select Boundary Scan Register Select Boundary Scan Register JTAG Instruction Register Decoding TEST DATA REGISTER As specified in IEEE-1149.1, the IDT72V70840 JTAG Interface contains two test data registers: •The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the IDT72V70840 core logic. •The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO. The IDT72V70840 boundary scan register bits are shown in Table 10. Bit 0 is the first bit clocked out. All three-state enable bits are active high. 11 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 10 — BOUNDARY SCAN REGISTER BITS Device Pin ODE RESET CLK F0i FE/HCLK WFPS DS CS R/W A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 DTA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TX31 TX30 TX29 TX28 TX27 TX26 TX25 TX24 RX31 RX30 RX29 RX28 Boundary Scan Bit 0 to bit 167 Three-State Output Input Control Scan Cell Scan Cell 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 12 Device Pin RX27 RX26 RX25 RX24 TX23 TX22 TX21 TX20 TX19 TX18 TX17 TX16 RX23 RX22 RX21 RX20 RX19 RX18 RX17 RX16 TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 Boundary Scan Bit 0 to bit 167 Three-State Output Input Control Scan Cell Scan Cell 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE APPLICATIONS CREATING LARGE SWITCH MATRICES To create a switch matrix with twice the capacity of a given TSIS device, four devices must be used. In the example below, four IDT72V70840, 4096 x 4096 channel capacity devices are used to create an 8192 x 8192 channel switch matrix. As can be seen, Device #1 and Device #2 will receive the same incoming RX0-31 data and thus have the same contents in Data Memory. On the output side, however Device #1 is used to switch data out on to TX0-31 where as Device #2 is used to switch out on TX32-63. Like wise Device #3 and Device #4 are used in the same way as Device #1 and Device #2 but switch RX32-63, to TX0-31 and TX32-63. With this configuration all possible combinations of input and output streams are possible. In short, Device #1 is used to switch RX0-31 to TX0-31, Device #2 to switch RX0-31 to TX32-63, Device #3 to switch RX3263 to TX0-31, and Device #4 to switch RX32-63 to TX32-63. RX0-31 Device 1 IDT72V70840 TX0-31 Device 2 IDT72V70840 TX32-63 RX32-63 Device 3 IDT72V70840 Device 4 IDT72V70840 5715 drw06 Figure 3. Creating Larger Switch Matrices 13 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC Vi IO TS PD Parameter Supply Voltage Voltage on Digital Inputs Current at Digital Outputs Storage Temperature Package Power Dissapation Min. 3.0 GND -0.3 -50 -55  Max. 3.6 5.3 50 +125 2 Unit V V mA °C W RECOMMENDED OPERATING CONDITIONS(1) Symbol VCC VIH VIL TOP Parameter Positive Supply Input HIGH Voltage Input LOW Voltage Operating Temperature Commercial Min. 3.0 2.0  -40 Typ. 3.3   25 Max. 3.6 5.3 0.8 +85 Unit V V V °C NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. NOTE: 1.Voltages are with respect to Ground unless otherwise stated. DC ELECTRICAL CHARACTERISTICS Symbol ICC (2) Parameter Supply Current @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s Min. 2.4 Typ. 15 25 47 Max. 20 35 70 50 50 0.4 Units mA mA mA µA µA V V IIL(3,4) IOZ(3,4) VOH(5) VOL(6) Input Leakage (input pins) High-impedance Leakage Output HIGH Voltage Output LOW Voltage NOTES: 1. Voltages are with respect to ground (GND) unless otherwise stated. 2. Outputs unloaded. 3. 0 ≤ V ≤ VCC. 4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V). 5. IOH = 10 mA. 6. IOL = 10 mA. AC ELECTRICAL CHARACTERISTICS - TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS Symbol V TT VHM VLM Rating TTL Threshold TTL Rise/Fall Threshold Voltage HIGH TTL Rise/Fall Threshold Voltage LOW Level 1.5 2.0 0.8 Unit V V V Test Point VCC Output Pin S1 CL GND RL S2 GND S1 is open circuit except when testing output levels or high impedance states. S2 is switched to VCC or GND when testing output levels or high impedance states. 5715 drw07 Figure 4. Output Load 14 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - .RAME PULSE AND CLK Symbol tFPW(1) Parameter Frame Pulse Width (ST-BUS®, GCI) Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s Frame Pulse Setup time before CLK falling (ST-BUS® or GCI) Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI) CLK Period Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s CLK Pulse Width HIGH Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s CLK Pulse Width LOW Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s Clock Rise/Fall Time Wide Frame Pulse Width Bit rate = 8.192 Mb/s Frame Pulse Setup Time before HCLK falling Frame Pulse Hold Time from HCLK falling HCLK (4.096 MHz) Period Bit rate = 8.192 Mb/s HCLK (4.096 MHz) Pulse Width HIGH Bit rate = 8.192 Mb/s HCLK (4.096 MHz) Pulse Width LOW Bit rate = 8.192 Mb/s HCLK Rise/Fall Time Delay between falling edge of HCLK and falling edge of CLK Min. 26 26 26 5 10 190 110 58 85 50 20 85 50 20  195 5 10 190 85 85  -10 Typ.                        Max. 295 145 80   300 150 70 150 75 40 150 75 40 10 295 150 150 300 150 150 10 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tFPS(1) t FPH(1) tCP(1) tCH(1) tCL(1) tr, tf t HFPW(2) tHFPS(2) tHFPH(2) t HCP(2) tHCH(2) tHCL(2) tHr, tHf tDIF(3) NOTES: 1. WFPS Pin = 0. 2. WFPS Pin = 1 3. WFPS Pin = 0 or 1. 15 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS(1)  SERIAL STREAM (ST-BUS® and GCI) Symbol tSIS tSIH tSOD Parameter RX Setup Time RX Hold Time TX Delay – Active to Active @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s TX Delay – Active to High-Z @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s TX Delay – High-Z to Active @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s Output Driver Enable (ODE) Delay @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s Min. 5 10             Typ.               Max.   30 30 30 30 30 30 30 30 30 30 30 30 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns tDZ tZD tODE NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL (1K), with timing corrected to cancel time taken to discharge CL (150 pF). tFPW F0i tFPS CLK tSOD TX Bit 0, Last Ch(1) Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 tFPH tCP tCH tCL tr tf tSIS RX Bit 0, Last Ch (1) tSIH Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 5715 drw08 NOTE : 1. @ 2.048 Mb/s mode, last channel = ch 31, @ 4.096 Mb/s mode, last channel = ch 63, @ 8.192 Mb/s mode, last channel = ch 127. Figure 5. ST-BUS® Timing 16 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE tFPW F0i tFPS CLK tSOD TX Bit 7, Last Ch(1) Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 tFPH tCP tCH tCL tr tf tSIS RX NOTE : 1. @ 2.048 Mb/s mode, last channel = ch 31, @ 4.096 Mb/s mode, last channel = ch 63, @ 8.192 Mb/s mode, last channel = ch 127. Bit 7, Last Ch (1) tSIH Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 5715 drw09 Figure 6. GCI Timing tHFPW tHFPS F0i tHFPH tHCP tHCL HCLK 4.096 MHz tHCH tDIF CLK 16.384 MHz tHr tHf tCP tCH tCL tr tf tSOD TX Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0 Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0 tSIS RX Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0 tSIH Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0 5715 drw10 Figure 7. WFP Bus Timing (@ 8.192 Mb/s, when pin WFPS is HIGH) CLK (ST-BUS mode) CLK (GCI mode) tDZ ODE TX VALID DATA HiZ tODE tODE HIZ 5715 drw12 tZD TX HiZ VALID DATA 5715 drw 10 TX HIZ VALID DATA Figure 8. Serial Output and External Control 17 Figure 9. Output Driver Enable (ODE) IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - MICROPROCESSOR INTER.ACE TIMING Symbol tCSS tRWS tADS tCSH tRWH tADH tDDR(1) tDHR(1,2,3) tDSW tSWD tDHW tAKD (1) Parameter CS Setup from DS falling R/W Setup from DS falling Address Setup from DS falling CS Hold after DS rising R/W Hold after DS Rising Address Hold after DS Rising Data Setup from DTA LOW on Read Data Hold on Read Data Setup on Write (Fast Write) Valid Data Delay on Write (Slow Write) Data Hold on Write Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory Min. 0 3 2 0 3 2 2 10 10 5 Typ.        15    Max.        25  0  30 345 200 120  2   20  Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s tAKH (1,2,3) Acknowledgment Hold Time Data Strobe Setup Time tDSS (4) NOTES : 1. CL= 150pF 2. RL = 1K 3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 4. To achieve one clock cycle fast memory access, this setup time, tDSS should be met. Otherwise, worst case memory access operation is determined by tAKD. 18 IDT72V70840 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE CLK GCI CLK ST-BUS tDSS DS tCSH tCSS CS tRWS R/W tRWH tADS A0-A11 VALID ADDRESS tADH tDHR D0-D15 READ VALID READ DATA tSWD D0-D15 WRITE tDSW tDHW VALID WRITE DATA tDDR DTA tAKD tAKH 5715 drw13 Figure 10. Motorola Non-Mulitplexed Bus Timing 19 ORDERING IN.ORMATION IDT XXXXXX Device Type XX Package X Process/ Temperature Range BLANK Commercial (-40°C to +85°C) DA DAG Thin Quad Flatpacks (TQFP, DA144) Green Thin Quad Flatpacks (TQFP, DAG144) 72V70840 4,096 x 4,0963.3V Time Slot Interchange Digital Switch 5715 drw14 DATASHEET DOCUMENT HISTORY 5/05/2000 6/08/2000 8/30/2000 01/24/2001 10/22/2001 1/04/2002 12/14/2006 10/06/2008 pg. 1 pgs. 1, 2, 3 and 19. pgs. 2, 4, 6, 9, 11, 13, 14, 16, 17 and 19. pg. 14 pg. 1. pgs. 1 and 15. pgs. 2 and 20. pg. 3. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 20 for Tech Support: 408-330-1753 email: TELECOMhelp@idt.com