IDT74FCT162373AT

IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE FAST CMOS 16-BIT TRANSPARENT LATCH FEATURES: • • • • • • • • 0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage ≤1µA (max.) VCC = 5V ±10% Balanced Output Drivers: ±24mA Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25°C • Available in SSOP and TSSOP packages IDT74FCT162373AT/CT/ET DESCRIPTION: The FCT162373T 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. It can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 8-bit latches, or one 16-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT162373T has balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors. The FCT162373T is a plug-in replacement for the FCT16373T and ABT16373 for on-board interface applications. FUNCTIONAL BLOCK DIAGRAM 1 OE 2 OE 1 LE 1D 1 2 LE D 1O 1 2D 1 D 2O 1 C C TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 © 2006 Integrated Device Technology, Inc. JUNE 2006 DSC-5455/5 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION 1OE 1O1 1O2 ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max –0.5 to +7 –0.5 to VCC+0.5 –65 to +150 –60 to +120 Unit V V °C mA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VTERM(2) 1LE 1D 1 1D 2 VTERM(3) TSTG IOUT GND 1O3 1O4 GND 1D 3 1D 4 VCC 1O5 1O6 VCC 1D 5 1D 6 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals terminals for FCT162XXX. CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF GND 1O7 1O8 2O1 2O2 GND 1D 7 1D 8 2D 1 2D 2 NOTE: 1. This parameter is measured at characterization but not tested. PIN DESCRIPTION Pin Names xDx Data Inputs Latch Enable Input (Active HIGH) Outputs Enable Input (Active LOW) 3-State Outputs xLE x OE xOx Description GND 2O3 2O4 GND 2D 3 2D 4 VCC 2O5 2O6 VCC 2D 5 2D 6 FUNCTION TABLE(1) Inputs xDx H L X NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance Outputs xOE L L H GND 2O7 2O8 2OE GND 2D 7 2D 8 2LE xLE H H X xOx H L Z SSOP/ TSSOP TOP VIEW 2 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10% Symbol VIH VIL IIH Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) IIL Input LOW Current (Input pins)(5) Input LOW Current (I/O pins)(5) IOZH IOZL VIK IOS VH ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins)(5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Min., IIN = –18mA VCC = Max., VO = GND(3) — VCC = Max. VO = 2.7V VO = 0.5V VCC = Max. VI = GND Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2 — — — — — — — — –80 — — Typ.(2) — — — — — — — — –0.7 –140 100 5 Max. — 0.8 ±1 ±1 ±1 ±1 ±1 ±1 –1.2 –250 — 500 V mA mV µA µA µA Unit V V µA OUTPUT DRIVE CHARACTERISTICS Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) VCC = Min VIN = VIH or VIL VCC = Min VIN = VIH or VIL IOH = –24mA IOL = 24mA Min. 60 –60 2.4 — Typ.(2) 115 –115 3.3 0.3 Max. 200 –200 — 0.55 Unit mA mA V V NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is ±5µA at TA = –55°C. 3 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol ΔICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open xOE = GND One Input Togging 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle xOE = GND xLE = VCC One Bit Togging VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle xOE = GND xLE = VCC Sixteen Bits Togging VIN = VCC VIN = GND Test Conditions(1) Min. — — Typ.(2) 0.5 60 Max. 1.5 100 Unit mA µA/ MHz IC Total Power Supply Current(6) VIN = VCC VIN = GND VIN = 3.4V VIN = GND — 0.6 1.5 mA — 0.9 2.3 VIN = VCC VIN = GND — 2.4 4.5(5) VIN = 3.4V VIN = GND — 6.4 16.5(5) NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 4 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tPLH tPHL tPLH tPHL tPZL tPZH tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay xDx to xOx Propagation Delay xLE to xOx Output Enable Time Output Disable Time Set-up Time HIGH or LOW, xDx to xLE Hold Time HIGH or LOW, xDx to xLE xLE Pulse Width HIGH Output Skew(3) Condition(1) CL = 50pF RL = 500Ω 74FCT162373AT Min.(2) Max. 1.5 5.2 2 1.5 1.5 2 1.5 5 — 8.5 6.5 5.5 — — — 0.5 74FCT162373CT Min.(2) Max. 1.5 4.2 2 1.5 1.5 2 1.5 5 — 5.5 5.5 5 — — — 0.5 74FCT162373ET Min.(2) Max. 1.5 3.4 1.5 1.5 1.5 1 1 3(4) — 3.7 4.4 3.6 — — — 0.5 Unit ns ns ns ns ns ns ns ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested. 5 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC 500Ω VIN Pulse Generator RT D.U.T. 50pF CL 500Ω V OUT 7.0V SWITCH POSITION Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test Circuits for All Outputs DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU tH tREM 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE 1.5V 1.5V tSU tH Pulse Width Set-up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ DISABLE 3V 1.5V 0V 3.5V 0.3V VOL Propagation Delay Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 6 IDT74FCT162373AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX FCT Temp. Range XXX Family XXXX Device Type XX Package PV PVG PA PAG Shrink Small Outline Package SSOP - Green Thin Shrink Small Outline Package TSSOP - Green 373AT 16-Bit Transparent Latch 373CT 373ET 162 Double-Density, 5 Volt, Balanced Drive 74 – 40°C to +85°C CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 7 for Tech Support: logichelp@idt.com