MPC92439FA

900MHz, Low Voltage, LVPECL Clock Syntheesizer The MPC92439 is a 3.3 V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 3.125 MHz to 900 MHz and the support of differential LVPECL output signals the device meets the needs of the most demanding clock applications. Features • • • • • • • • • • • • • • • 3.125 MHz to 900 MHz synthesized clock output signal Differential LVPECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference input 3.3V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 28-PLCC and 32-LQFP packaging 28-Lead and 32-lead Pb-free packages available SiGe Technology Ambient temperature range 0°C to + 70°C Pin and function compatible to the MC12439 and MPC9239 MPC92439 DATA SHEET 900MHZ LOW VOLTAGE CLOCK SYNTHESIZER FN SUFFIX(1) 28-LEAD PLCC PACKAGE CASE 776-02 EI SUFFIX(2) 28-LEAD PLCC PACKAGE CASE 776-02 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 400 to 900 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The AC SUFFIX(2) crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N de32-LEAD LQFP PACKAGE termine the output frequency. CASE 873A-03 The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for K SUFFIX some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL 32-LEAD VFQFN PACKAGE will be stable if the VCO frequency is within the specified VCO frequency range (400 to 900 Pb-FREE PACKAGE MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, Notes: and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance (1) FN, FA suffix: leaded terminations of the part while providing a 50% duty cycle. The output driver is driven differentially from (2) EI, AC suffix: lead-free, RoHS-compliant, EPP the output divider, and is capable of driving a pair of transmission lines terminated 50Ω to VCC – 2.0V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. ORDERING INFORMATION The configuration logic has two sections: serial and parallel. The parallel interface uses Device Package the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the MPC92439EI PLCC-28 (Pb-Free) LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface MPC92439FA LQFP-32 has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and MPC92439AC LQFP-32 (Pb-Free) N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the MPC92439KLF VFQFN-32 (Pb-Free) S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAMMING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments. FA SUFFIX(1) 32-LEAD LQFP PACKAGE CASE 873A-03 PROPOSED MPC92439 REVISION 4 OCTOBER 27, 2009 1 P R ©2009 Integrated Device Technology, Inc. O P O S E D MPC92439 Data Sheet 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER XTAL_IN XTAL_OUT FREF_EXT XTAL 10 – 20 MHz 1 Ref 0 VCO PLL 400 – 900 MHz FB ÷0 TO ÷127 7-BIT M-DIVIDER ÷1 ÷2 ÷4 ÷8 11 00 01 10 ÷16 1 OE 0 FOUT FOUT VCC XTAL_SEL VCC P_LOAD S_LOAD LE P/S TEST 2 N-LATCH 3 T-LATCH TEST 7 M-LATCH 0 S_DATA S_CLOCK BITS 11-5 VCC 1 BITS 3-4 0 1 BITS 0-2 12-BIT SHIFT REGISTER M[0:6] N[1:0] PWR_DOWN OE Figure 1. MPC92439 Logic Diagram XTAL_SEL FOUT FOUT TEST GND GND VCC VCC M[6] M[5] 18 S_CLOCK S_DATA S_LOAD VCC_PLL PWR_DOWN FREF_EXT XTAL_IN 26 27 28 1 2 3 4 25 24 23 22 21 20 19 18 17 16 N[1] N[0] NC XTAL_SEL M[6] M[5] M[4] GND TEST VCC VCC GND FOUT FOUT VCC 25 26 27 28 29 30 31 32 24 23 22 21 20 19 M[4] 17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 13 12 11 10 9 8 XTAL_IN NC MPC92439 15 14 13 12 MPC92439 5 XTAL_OUT 6 OE 7 P_LOAD 8 M[0] 9 M[1] 10 M[2] 11 M[3] 1 2 3 NC 4 N1 N0 5 6 7 Figure 2. MPC92439 28-Lead PLCC Pinout (Top View) Figure 3. MPC92439 32-Lead Package Pinout (Top View) 2 ©2009 Integrated Device Technology, Inc. MPC92439 REVISION 4 OCTOBER 27, 2009 POWER_DOWN FREF_EXT VCC_PLL S_CLOCK S_LOAD S_DATA VCC_PLL MPC92439 Data Sheet 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER XTAL_SEL M[6] M[5] 24 23 22 21 20 19 18 17 GND TEST VCC VCC GND FOUT FOUT VCC 25 26 27 28 29 30 31 32 1 S_CLOCK E S O P MPC92439 D 16 15 14 13 12 11 10 9 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 8 XTAL_IN P 2 S_DATA R 3 S_LOAD O 4 VCC_PLL 5 VCC_PLL 6 POWER_DOWN 7 FREF_EXT Figure 4. 32-Lead VFQFN Package Pinout (Top View) MPC92439 REVISION 4 OCTOBER 27, 2009 M[4] NC NC N1 N0 3 ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet Table 1. Pin Configurations Pin XTAL_IN, XTAL_OUT FREF_EXT FOUT, FOUT TEST XTAL_SEL PWR_DOWN Input Output Output Input Input 1 0 I/O Default 6 0 Type Analog Crystal oscillator interface 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER Function LVCMOS Alternative PLL reference input LVPECL Differential clock output LVCMOS Test and device diagnosis output LVCMOS PLL reference select input LVCMOS Configuration input for power down mode. Assertion (deassertion) of power down will decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps. PWR_DOWN assertion (deassertion) is synchronous to the input reference clock. LVCMOS Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. LVCMOS Parallel configuration control input. this input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the lowto-high transition of P_LOAD. P_LOAD is state sensitive. LVCMOS Serial configuration data input. LVCMOS Serial configuration clock input. LVCMOS Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. LVCMOS Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD. LVCMOS Output enable (active high) The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state (FOUT = L, FOUT = H). Ground VCC VCC Negative power supply (GND). Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. PLL positive power supply (analog power supply). Do not connect S_LOAD Input 0 P_LOAD Input 1 S_DATA S_CLOCK M[0:6] N[1:0] OE Input Input Input Input Input 0 0 1 1 1 GND VCC VCC_PLL NC Supply Supply Supply Table 2. Output Frequency Range and PLL Post-Divider N PWR_DOWN 0 0 0 0 1 1 1 1 N 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 VCO Output Frequency Division 2 4 8 1 32 64 128 16 FOUT Frequency Range 200 - 450 MHz 100 -225 MHz 50-112.5 MHz 400-900 MHz 12.5-28.125 MHz 6.25-14.0625 MHz 3.125-7.03125 MHz 25-56.25 MHz MPC92439 REVISION 4 OCTOBER 27, 2009 4 ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet Table 3. Function Table Input XTAL_SEL OE PWR_DOWN 0 FREF_EXT Outputs disabled, FOUT is stopped in the logic low state (FOUT = L, FOUT = H) Output divider ÷ 1 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER 1 XTAL interface Outputs enabled Output divider ÷ 16 Table 4. General Specifications Symbol VTT MM HBM LU CIN θJA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Input Capacitance LQFP 32 Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 200 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 2.5 43.0 1 37.6 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 0 33.7 26.3 Min Typ VCC – 2 Max Unit V V V mA pF °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min meters per second °C/W °C/W MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multi-layer test board Thermal Resistance Junction to Ambient 32 VFQFN PROPOSED θJC LQFP 32 Thermal Resistance Junction to Case Table 5. Absolute Maximum Ratings(1) Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature –65 Characteristics Min –0.3 –0.3 –0.3 Max 4.6 VCC + 0.3 VCC + 0.3 ±20 ±50 125 Unit V V V mA mA °C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. MPC92439 REVISION 4 OCTOBER 27, 2009 5 ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet Table 6. DC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to +70°C) Symbol VIH VIL IIN Characteristics Input High Voltage Input Low Voltage Input Current(1) (2) 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER Min 2.0 Typ Max VCC + 0.3 0.8 ±200 Unit V V µA Condition LVCMOS LVCMOS VIN = VCC or GND LVCMOS Control Inputs (FREF_EXT, POWER_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE) Differential Clock Output FOUT VOH VOL VOH VOL ICC_PLL ICC Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage VCC–1.02 VCC–1.95 2.0 VCC–0.74 VCC–1.60 V V LVPECL LVPECL Test and Diagnosis Output TEST V 0.55 V IOH = –0.8 mA IOL = 0.8 mA VCC_PLL Pins All VCC Pins Supply Current Maximum PLL Supply Current Maximum Supply Current 62 20 110 mA mA 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50Ω to VTT = VCC – 2V. Table 7. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1) Symbol fXTAL fVCO fMAX Characteristics Crystal interface frequency range VCO frequency range(2) N = 11 (÷1) N = 00 (÷2) N = 01 (÷4) N = 10 (÷8) Min 10 400 400 200 100 50 0 50 45 0.05 S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD N=11 (÷1) N=00 (÷2) N=01 (÷4) N=10 (÷8) N=11 (÷1) N=00 (÷2) N=01 (÷4) N=10 (÷8) 20 20 20 20 20 12 25 55 65 13 23 36 40 10 ms 50 55 0.3 Typ Max 20 900 900 450 225 112.5 10 Unit MHz MHz MHz MHz MHz MHz MHz ns % ns ns ns ns ns ns ps 20% to 80% PWR_DOWN = 0 Condition Output Frequency fS_CLOCK tP,MIN DC tr, tf tS Serial Interface Programming Clock Frequency(3) Minimum Pulse Width Output Duty Cycle Output Rise/Fall Time Setup Time (S-LOAD, P_LOAD) tS tJIT(CC) Hold Time Cycle-to-cycle jitter (RMS 1σ)(4) tJIT(CC) Period jitter (RMS 1σ)(5) tLOCK Maximum PLL Lock Time 1. AC characteristics apply for parallel output termination of 50Ω to VTT. 2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL · M 3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. See APPLICATIONS INFORMATION for more details. 4. Maximum cycle jitter measured at the lowest VCO frequency. Figure 5 shows the cycle jitter vs. frequency characteristics 5. Maximum period jitter measured at the lowest VCO frequency. Figure 6 shows the period jitter vs. frequency characteristics MPC92439 REVISION 4 OCTOBER 27, 2009 6 ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet Table 8. MPC92439 Frequency Operating Range (in MHz) VCO frequency for an crystal interface frequency of M 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ... M[6:0] 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 400 410 420 430 440 450 460 470 480 490 500 510 520 530 540 550 560 570 580 590 600 610 620 630 640 ... 408 420 432 444 456 468 480 492 504 516 528 540 552 564 576 588 600 612 624 636 648 660 672 684 696 708 720 732 744 756 768 ... 406 420 434 448 462 476 490 504 518 532 546 560 574 588 602 616 630 644 658 672 684 700 714 728 742 756 770 784 798 812 826 840 854 868 882 896 ... 400 416 432 448 464 480 496 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 784 800 816 832 848 864 880 896 414 432 450 468 486 504 522 540 558 576 594 612 630 648 666 684 702 720 738 756 774 792 810 828 846 864 882 900 10 12 14 16 18 20 400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 700 720 740 760 780 800 820 840 860 880 900 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER Output frequency for fXTAL=16 MHz and for N = 1 2 4 8 400 416 432 448 464 480 496 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 784 800 816 832 848 864 880 896 200 208 216 224 232 240 248 256 264 272 280 288 296 304 312 320 328 336 344 352 360 368 376 384 392 400 408 416 424 432 440 448 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 MPC92439 REVISION 4 OCTOBER 27, 2009 7 ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER PROGRAMMING INTERFACE Programming the MPC92439 Programming the MPC92439 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: fOUT = fXTAL ⋅ M ÷ N (1) where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured to match the VCO frequency range of 400 to 900 MHz in order to achieve stable PLL operation: MMIN = fVCO,MIN ÷ (fXTAL) and MMAX = fVCO,MAX ÷ (fXTAL) (2) (3) Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 9. Output Frequency Range for fXTAL = 16 MHz N 1 0 0 1 1 0 0 1 0 1 Value 2 4 8 1 FOUT 8⋅M 4⋅M 2⋅M 16⋅M FOUT Range 200-450 MHz 100-225 MHz 50-112.5 MHz 400-900 MHz FOUT Step 8 MHz 4 MHz 2 MHz 16 MHz For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 25 and M = 56. Table 8 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (1) reduces to: fOUT = 16 M ÷ N (4) Example Calculation for an 16 MHz Input Frequency For example, if an output frequency of 384 MHz was desired, the following steps would be taken to identify the appropriate M and N values. 384 MHz falls within the frequency range set by an N value of 2, so N[1:0]=00. For N = 2, FOUT = 8⋅M and M = FOUT÷8. Therefore, M = 384 ÷ 8 = 48, so M[6:0] = 0110000. Following this procedure a user can generate any whole frequency between 50 MHz and 900 MHz. The size of the programmable frequency steps will be equal to: fSTEP = fXTAL ÷ N (5) APPLICATIONS INFORMATION Jitter Performance of the MPC92439 Figure 5 and Figure 6 illustrate the RMS jitter performance of the MPC92439 across its specified VCO frequency range. The cycle-tocycle and period jitter is a function of the VCO frequency and the output divider N. The general trend is that as the output frequency increases (higher VCO frequency and lower N-divider) the MPC92439 output jitter decreases. Optimum jitter performance can be achieved at higher VCO and output frequencies. The maximum cycle-to-cycle and period jitter published in Table 7 correspond to the jitter performance at the lowest VCO frequency limit). Cycle-to-cycle jitter vs. VCO frequency Parameter: Output divider N 70 Period jitter vs. VCO frequency Parameter: Output divider N 40 N=÷8 35 N=÷4 30 25 20 15 N=÷2 10 N=÷1 5 0 400 500 tjit(cyc) [ps] rms 600 700 800 900 VCO frequency [MHz] Figure 6. MPC92439 Period Jitter Using the Parallel and Serial Interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[6:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[6:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 12 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two, and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M6). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW 60 tjit(cyc) [ps] rms 50 N=÷8 N=÷4 40 30 20 10 N=÷2 500 600 700 800 900 N=÷1 400 0 VCO frequency [MHz] Figure 5. MPC92439 Cycle-to-cycle Jitter MPC92439 REVISION 4 OCTOBER 27, 2009 8 ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet transition on the S_LOAD input will latch the new divide values into the counters. Figure 7 illustrates the timing diagram for both a parallel and a serial load of the MPC92439 synthesizer. M[6:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the Test and Diagnosis Output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the LVCMOS output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1 and T0 control bits are preset to ‘000' when P_LOAD is LOW so that the PECL FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC92439 itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC92439 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER the user more control on the test clocks sent through the clocktree shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. Table 10. Test and Debug Configuration for TEST T[2:0] T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST Output 12-bit shift register out(1) Logic 1 fXTAL ÷ 2 M-Counter out FOUT Logic 0 M-Counter out in PLL-bypass mode FOUT ÷ 4 1. Clocked out at the rate of S_CLOCK\ Table 11. Debug Configuration for PLL Bypass(1) Output FOUT TEST S_CLOCK ÷ N M-Counter out(2) Configuration 1. T[2:0] = 110. AC specifications do not apply in PLL bypass mode 2. Clocked out at the rate of S_CLOCK ÷ (2⋅N) S_CLOCK S_DATA S_LOAD M[6:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M6 M5 M4 M3 M2 M1 M0 Last Bit Figure 7. Serial Interface Timing Diagram Power Supply Filtering The MPC92439 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device characteristics. The MPC92439 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of MPC92439 REVISION 4 OCTOBER 27, 2009 9 isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC92439. Figure 8 illustrates a typical power supply filter scheme. The MPC92439 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet the VCC supply and the MPC92439 pin of the MPC92439. From the data sheet, the VCC_PLL current (the current sourced through the VCC_PLL pin) is maximum 20 mA, assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. The resistor shown in Figure 8 must have a resistance of 10–15 Ω to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 µH choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than 15 Ω). RF = 10-15 Ω CF = 2 2 µ F C2 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. C1 C1 1 CF C2 XTAL = VCC = GND = Via VCC VCC_PLL MPC92439 VCC Figure 9. PCB Board Layout Recommendation for the PLCC28 Package The On-Chip Crystal Oscillator The MPC92439 features an integrated on-chip crystal oscillator to minimize system implementation cost. The integrated oscillator is a Pierce-type that uses the crystal in its parallel resonance mode. It is recommended to use a 10 to 20 MHz crystal with a load specification of CL = 10 pF. Crystals with a load specification of CL = 20 pF may be used at the expense of an slightly higher frequency than specified for the crystal. Externally connected capacitors on both the XTAL_IN and XTAL_OUT pins are not required but can be used to fine-tune the crystal frequency as desired. The crystal, the trace and optional capacitors should be placed on the board as close as possible to the MPC92439 XTAL_IN and XTAL_OUT pins to reduce crosstalk of active signals into the oscillator. Short and wide traces further reduce parasitic inductance and resistance. It is further recommended to guard the crystal circuit by placing a ground ring around the traces and oscillator components. See Table 12 for recommended crystal specifications. Table 12. Recommended Crystal Specifications Parameter Crystal Cut Resonance Mode Crystal Frequency Shunt Capacitance C0 Load Capacitance CL Equivalent Series Resistance ESR Value Fundamental AT Cut Parallel 10 - 20 MHz 5 - 7 pF 10 pF 20–60 Ω C1, C2 = 0.01...0.1 µF C1 Figure 8. VCC_PLL Power Supply Filter Layout Recommendations The MPC92439 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 9 shows a representative board layout for the MPC92439. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 9 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC92439 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. Although the MPC92439 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being MPC92439 REVISION 4 OCTOBER 27, 2009 10 ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet As an alternative to parallel resonance mode crystals, the oscillator also works with crystals specified in the series resonance mode. With series resonance crystals, the oscillator frequency and the synthesized output frequency of the MPC92439 will be a approximately 350-400 ppm higher than using crystals specified for parallel frequency mode. This is applicable to applications using the MPC92439 in sockets designed for the pin and function compatible MC12439 synthesizer, which has an oscillator using the crystal in its series resonance mode.Table 13 shows the recommended specifications for series resonance mode crystals 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER Table 13. Alternative Crystal Specifications Parameter Crystal Cut Resonance Mode Crystal Frequency Shunt Capacitance C0 Equivalent Series Resistance ESR Series 10 - 20 MHz 5 - 7 pF 50–80 Ω Value Fundamental AT Cut MPC92439 REVISION 4 OCTOBER 27, 2009 11 ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER Package Outline and Package Dimensions PACKAGE DIMENSIONS CASE 776-02 ISSUE D PLCC PLASTIC PACKAGE MPC92439 REVISION 4 OCTOBER 27, 2009 12 ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER PACKAGE DIMENSIONS 4X 6 D1 PIN 1 INDEX 0.20 H A-B D e/2 3 A, B, D D1/2 32 25 1 E1/2 A 6 E1 DETAIL G 8 B E E/2 4 F F 17 DETAIL G NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. 7 9 D D 4 D/2 4X 0.20 C A-B D H 28X e 32X 0.1 C SEATING PLANE C DETAIL AD PLATING BASE METAL b1 c c1 b 8X 5 8 (θ1˚) R R2 R R1 0.20 M C A-B D SECTION F-F A A2 0.25 GAUGE PLANE A1 (S) (L1) L θ˚ DETAIL AD DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0˚ 7˚ 12 REF 0.08 0.20 0.08 --0.20 REF CASE 873A-03 ISSUE B LQFP PLASTIC PACKAGE MPC92439 REVISION 4 OCTOBER 27, 2009 13 ©2009 Integrated Device Technology, Inc. MPC92439 Data Sheet 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER Package Outline - K Suffix for 32 Lead VFQFN S eating Plan e Ind ex Area N A1 A3 L N 1 2 E2 (N -1)x e E2 2 (Re f.) (Ref.) (N -1)x e (R ef.) N &N Even e (Ty p.) 2 If N & N Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C D2 Bottom View w/Type A ID Bottom View w/Type B ID P 4 BB 2 1 CHAMFER R O Bottom View w/Type C ID D N &N Odd D2 2 P 2 1 RADIUS A (Ref.) e Th er mal Ba se 2 1 N N-1 AA 4 4 O N N-1 ©2009 Integrated Device Technology, Inc. There are 3 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type B: Dummy pad between pin 1 and N. 3. Type C: Mouse bite on the paddle (near pin 1) Table 14. Package Dimensions D CC 4 N N-1 4 DD 4 JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 P R O NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 14. P O S E MPC92439 REVISION 4 OCTOBER 27, 2009 14 S b E To p View Anvil Anvil Singulation Singula tion or OR Sawn Singulation are Even D MPC92439 Data Sheet 900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. 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