MPC9446

3.3V AND 2.5V, LVCMOS CLOCK FANOUT BUFFER MPC9446 The MPC9446 is a 2.5 V and 3.3 V compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed-voltage applications. The MPC9446 offers 10 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1 and 1:2 output to input frequency ratios. The MPC9446 is specified for the extended temperature range of –40°C to 85°C. Features • • • • • • • • • • • Configurable 10 outputs LVCMOS clock distribution buffer Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply Wide range output clock frequency up to 250 MHz Designed for mid-range to high-performance telecom, networking and computer applications Supports applications requiring clock redundancy Maximum output skew of 200 ps (150 ps within one bank) Selectable output configurations per output bank Tristable outputs 32-lead LQFP package 32-lead Pb-free package available Ambient operating temperature range of –40 to 85°C MPC9446 LOW VOLTAGE SINGLE OR DUAL SUPPLY 2.5 V AND 3.3 V LVCMOS CLOCK DISTRIBUTION BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 Functional Description AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be rese,t and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/OE will enable the outputs. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible inputs. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package. IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER 1 MPC9446REV 4 NOVEMBER 28, 2007 MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER CCLK0 CCLK1 CCLK_SEL VCC 25k VCC 25k Bank A 0 1 CLK CLK ÷ 2 0 1 QA0 QA1 QA2 25k 0 1 Bank B QB0 QB1 QB2 QC0 QC1 QC2 QC3 FSELA FSELB FSELC MR/OE Bank C 25k 25k 25k 25k 0 1 Figure 1. MPC9446 Logic Diagram VCCC VCCB VCCB GND GND QB0 QB1 QB2 VCCB is internally connected to VCC 24 VCCA QA2 GND QA1 VCCA QA0 GND MR/OE 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 QC3 GND QC2 VCCC QC1 GND QC0 VCCC MPC9446 13 12 11 10 9 CCLK_SEL CCLK0 CCLK1 VCC FSELA FSELB FSELC Figure 2. Pinout: 32-Lead Package Pinout (Top View) IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER GND 2MPC9446 REV 4 NOVEMBER 28, 2007) MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER Table 1. Pin Configuration Pin CCLK0,1 FSELA, FSELB, FSELC MR/OE GND VCCA, VCCB VCC QA0 – QA2 QB0 – QB2 QC0 – QC3 Output Output Output (1), I/O Input Input Input Type LVCMOS LVCMOS LVCMOS Supply LVCMOS clock inputs Output bank divide select input Function Internal reset and output (high impedance) control Negative voltage supply (GND) Positive voltage supply for output banks Positive voltage supply for core (VCC) Bank A outputs Bank B outputs Bank C outputs VCCC Supply Supply LVCMOS LVCMOS LVCMOS 1. VCCB is internally connected to VCC. Table 2. Supported Single and Dual Supply Configurations Supply Voltage Configuration 3.3 V Mixed Voltage Supply 2.5 V 1. 2. 3. 4. VCC(1) 3.3 V 3.3 V 2.5 V VCCA(2) 3.3 V 3.3 V or 2.5 V 2.5 V VCCB(3) 3.3 V 3.3 V 2.5 V VCCC(4) 3.3 V 3.3 V or 2.5 V 2.5 V GND 0V 0V 0V VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels. VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels. VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC. VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels. Table 3. Function Table (Controls) Control CCLK_SEL FSELA FSELB FSELC MR/OE Default 0 0 0 0 0 CCLK0 fQA0:2 = fREF fQB0:2 = fREF fQC0:3 = fREF Outputs enabled 0 CCLK1 fQA0:2 = fREF ÷ 2 fQB0:2 = fREF ÷ 2 fQC0:3 = fREF ÷ 2 Internal reset outputs disabled (tristate) 1 Table 4. Absolute Maximum Ratings(1) Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature –65 Characteristics Min –0.3 –0.3 –0.3 Max 3.6 VCC+0.3 VCC+0.3 ±20 ±50 125 Unit V V V mA mA °C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER 3MPC9446 REV 4 NOVEMBER 28, 2007) MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER Table 5. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC ÷ 2 Max Unit V V V mA pF pF Per output Condition Table 6. DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3 V ± 5%, TA = –40°C to +85°C) Symbol VIH VIL IIN VOH VOL ZOUT ICCQ (3) Characteristics Input High Voltage Input Low Voltage Input Current (1) Min 2.0 –0.3 Typ Max VCC + 0.3 0.8 200 Unit V V µA V Condition LVCMOS LVCMOS VIN = GND or VIN = VCC IOH = –24 mA(2) IOL = 24 mA(2) IOL = 12 mA All VCC Pins Output High Voltage Output Low Voltage Output Impedance Maximum Quiescent Supply Current 2.4 0.55 0.30 14 – 17 2.0 V V Ω mA 1. Input pull-up / pull-down resistors influence input current. 2. The MPC9446 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3 V ± 5%, TA = –40°C to +85°C)(1) Symbol fref fMAX tP, REF tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) Input Frequency Maximum Output Frequency Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-Device Skew Output Pulse Skew(4) ÷1 output ÷2 output 47 45 0.1 50 50 CCLK0,1 to any Q CCLK0,1 to any Q 2.2 2.2 2.8 2.8 ÷1 output ÷2 output Characteristics Min 0 0 0 1.4 1.0(3) 4.45 4.2 10 10 150 200 350 2.25 200 53 55 1.0 Typ Max 250(2) 250(2) 125 Unit MHz MHz MHz ns ns ns ns ns ns ps ps ps ns ps % % ns DCREF = 50% DCREF = 25%–75% 0.55 to 2.4 V 0.8 to 2.0 V FSELx = 0 FSELx = 1 Condition tsk(PP) tSK(P) DCQ tr, tf Output Duty Cycle Output Rise/Fall Time 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency dependent: DCQ = (0.5 ± tSK(P) • fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%. IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER 4MPC9446 REV 4 NOVEMBER 28, 2007) MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40°C to +85°C) Symbol VIH VIL VOH VOL ZOUT IIN ICCQ (3) Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current(2) Maximum Quiescent Supply Current Min 1.7 –0.3 1.8 Typ Max VCC + 0.3 0.7 0.6 Unit V V V V Ω µA mA Condition LVCMOS LVCMOS IOH = –15 mA(1) IOL = 15 mA VIN = GND or VIN = VCC All VCC Pins 17 – 20 (2) ±200 2.0 1. The MPC9446 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines per output. 2. Input pull-up / pull-down resistors influence input current. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40°C to +85°C)(1) Symbol fref fMAX tP, REF tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ tsk(O) Input Frequency Maximum Output Frequency Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-Device Skew Output Pulse Skew(4) ÷1 or ÷2 output 45 0.1 50 CCLK0,1 to any Q CCLK0,1 to any Q 2.6 2.6 ÷1 output ÷2 output Characteristics Min 0 0 0 1.4 1.0(3) 5.6 5.5 10 10 150 200 350 3.0 200 55 1.0 Typ Max 250(2) 250(2) 125 Unit MHz MHz MHz ns ns ns ns ns ns ps ps ps ns ps % ns DCREF = 50% 0.6 to 1.8 V 0.7 to 1.7 V FSELx = 0 FSELx = 1 Condition tsk(PP) tSK(P) DCQ tr, tf Output Duty Cycle Output Rise/Fall Time 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency dependent: DCQ = (0.5 ± tSK(P) • fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%. Table 10. AC Characteristics (VCC = 3.3 V + 5%, VCCA, VCCB, VCCC = 2.5 V + 5% or 3.3 V + 5%, TA = –40°C to +85°C)(1) (2) Symbol tsk(O) Characteristics Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider Device-to-Device Skew Propagation Delay Output Pulse Skew(3) Output Duty Cycle ÷1 or ÷2 output 45 50 CCLK0,1 to any Q See 3.3 V Table 250 55 ps % DCREF = 50% Min Typ Max 150 250 350 2.5 Unit ps ps ps ns Condition tsk(PP) tPLH,HL tSK(P) DCQ 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. For all other AC specifications, refer to 2.5 V or 3.3 V tables according to the supply voltage of the output bank. 3. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency dependent: DCQ = (0.5 ± tSK(P) • fOUT). IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER 5MPC9446 REV 4 NOVEMBER 28, 2007) MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER APPLICATIONS INFORMATION Driving Transmission Lines The MPC9446 clock driver was designed to drive highspeed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω, the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale application note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 Ω resistance to VCC÷2. This technique draws a fairly high level of DC current, and thus, only a single terminated line can be driven by each output of the MPC9446 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 3 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9446 clock driver is effectively doubled due to its capability to drive multiple lines. the line impedances. The voltage wave launched down the two lines will equal: VL = Z0 = RS = R0 = VL = = VS (Z0 ÷ (RS + R0 + Z0)) 50 Ω || 50 Ω 36 Ω || 36 Ω 14 Ω 3.0 (25 ÷ (18 + 14 + 25) 1.31 V At the load end, the voltage will double, due to the near unity reflection coefficient, to 2.5 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 3.0 2.5 2.0 Voltage (V) In 1.5 1.0 OutA tD = 3.8956 OutB tD = 3.9386 MPC9446 Output Buffer IN 14Ω RS = 36Ω ZO = 50Ω OutA 0.5 0 2 4 6 8 Time (ns) 10 12 14 MPC9446 Output Buffer IN 14Ω Figure 4. Single versus Dual Waveforms RS = 36Ω ZO = 50Ω OutB0 RS = 36Ω ZO = 50Ω OutB1 Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4 show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9446 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations, a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9446. The output waveform in Figure 4 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 Ω series resistor plus the output impedance does not match the parallel combination of Since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 5 should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. MPC9446 Output Buffer 14Ω RS = 22Ω ZO = 50Ω RS = 22Ω ZO = 50Ω 14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω 25 Ω = 25 Ω Figure 5. Optimized Dual Line Termination IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER 6MPC9446 REV 4 NOVEMBER 28, 2007) MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER MPC9446 DUT Pulse Generator Z = 50Ω ZO = 50Ω ZO = 50 Ω R T = 50 Ω VTT RT = 50Ω VTT Figure 6. CCLK0, 1 MPC9446 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V VCC = 3.3V 2.4 0.55 tF tR VCC = 2.5V 1.8V 0.6V Qx t(LH) t(HL) VCC CCLK VCC÷2 GND VCC VCC÷2 GND Figure 7. Output Transition Time Test Reference Figure 8. Propagation Delay (tPD) Test Reference VCC VCC÷2 GND VCC VCC÷2 GND tSK(LH) tSK(HL) CCLK VCC VCC÷2 GND VCC VCC÷2 GND t(LH) t(HL) QX The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device. tSK(P) = | tPLH – tPHL | Figure 9. Output-to-Output Skew tSK(LH, HL) Figure 10. Output Pulse Skew (tSK(P)) Test Reference VCC VCC÷2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. Figure 11. Output Duty Cycle (DC) IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER 7MPC9446 REV 4 NOVEMBER 28, 2007) MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER PACKAGE DIMENSIONS PAGE 1 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER 8MPC9446 REV 4 NOVEMBER 28, 2007) MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER PACKAGE DIMENSIONS PAGE 2 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER 9MPC9446 REV 4 NOVEMBER 28, 2007) MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE PAGE 3 OF 3 IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER 10MPC9446 REV 4 NOVEMBER 28, 2007) MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER Innovate with IDT and accelerate your future networks. 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