MPC9447

MOTOROLA Freescale SEMICONDUCTOR TECHNICAL DATA Semiconductor, Inc. Order Number: MPC9447/D Rev 2, SHEET DATA 04/2003 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer MPC9447 3.3V/2.5V 1:9 LVCMOS Clock The MPC9447 is a 3.3V or 2.5V compatible, 1:9 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. Freescale Semiconductor, Inc... • • • • • Features 9 LVCMOS Compatible Clock Outputs 2 Selectable, LVCMOS Compatible Inputs Maximum Clock Frequency of 350 MHz Maximum Clock Skew of 150 ps 3.3 V/2.5 V LVCMOS 1:9 CLOCK FANOUT BUFFER Synchronous Output Stop in Logic Low State Eliminates Output Runt Pulses • High--Impedance Output Control • • • • • 3.3V or 2.5V Power Supply Drives up to 18 Series Terminated Clock Lines Ambient Temperature Range --40_C to +85_C 32 Lead LQFP Packaging FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A Supports Clock Distribution in Networking, Telecommunications, and Computer Applications • Pin and Function Compatible to MPC947 Functional Description MPC9447 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50Ω terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable independent LVCMOS compatible clock inputs are available, providing support of redundant clock source systems. The MPC9447 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high--impedance mode. All inputs have an internal pull--up or pull--down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of --40_C to +85_C. The MPC9447 is pin and function compatible but performance--enhanced to the MPC947. IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 1 MPC9447 MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer MPC9447 Freescale Semiconductor, Inc. GND GND GND VCC VCC Q3 Q4 Q5 NETCOM Q0 CCLK0 CCLK1 VCC CLK_SEL VCC CLK_STOP SYNC Q4 Q5 0 1 CLK STOP 24 Q1 GND Q2 Q3 Q2 VCC Q1 GND Q0 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 GND Q6 VCC Q7 GND Q8 VCC GND MPC9447 13 12 11 10 9 Q6 VCC Q7 GND Freescale Semiconductor, Inc... VCC (all input resistors have a value of 25kΩ) OE Q8 CLK_SEL CLK_STOP GND VCC Unit V V V mA 10 4.0 pF pF Per output Inputs CCLK0 CCLK1 GND 1 CLK1 input selected Outputs enabled Outputs active Condition OE Figure 1. Logic Diagram Figure 2. 32-Lead Pinout (Top View) Table 1. Function Table Control CLK_SEL OE CLK_STOP Default 1 1 1 CLK0 input selected Outputs disabled (high--impedance state)a Outputs synchronously stopped in logic low state 0 a. OE = 0 will high--impedance tristate all outputs independent on CLK_STOP Table 2. Pin Configuration Pin CCLK0 CCLK1 CLK_SEL CLK_STOP OE Q0--8 GND VCC I/O Input Input Input Input Input Output Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC Clock signal input Alternative clock signal input Clock input select Clock output enable/disable Output enable/disable (high--impedance tristate) Clock outputs Negative power supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function Table 3. General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Power dissipation capacitance Input capacitance 200 2000 200 Min Typ VCC ÷ 2 Max IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer MOTOROLA For More Iby Integrated Device Technology, Inc Freescale Timing Solutions Organization has been acquired nformation On This Product, Go to: www.freescale.com 2 2 TIMING SOLUTIONS MPC9447 MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Semiconductor, Inc. NETCOM MPC9447 Table 4. Absolute Maximum Ratingsa Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 ±20 ±50 125 Unit V V V mA mA °C Condition a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 3.3V ± 5%, TA = 40°C to +85°C) Symbol Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Currentb Maximum Quiescent Supply Currentc 17 ±300 2.0 Min 2.0 --0.3 2.4 0.55 0.30 Typ Max VCC + 0.3 0.8 Unit V V V V V Ω µA mA VIN = VCC or GND All VCC Pins Condition LVCMOS LVCMOS IOH = -24 mAa IOL = 24 mA IOL = 12 mA Freescale Semiconductor, Inc... VIH VIL VOH VOL ZOUT IIN ICCQ a. The MPC9447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for VCC=3.3V). b. Inputs have pull-down or pull-up resistors affecting the input current. c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 6. AC Characteristics (VCC = 3.3V ± 5%, TA = --40°C to +85°C)a Symbol fref fmax fP,REF tr, tf tPLH/HL tPLZ, HZ tPZL, ZH tS tH tsk(O) tsk(PP) tSK(P) DCQ tr, tf tJIT(CC) Input Frequency Output Frequency Reference Input Pulse Width CCLK0, CCLK1 Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Setup Time Hold Time Output-to-Output Skew Device-to-Device Skew Output Pulse Skewd Output Duty Cycle Output Rise/Fall Time Cycle-to-cycle jitter RMS (1 σ) fQ