RC32365T365-150BCG

IDTTM InterpriseTM Integrated Communications Processor RC32365 Device Overview The RC32365 device is a member of the IDT™ Interprise™ family of integrated communications processors. This device is designed to address a range of communications applications that require the efficient processing of IPSec algorithms. These applications include gateways, wireless access points, and virtual private network (VPN) equipment. The key to the RC32365’s efficient processing of IPSec algorithms is a highly progammable security engine which off-loads the CPU core of encryption/decryption, hashing, and padding tasks. Features List ◆ RC32300 32-bit CPU core – 32-bit MIPS instruction set – Supports big or little endian operation – MMU – 16-entry TLB – Supports variable page sizes and enhanced write algorithm – Supports variable number of locked entries – 8KB Instruction Cache – 2-way set associative – LRU replacement algorithm – 4 word line size – Sub-block ordering – Word parity – Per line cache locking – 2KB Data Cache 2-way set associative LRU replacement algorithm 4 word line size Sub-block ordering Byte parity Per line cache locking Can be programmed on a page basis to implement writethrough no write allocate, write-through write allocate, or write-back algorithms – Enhanced EJTAG and JTAG Interfaces – Compatible with IEEE Std. 1149.1-1990 ◆ Security Engine – Dedicated DMA channels for high speed data transfers to and from the security engine – On-chip memory for storage of two security contexts – Supports ECB and CBC modes for the following symmetric encryption algorithms: DES, triple DES (both two key (k1=k3) and three key (k1!=k3) modes), AES-128 with 128-bit blocks, AES-192 with 128-bit blocks – Hardware support for encryption pad generation and checking using one of seven popular padding algorithms: supports pad algorithm required by IPSec ESP – Supports MD5 and SHA-1 one-way hash functions – Programmable truncation length of computed hash and HMAC on a security context basis – Supports concurrent hash and encryption operations – – – – – – – Block Diagram MII MII 32-bit MIPS CPU Core JTAG EJTAG D. Cache MMU I. Cache Security Functions Interrupt Controller . . Bus/System Integrity Monitor 2 Ethernet 10/100 Interfaces Security Context Storage Hash Unit RNG Encryption Unit DMA Controller Arbiter IPBusTM Controllers including PCMCIA Support SDRAM & Device 3 Counter Timers UART (16550) GPIO Interface SPI Controller PCI Master/Target Interface PCI Arbiter (Host Mode) Memory & Peripheral Bus (including PCMCIA) Serial Channel GPIO Pins SPI Bus PCI Bus Figure 1 RC32365 Internal Block Diagram IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 of 44 © 2005 Integrated Device Technology, Inc. October 5, 2005 DSC 6210 RC32365 – Optimized for IPSec AH, ESP, and AH+ESP (single MAC) tunnel and transport mode processing: initialization Vector (IV) insertion and extraction, HMAC checking, AH mutable field processing for both IPv4 and IPv6 packets, IPSec pad generation and checking ◆ Random Number Generator – True hardware random number generator suitable for security applications: may be used to generate symmetric and public keys, initialization vectors, and nonces – Dedicated DMA engine for transferring random numbers to memory – Generates random numbers at a bit rate equal to IPBus clock frequency divided by 32 – Provides 4 word (16 byte) FIFO to queue random numbers – Randomness tester continually verifies proper operation of random number generator using a randomness test defined in FIPS 140-2 ◆ PCI Interface – 32-bit PCI revision 2.2 compliant – Supports host or satellite operation in both master and target modes – PCI clock: supports frequencies from 16 MHz to 66 MHz, PCI clock may be asynchronous to master clock (CLK) – PCI arbiter in Host mode: supports 3 external masters, fixed priority or round robin arbitration – I2O “like” PCI Messaging Unit ◆ Two Ethernet Interfaces – 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant – Two IEEE 802.3u compatible Media Independent Interfaces (MII) with serial management interface – MII supports IEEE 802.3u auto-negotiation speed selection – Supports 64 entry hash table based multicast address filtering – 512 byte transmit and receive FIFOs – Supports flow control functions outlined in IEEE Std. 802.3x1997 ◆ SDRAM Controller – Supports up to 512 MB of memory – 2 chip selects (each supports 2 or 4 banks internal SDRAM banks) – 32-bit data width, supports 8/16/32-bit width devices – Supports 16Mb, 64Mb, 128Mb, and 256Mb, and 512Mb devices – Automatic refresh generation ◆ Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Provides “glueless” interface to many 16-bit PCMCIA devices – Demultiplexed address and data buses: 32-bit data bus, 26-bit address bus, 6 chip selects, control for external data bus buffers – Supports 8-bit, 16-bit, and 32-bit width devices: automatic byte gathering and scattering – Flexible protocol configuration parameters: programmable number of wait states (0 to 63), programmable postread/postwrite delay (0 to 31), supports external wait state generation, supports Intel and Motorola style peripherals – Write protect capability per chip select – Programmable bus transaction timer generates warm reset when counter expires – Supports up to 64MB of memory per chip select ◆ DMA Controller – 9 DMA channels: two channels for each of the two Ethernet interfaces (transmit/receive), two channels for PCI (PCI to Memory and Memory to PCI), two channels for security engine (input/output), one channel for the hardware random number generator – Provides flexible descriptor based operation – Supports unaligned transfers (i.e., source or destination address may be on any byte boundary) with arbitrary byte length ◆ General Purpose Peripherals – Serial port compatible with 16550 Universal Asynchronous Receiver Transmitter (UART) – Three general purpose 32-bit counter/timers – Interrupt Controller – Serial Peripheral Interface (SPI) supporting host mode – 16 general purpose I/O (GPIO) pins which can be configured as interrupt sources ◆ System Features – JTAG Interface (IEEE Std. 1149.1 compatible) – 256 pin CABGA package – 2.5V core supply and 3.3V I/O supply CPU Execution Core The RC32365 is built around the RC32300 32-bit high performance microprocessor core. The RC32300 implements the enhanced MIPS-II ISA and helps meet the real-time goals and maximize throughput of communications and consumer systems by providing capabilities such as a prefetch instruction, multiple DSP instructions, and cache locking. The instruction set is largely compatible with the MIPS32 instruction set, allowing the customer to select from a broad range of software and development tools. Cache locking guarantees real-time performance by holding critical code and parameters in the cache for immediate availability. The microprocessor also implements an on-chip MMU with a TLB, making the it fully compliant with the requirements of real time operating systems. Security Engine The RC32365 incorporates an on-chip security engine that has been designed to accelerate IPSec performance and minimize the amount of performance required by the CPU to process secure packet traffic. The engine includes hardware support for the DES, 3DES, and AES encryption algorithms and the MD5 and SHA1 hash functions. The engine also supports hardware-assisted packet processing for the various modes of IPSec, including AH, ESP, and AH+ESP tunnel and transport modes. Two dedicated DMA channels are used to transfer data to and from the security engine, allowing the CPU to work on other tasks during this time. 2 of 44 October 5, 2005 RC32365 PCI Interface The PCI interface on the RC32365 is compatible with version 2.2 of the PCI specification. An on-chip arbiter supports up to three external bus masters, supporting both fixed priority and rotating priority arbitration schemes. The RC32365 can support both satellite and host PCI configurations, enabling it to act as a slave controller for a PCI add-in card application, or as the primary PCI controller in the system. The PCI interface can be operated synchronously or asynchronously to the other I/O interfaces on the RC32365 device. PCMCIA Interface The RC32365 provides a "glueless" connection to a single PCMCIA I/O device via the memory and peripheral device controller. The PCMCIA interface allows the RC32365 to connect to various types of I/O peripherals including fax modems, storage devices, and wireless LAN chipsets. The RC32365 implementation provides a maximum throughput of 160 Mbps through the 16-bit wide interface as specified by the PCMCIA 2.1 Standard. Ethernet Interface The RC32365 has two Ethernet Channels supporting 10Mbps and 100Mbps speeds and provides a standard media independent interface (MII) off-chip, allowing a wide range of external devices to be connected efficiently. Memory and I/O Controller The RC32365 incorporates a flexible memory and peripheral device controller providing direct support for SDRAM, Flash ROM, SRAM, PCMCIA, and other I/O devices. It can interface directly to 8-bit boot ROM for a very low cost system implementation. It also offers various trade-offs in cost / performance for the main memory architecture. The timers implemented on the RC32365 satisfy the requirements of most real time operating systems. DMA Controller The DMA controller off-loads the CPU core from moving data among the on-chip interfaces, external peripherals, and memory. The DMA controller supports scatter / gather DMA with no alignment restrictions, appropriate for communications and graphics systems. Enhanced JTAG Interface For system debugging, the RC32300 CPU core includes an Enhanced JTAG (EJTAG) interface which operates in Run-Time Mode. Revision History March 17, 2003: Initial publication. May 15, 2003: Removed “write protect capability” from features of the SDRAM Controller. July 9, 2003: In Table 6, changed values for RSTN (output). Changed values in Tables 7, 8, 9, 10, and 17. October 3, 2003: Added 180 MHz speed grade. Changed min values in Table 7 from 1.8 to 1.2 for all signals except SDCLKINP and SDCKENP. Changed min values for Tdo 10b and 10c in Table 10 for PCIBEN, etc. and PCIGNTN/PCIREQN from 2.0 to 1.5. February 25, 2004: Deleted reference to RNGCLK in Table 1 (GPIO[6]) and Table 22. May 25, 2004: In Table 9, signals MIIxRXCLK and MIIxTXCLK, the Min and Max values for Thigh/Tlow_9c were changed to 140 and 260 respectively and the Min and Max values for Thigh/Tlow_9d were changed to 14.0 and 26.0 respectively. October 5, 2005: Removed 180 MHz speed grade. Thermal Considerations The RC32365 is guaranteed in a ambient temperature range of 0° to +70° C for commercial temperature devices and - 40° to +85° for industrial temperature devices. 3 of 44 October 5, 2005 RC32365 Pin Description Table The following table lists the functions of the pins provided on the RC32365. Some of the functions listed may be multiplexed onto the same pin (indicated as alternate functions). To define the active polarity of a signal, a suffix will be used. Signals ending with an “N” should be interpreted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description Memory and Peripheral Bus BDIRN O External Buffer Direction. Memory and peripheral bus external data bus buffer direction control. If the RC32365 memory and peripheral bus is connected to the A side of a transceiver such as an IDT74FCT245, then this pin may be directly connected to the direction control (e.g., BDIR) pin of the transceiver. External Buffer Enable. These signals provide output enable control for external buffers on the memory and peripheral data bus. Byte Write Enables. These signals are memory and peripheral bus byte write enable signals. BWEN[0] corresponds to byte lane MDATA[7:0] BWEN[1] corresponds to byte lane MDATA[15:8] BWEN[2] corresponds to byte lane MDATA[23:16] BWEN[3] corresponds to byte lane MDATA[31:24] Chip Selects. These signals are used to select an external device on the memory and peripheral bus. Address Bus. 22-bit memory and peripheral bus address bus. MADDR[25:22] are available as GPIO[5:2] alternate functions. Data Bus. 32-bit memory and peripheral data bus. During a cold reset, bits 0 through 16 of this data bus function as inputs that are used to load the boot configuration vector. Output Enable. This signal is asserted when data should be driven by an external device on the memory and peripheral bus. Read Write. This signal indicates whether the transaction on the memory and peripheral bus is a read transaction or a write transaction. A high level indicates a read from an external device. A low level indicates a write to an external device. Wait or Transfer Acknowledge. When configured as wait, this signal is asserted during a memory and peripheral bus transaction to extend the bus cycle. When configured as a transfer acknowledge, this signal is asserted during a transaction to signal the completion of the transaction. SDRAM Row Address Strobe. Row address strobe asserted during memory and peripheral bus SDRAM transactions. SDRAM Column Address Strobe. Column address strobe asserted during memory and peripheral bus SDRAM transactions. SDRAM Chip Selects. These signals are used to select SDRAM device(s) on the memory and peripheral bus. SDRAM Write Enable. This signal is asserted during memory and peripheral bus SDRAM write transactions. SDRAM Clock Output. This clock is used for all SDRAM memory and peripheral bus operations. SDRAM Clock Input. This clock input is typically a delayed version of SDCLKOUT. Data from the SDRAMs is sampled using this clock. Table 1 Pin Description (Part 1 of 6) BOEN[1:0] BWEN[3:0] O O CSN[5:0] MADDR[21:0] MDATA[31:0] OEN RWN O O I/O O O WAITACKN I RASN CASN SDCSN[1:0] SDWEN SDCLKOUT SDCLKINP O O O O O I 4 of 44 October 5, 2005 RC32365 Signal General Purpose I/O GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0SOUT Alternate function: UART channel 0 serial output. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0SINP Alternate function: UART channel 0 serial input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[22] Alternate function: Memory and Peripheral bus address bit 22 (output). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[23] Alternate function: Memory and Peripheral bus address bit 23 (output). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[24] Alternate function: Memory and Peripheral bus address bit 24 (output). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[25] Alternate function: Memory and Peripheral bus address bit 25 (output). General Purpose I/O. This pin can be configured as a general purpose I/O pin. The value of this pin may be used as a Counter Timer Clock input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: SDCKENP Alternate function: SDRAM clock enable output The value of this pin may be used as a Counter Timer Clock input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: CEN1 Alternate function: PCMCIA chip enable 1 (CE1#) (output). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: CEN2 Alternate function: PCMCIA chip enable 2 (CE2#) (output). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: REGN Alternate function: PCMCIA Attribute Memory Select (REG#) (output). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IORDN Alternate function: PCMCIA IO Read (IORD#) (output). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOWRN Alternate function: PCMCIA IO Write (IOWR#) (output). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIREQN[2] Alternate function: PCI bus request 2 (output). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIGNTN[2] Alternate function: PCI bus grant 2 (output). Table 1 Pin Description (Part 2 of 6) Type Name/Description GPIO[1] I/O GPIO[2] I/O GPIO[3] I/O GPIO[4] I/O GPIO[5] I/O GPIO[6] GPIO[7] I/O I/O GPIO[8] I/O GPIO[9] I/O GPIO[10] I/O GPIO[11] I/O GPIO[12] I/O GPIO[13] I/O GPIO[14] I/O 5 of 44 October 5, 2005 RC32365 Signal GPIO[15] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIMUINTN Alternate function: PCI Messaging unit interrupt output. Serial Interface SCK SDI SDO PCI Bus PCIAD[31:0] I/O PCI Multiplexed Address/Data Bus. Address is driven by a bus master during initial PCIFRAMEN assertion. Data is then driven by the bus master during writes or by the bus target during reads. PCI Multiplexed Command/Byte Enable Bus. PCI command is driven by the bus master during the initial PCIFRAMEN assertion. Byte enables are driven by the bus master during subsequent data phase(s). PCI Clock. Clock used for all PCI bus transactions. PCI Device Select. This signal is driven by a bus target to indicate that the target has decoded the address as one of its own address spaces. PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus transaction. Negation indicates the last data. PCI Bus Grant. In PCI host mode with internal arbiter: The assertion of these signals indicates to the agent that the internal RC32365 arbiter has granted the agent access to the PCI bus. In PCI host mode with external arbiter: PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32365 that access to the PCI bus has been granted. PCIGNTN[1]: unused and driven high. In PCI satellite mode: PCIGNTN[0]: this signal is asserted by an external arbiter to indicate to the RC32365 that access to the PCI bus has been granted. PCIGNTN[1]: this signal takes on the alternate function of PCIEECS and is used as a PCI Serial EEPROM chip select. PCI Initiator Ready. Driven by the bus master to indicate that the current data can complete. PCI Lock. This signal is asserted by an external bus master to indicate that an exclusive operation is occurring. PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during address and write data phases. Driven by the bus target during the read data phases. PCI Parity Error. This signal is asserted by the receiving bus agent 2 clocks after the data is received if a parity error is detected. Table 1 Pin Description (Part 3 of 6) I/O I/O I/O Serial Clock. This signal is used as the serial SPI clock output. This pin may be used as a bit input/output port. Serial Data Input. This signal is used to shift in serial SPI data. This pin may be used as a bit input/output port. Serial Data Output. This signal is used to shift out serial SPI data. This pin may be used as a bit input/output port. PCICBEN[3:0] I/O PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[1:0] I I/O I/O I/O PCIIRDYN PCILOCKN PCIPAR PCIPERRN I/O I/O I/O I/O 6 of 44 October 5, 2005 RC32365 Signal PCIREQN[1:0] Type I/O Name/Description PCI Bus Request. In PCI host mode with internal arbiter: These signals are inputs whose assertion indicates to the internal RC32365 arbiter that an agent desires ownership of the PCI bus. In PCI host mode with external arbiter: PCIREQN[0]: asserted by the RC32365 to request ownership of the PCI bus. PCIREQN[1]: unused and driven high. In PCI satellite mode: PCIREQN[0]: this signal is asserted by the RC32365 to request ownership of the PCI bus. PCIREQN[1]: function changes to PCIIDSEL and is used as a chip select during configuration read and write transactions. PCI Reset. In host mode, this signal is asserted by the RC32365 to generate a PCI reset. In satellite mode, assertion of this signal initiates a warm reset. PCI System Error. This signal is driven by an agent to indicate an address parity error, data parity error during a special cycle command, or any other system error. Requires an external pull-up. PCI Stop. Driven by the bus target to terminate the current bus transaction. For example, to indicate a retry. PCI Target Ready. Driven by the bus target to indicate that the current data can complete. PCIRSTN PCISERRN PCISTOPN PCITRDYN Ethernet Interface MII0CL MII0CRS MII0RXCLK MII0RXD[3:0] MII0RXDV MII0RXER MII0TXCLK MII0TXD[3:0] MII0TXENP MII0TXER MII1CL MII1CRS MII1RXCLK I/O I/O I/O I/O I I I I I I I O O O I I I Ethernet 0 MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is detected. Ethernet 0 MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle. Ethernet 0 MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data. Ethernet 0 MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY. Ethernet 0 MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus. Ethernet 0 MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the MII receive data bus. Ethernet 0 MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data. Ethernet 0 MII Transmit Data. This nibble wide data bus contains the data to be transmitted. Ethernet 0 MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission. Ethernet 0 MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols which are not valid data or delimiters. Ethernet 1 MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is detected. Ethernet 1 MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle. Ethernet 1 MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data. Table 1 Pin Description (Part 4 of 6) 7 of 44 October 5, 2005 RC32365 Signal MII1RXD[3:0] MII1RXDV MII1RXER MII1TXCLK MII1TXD[3:0] MII1TXENP MII1TXER MIIMDC MIIMDIO EJTAG / JTAG JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. When using the EJTAG debug interface, this pin should be left disconnected (since there is an internal pull-up) or driven high. EJTAG Mode. The value on this signal controls the test mode select of the EJTAG Controller. When using the JTAG boundary scan, this pin should be left disconnected (since there is an internal pull-up) or driven high. JTAG Reset. This active low signal asynchronously resets the boundary scan logic, JTAG TAP Controller, and the EJTAG Debug TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board 3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high. JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic, JTAG Controller, or the EJTAG Controller. JTAG_TCK is independent of the system and the processor clock with a nominal 50% duty cycle. JTAG Data Output. This is the serial data shifted out from the boundary scan logic, JTAG Controller, or the EJTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Data Input. This is the serial data input to the boundary scan logic, JTAG Controller, or the EJTAG Controller. Table 1 Pin Description (Part 5 of 6) Type I I I I O O O O I/O Name/Description Ethernet 1 MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY. Ethernet 1 MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus. Ethernet 1 MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the MII receive data bus. Ethernet 1 MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data. Ethernet 1 MII Transmit Data. This nibble wide data bus contains the data to be transmitted. Ethernet 1 MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission. Ethernet 1 MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols which are not valid data or delimiters. MII Management Data Clock. This signal is used as a timing reference for transmission of data on the management interface. MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the ethernet PHY. EJTAG_TMS I JTAG_TRST_N I JTAG_TCK I JTAG_TDO JTAG_TDI O I 8 of 44 October 5, 2005 RC32365 Signal Miscellaneous CLK I Master Clock. This is the master clock input. The processor frequency is a multiple of this clock frequency. This clock is used as the system clock for all memory and peripheral bus operations except those associated with SDRAMs. Cold Reset. The assertion of this signal initiates a cold reset. This causes the processor state to be initialized, boot configuration to be loaded, and the internal PLL to lock onto the master clock (CLK). Reset. The assertion of this bidirectional signal initiates a warm reset. This signal is asserted by the RC32365 during a warm reset. It can also be asserted by an external device to force the RC32365 to take a warm reset exception. Table 1 Pin Description (Part 6 of 6) Type Name/Description COLDRSTN I RSTN I/O Pin Characteristics Pin Name Memory and Peripheral Bus BDIRN BOEN[1:0] BWEN[3:0] CSN[5:0] MADDR[21:0] MDATA[31:0] OEN RWN WAITACKN RASN CASN SDCSN[1:0] SDWEN SDCLKOUT SDCLKINP General Purpose I/O GPIO[15:13] GPIO[12:0] Serial Interface SCK SDI SDO PCI Bus Interface PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN Type O O O O O I/O O O I O O O O O I I/O I/O I/O I/O I/O I/O I/O I I/O Buffer LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL PCI LVTTL LVTTL LVTTL LVTTL PCI PCI PCI PCI I/O Type High Drive High Drive High Drive High Drive High Drive High Drive High Drive High Drive STI2 High Drive High Drive High Drive High Drive High Drive STI PCI Low Drive Low Drive Low Drive Low Drive PCI PCI PCI PCI Internal Resistor External Resistor1 pull-up pull-up pull-up pull-up pull-up pull-up pull-up on board pull-up on board pull-up on board pull-up on board Table 2 Pin Characteristics (Part 1 of 2) 9 of 44 October 5, 2005 RC32365 Pin Name PCIFRAMEN PCIGNTN[1:0] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[1:0] PCIRSTN PCISERRN PCISTOPN PCITRDYN Ethernet Interfaces MII0CL MII0CRS MII0RXCLK MII0RXD[3:0] MII0RXDV MII0RXER MII0TXCLK MII0TXD[3:0] MII0TXENP MII0TXER MII1CL MII1CRS MII1RXCLK MII1RXD[3:0] MII1RXDV MII1RXER MII1TXCLK MII1TXD[3:0] MII1TXENP MII1TXER MIIMDC MIIMDIO EJTAG / JTAG JTAG_TMS EJTAG_TMS JTAG_TRST_N JTAG_TCK JTAG_TDO JTAG_TDI Miscellaneous CLK COLDRSTN RSTN 1. Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I O O O I I I I I I I O O O O I/O I I I I O I I I I/O Buffer PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL I/O Type PCI PCI PCI PCI PCI PCI PCI PCI Open Collector; PCI PCI PCI STI STI STI STI STI STI STI Low Drive Low Drive Low Drive STI STI STI STI STI STI STI Low Drive Low Drive Low Drive Low Drive Low Drive STI STI STI STI Low Drive STI STI STI Low Drive / STI Internal Resistor External Resistor1 pull-up on board pull-up on board pull-up on board pull-up on board pull-down on board pull-up on board pull-up on board pull-up on board pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up See Chapters 22 and 23 of the RC32365 User Reference Manual pull-up pull-up on board Table 2 Pin Characteristics (Part 2 of 2) External pull-up required in most system applications. Some applications may require additional pull-ups not identified in this table. Trigger Input (STI). 2. Schmidt 10 of 44 October 5, 2005 RC32365 Boot Configuration Vector The boot configuration vector is read into the RC32365 during cold reset. The vector defines parameters in the RC32365 that are essential to operation when cold reset is complete. The encoding of boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4. Signal MDATA[2:0] Name/Description CPU Clock Multiplier. This field specifies the value by which the PLL multiplies the master clock input (CLK) to obtain the processor clock frequency (PCLK). 0x0 - Multiply by 2 0x1 - 0x7 — Reserved Endian. This bit specifies the endianness. 0x0 - little endian 0x1 - big endian Reserved. This pin may be driven high or low during boot configuration and its state is recorded in the Boot Configuration Vector (BCV) field of the BCV register. This reserved bit may be used to pass boot configuration parameters to software. Boot Device Width. This field specifies the width of the boot device (i.e., Device 0). 0x0 - 8-bit boot device width 0x1 - 16-bit boot device width 0x2 - 32-bit boot device width 0x3 - reserved Reset Mode. This bit specifies the length of time the RSTN signal is driven. 0x0 - Normal reset: RSTN driven for minimum of 4096 clock cycles 0x1 - reserved Disable Watchdog Timer. When this bit is set, the watchdog timer is disabled following a cold reset. 0x0 - Watchdog timer is enabled 0x1 - Watchdog timer is disabled PCI Mode. This bit controls the operating mode of the PCI bus interface. The initial value of the EN bit in the PCIC register is determined by the PCI mode. 0x0 - Disabled (EN initial value is zero) 0x1 - PCI satellite mode with PCI target not ready (EN initial value is one) 0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one) 0x3 - PCI host mode with external arbiter (EN initial value is zero) 0x4 - PCI host mode with internal arbiter using fixed priority arbitration algorithm (EN initial value is zero) 0x5 - PCI host mode with internal arbiter using round robin arbitration algorithm (EN initial value is zero) 0x6 - reserved 0x7 - reserved Reserved. These pins may be driven high or low during boot configuration and their state is recorded in the Boot Configuration Vector (BCV) field of the BCV register. These reserved bits may be used to pass boot configuration parameters to software. Table 3 Boot Configuration Vector Encoding MDATA[3] MDATA[4] MDATA[6:5] MDATA[7] MDATA[8] MDATA[11:9] MDATA[15:12] 11 of 44 October 5, 2005 RC32365 Logic Diagram The following Logic Diagram shows the primary pin functions of the RC32365. Miscellaneous Signals CLK COLDRSTN RSTN 2 4 6 22 32 MIIMDC MIIMDIO MII0CL MII0CRS MII0RXCLK MII0RXD[3:0] MII0RXDV MII0RXER MII0TXCLK MII0TXD[3:0] MII0TXENP MII0TXER MII1CL MII1CRS MII1RXCLK MII1RXD[3:0] MII1RXDV MII1RXER MII1TXCLK MII1TXD[3:0] MII1TXENP MII1TXER 4 2 BDIRN BOEN[1:0] BWEN[3:0] CSN[5:0] MADDR[21:0] MDATA[31:0] OEN RWN WAITACKN RASN CASN SDCSN[1:0] SDWEN SDCLKOUT SDCLKINP Memory and Peripheral Bus 4 Ethernet RC32365 4 JTAG_TMS EJTAG_TMS JTAG_TRST_N JTAG_TCK JTAG_TDO JTAG_TDI EJTAG / JTAG Signals 4 16 GPIO[15:0] General Purpose I/O PCI Bus PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[1:0] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[1:0] PCIRSTN PCISERRN PCISTOPN PCITRDYN 32 4 SDO SDI SCK Serial I/O 2 VccCore VccI/O Vss VccPLL VssPLL Power/Ground 2 Figure 1 RC32365 Logic Diagram 12 of 44 October 5, 2005 RC32365 AC Timing Definitions Below are examples of the AC timing characteristics used throughout this document. Tlow Tper clock Tdo Output signal 1 Tzd Output signal 2 Tsu Input Signal 1 Tpw Signal 1 Signal 2 Signal 3 Tskew Thld Tdz Tdo Tjitter Trise Tfall Thigh Figure 2 AC Timing Definitions Waveform Symbol Tper Tlow Thigh Trise Tfall Tjitter Tdo Tzd Tdz Tsu Thld Tpw Tslew X(clock) Tskew Clock period. Clock low. Amount of time the clock is low in one clock period. Definition Clock high. Amount of time the clock is high in one clock period. Rise time. Low to high transition time. Fall time. High to low transition time. Jitter. Amount of time the reference clock (or signal) edge can vary on either the rising or falling edges. Data out. Amount of time after the reference clock edge that the output will become valid. The minimum time represents the data output hold. The maximum time represents the earliest time the designer can use the data. Z state to data valid. Amount of time after the reference clock edge that the tri-stated output takes to become valid. Data valid to Z state. Amount of time after the reference clock edge that the valid output takes to become tri-stated. Input set-up. Amount of time before the reference clock edge that the input must be valid. Input hold. Amount of time after the reference clock edge that the input must remain valid. Pulse width. Amount of time the input or output is active for asynchronous signals. Slew rate. The rise or fall rate for a signal to go from a high to low, or low to high. Timing value. This notation represents a value of ‘X’ multiplied by the clock time period of the specified clock. Using 5(CLK) as an example: X = 5 and the oscillator clock (CLK) = 25MHz, then the timing value is 200. Skew. The amount of time two signal edges deviate from one another. Table 4 AC Timing Definitions 13 of 44 October 5, 2005 RC32365 Clock Parameters 15. The values given below are based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 14 and Parameter PCLK1 CLK2,3 Symbol Frequency Frequency Tper_5a Thigh_5a, Tlow_5a Trise_5a, Tfall_5a Tjitter_5a Reference Edge none none 150MHz Min 100 50 13.3 40 — — Max 150 75 20 60 3.0 ± 250 Units MHz MHz ns % of Tper_5a ns ps Timing Diagram Reference See Figure 3 Table 5 RC32365 Clock Parameters 1. The CPU pipeline clock (PCLK) speed is selected during cold reset by the boot configuration vector (see Table 3). be less than or equal to 1/2 CLK frequency. PCI clock (PCICLK) frequency must be less than or equal to two times CLK. 2. Ethernet clock (MIIxRXCLK and MIIxTXCLK) frequency must 3. Tper_5a CLK Tjitter_5a Tjitter_5a Thigh_5a Tlow_5a Trise_5a Tfall_5a Figure 3 Clock Parameters Waveform 14 of 44 October 5, 2005 RC32365 AC Timing Characteristics The values given below are based on systems running at recommended operating supply voltages and temperatures as shown in Tables 14 and 15. Signal Reset and System COLDRSTN 2 Symbol Reference Edge 150MHz Min Max Unit Conditions Timing Diagram Reference Tpw_6a1 Trise_6a none 110 — — 5.0 9.0 — — 2(CLK) 2(CLK) ms ns ns ns ns ns ns ns Cold reset Cold reset Cold reset Cold reset Cold reset Cold reset Warm reset Warm reset See Figures 4 and 5 RSTN (output) RSTN2 (input) Tdo_6b Tpw_6c 1 CLK rising none COLDRSTN rising COLDRSTN falling RSTN falling RSTN rising 2.0 2(CLK) MDATA[15:0] Boot Configuration Vector Thld_6d Tdz_6d1 Tdz_6d1 Tzd_6d1 3.0 — — 3.0 — Table 6 Reset and System AC Timing Characteristics 1. 2. The values for this symbol were determined by calculation, not by testing. RSTN is a bidirectional signal. It is treated as an asynchronous input. 15 of 44 October 5, 2005 RC32365 1 2 3 4 5 6 7 8 CLK SDCLKOUT Trise_6a COLDRSTN Tdo_6b RSTN MDATA[31:0] BDIRN BOEN[1:0] >= 100 ms Tpw_6a 1. 2. 3. 4. 5. 6. 7. 8. COLDRSTN asserted by external logic. RC32365 asserts RSTN, asserts BOEN[0] low, drives BDIRN low, and tri-states the data bus in response. External logic begins driving valid boot configuration vector on the data bus, and the RC32365 starts sampling it. External logic negates COLDRSTN and tri-states the boot configuration vector on MDATA[15:0]. The boot configuration vector must not be tri-stated before COLDRSTN is deasserted. The RC32365 stops sampling the boot configuration vector. The RC32365 starts driving the data bus, MDATA[31:0], deasserts BOEN[0] high, and drives BDIRN high. SYSCLK may be held constant after this point if Hold SYSCLK Constant is selected in the boot configuration vector. RSTN negated by the RC32365. CPU begins executing by taking MIPS reset exception, and the RC32365 starts sampling RSTN as a warm reset input. >=10ms >= 4096 CLK clock cycles >= 4096 CLK clock cycles (RSTN ignored during this period to allow pull-up to drive signal high) Thld_6d Tdz_6d BOOT VECTOR FFFF_FFFF (RSTN sampled) Figure 4 Cold Reset AC Timing Waveform 1 2 3 4 5 CLK COLDRSTN Tdz_6d RSTN Tzd_6d FFFF_FFFF MDATA[31:0] Active Deasserted Mem Control Signals Active >= 4096 CLK clock cycles >= 4096 CLK clock cycles (RSTN ignored during this period to allow pull-up to drive signal high) (RSTN sampled) 1. 2. 3. 4. 5. Warm reset condition caused by either RSTN asserted, write to reset register, or bus transaction timer time-out. The RC32365 asserts RSTN output low in response. The RC32365 tri-states the data bus, MDATA[31:0], and deasserts all memory control signals, such as RASN, CASN, RWN, OEN, etc. The RC32365 deasserts RSTN. The RC32365 starts driving the data bus, MDATA[31:0], again, but does not sample the RSTN input. CPU begins executing by taking a MIPS soft reset exception and also starts sampling the RSTN input again. Figure 5 Warm Reset AC Timing Waveform 16 of 44 October 5, 2005 RC32365 Signal Symbol Reference Edge 150MHz Min Max Unit Conditions Timing Diagram Reference Memory and Peripheral Bus - SDRAM Access MDATA[31:0] Tsu_7a Thld_7a Tdo_7a Tdz_7a 1 SDCLKINP rising SDCLKOUT rising 1.0 1.7 1.2 1.2 1.2 — — 6.0 7.0 8.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 2.5 6.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns See Figures 6 and 7 Tzd_7a1 MADDR[20:2] RASN CASN SDWEN SDCSN[1:0] BDIRN BOEN[1:0] BWEN[3:0] SDCLKINP SDCKENP Tdo_7b Tdo_7c Tdo_7d Tdo_7e Tdo_7f Tdo_7g Tdo_7h Tdo_7i Tdelay_7k Tdo_7l SDCLKOUT rising SDCLKOUT rising SDCLKOUT rising SDCLKOUT rising SDCLKOUT rising SDCLKOUT rising SDCLKOUT rising SDCLKOUT rising SDCLKOUT rising SDCLKOUT rising 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 0.0 2.0 See Figures 6 and 8 Table 7 Memory and Peripheral Bus AC Timing Characteristics 1. The values for this symbol were determined by calculation, not by testing. 17 of 44 October 5, 2005 RC32365 CLK SDCLKOUT Tdo_7b MADDR[21:0] Addr Tdo_7i BWEN[3:0] 1111 BE's Tdo_7c, 7d, and 7e CMD[2:0]* NOP READ Tdo_7f SDCSN[1:0] 11 Chip-Sel Tdo_7g BDIRN Tdo_7h BOEN[1:0] 11 Tdz_7a MDATA[31:0] Buffer Enables Tsu_7a Thld_7a Data RC32365 samples read data SDCLKINP * NOTE: CMD[2:0] = {RASN, CASN, SDWEN} Tdo_7h 11 Tzd_7a 11 Tdo_7g NOP 1111 SDRAM CAS Latency Tdelay_7k Figure 6 Memory and Peripheral Bus AC Timing Waveform - SDRAM Read Access 18 of 44 October 5, 2005 RC32365 CLK SDCLKOUT Tdo_7b MADDR[21:0] Tdo_7i BWEN[3:0] 1111 BE's Tdo_7c, 7d, and 7e CMD[2:0]* NOP Tdo_7f SDCSN[1:0] 11 Chip-Sel Tdo_7g BDIRN Tdo_7h BOEN[1:0] 11 Buff Enable Tdo_7a MDATA[31:0] Data 11 11 WRITE NOP 1111 Addr SDRAM samples write data * NOTE: CMD[2:0] = {RASN, CASN, SDWEN} Figure 7 Memory and Peripheral Bus AC Timing Waveform - SDRAM Write Access 19 of 44 October 5, 2005 RC32365 Vcc SDCLKOUT Tdelay_7k SDCLKINP pull-up RSTN RC32365 COLDRSTN CLK Memory Bus external buffer SDRAM SRAM, EPROM, etc. Figure 8 SDCLKOUT - SDCLKINP Relationship Signal Symbol Reference Edge 150MHz Min Max Unit Conditions Timing Diagram Reference Memory and Peripheral Bus1 — Device Access MDATA[31:0] Tsu_8a Thld_8a Tdo_8a Tdz_8a2 Tzd_8a2 MADDR[21:0] MADDR[25:22] CSN[5:0] RWN OEN BWEN[1:0] BDIRN BOEN[1:0] WAITACKN3 Tdo_8b Tdo_8c Tdo_8d Tdo_8e Tdo_8f Tdo_8g Tdo_8h Tdo_8i Tsu_8j Thld_8j Tpw_8j2 none CLK rising CLK rising CLK rising CLK rising CLK rising CLK rising CLK rising CLK rising CLK rising CLK rising 2.5 1.0 2.0 2.0 2.0 2.0 3.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 0.5 2(CLK) — — 6.5 9.5 10.5 6.5 7.5 6.5 6.5 6.5 6.5 6.5 6.5 — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns See Figures 9 and 10 Table 8 Memory and Peripheral Bus AC Timing Characteristics — Device Access (Part 1 of 2) 20 of 44 October 5, 2005 RC32365 Reference Edge CLK rising CLK rising CLK rising CLK rising 150MHz Min 3.0 3.0 3.0 3.0 Max 7.5 7.5 7.5 7.5 Timing Diagram Reference See Figures 9 and 10 (cont.) Signal CEN14, CEN24 REGN 4 Symbol Tdo_8k Tdo_8l Tdo_8m Tdo_8n Unit ns ns ns ns Conditions IORDN4 IOWRN4 Table 8 Memory and Peripheral Bus AC Timing Characteristics — Device Access (Part 2 of 2) 1. The RC32365 provides bus turnaround cycles to prevent bus contention when going from a read to write and write to read. For example, there are no cycles where an external device and the RC32365 are both driving. See Chapter 6, Device Controller, in the RC32365 User Reference Manual. 2. The values 3. 4. for this symbol were determined by calculation, not by testing. WAITACKN must meet the setup and hold times if it is synchronous or the minimum pulse width if it is asynchronous. CEN1, CEN2, REGN, IORDN, and IOWRN are alternate functions of GPIO[12:8]. CLK Tdo_8b MADDR[21:0] Tdo_8c MADDR[25:22] RWN CSN[5:0] Tdo_8d Addr[25:22] Addr[21:0] Tdo_8d BWEN[3:0] Tdo_8f OEN Tdz_8a MDATA[31:0] Tdo_8h BDIRN Tdo_8i BOEN[1:0] WAITACKN 1111 Tdo_8f Thld_8a Tsu_8a Data RC32365 samples read data Tdo_8i Tzd_8a Tdo_8h Figure 9 Memory and Peripheral Bus AC Timing Waveform - Device Read Access 21 of 44 October 5, 2005 RC32365 CLK Tdo_8b MADDR[21:0] Tdo_8c MADDR[25:22] Tdo_8e RWN Tdo_8d CSN[5:0] Tdo_8g BWEN[3:0] OEN Tdo_8a MDATA[31:0] BDIRN Tdo_8i BOEN[1:0] WAITACKN Data 1111 Byte Enables 1111 Addr[25:22] Addr[21:0] Figure 10 Memory AC and Peripheral Bus Timing Waveform - Device Write Access 22 of 44 October 5, 2005 RC32365 150MHz Min Max Timing Diagram Reference Signal Ethernet1 MIIMDC Symbol Reference Edge Unit Conditions Tper_9a Thigh_9a, Tlow_9a None 53.3 23.0 — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 Mbps 10 Mbps See Figure 11 MIIMDIO Tsu_9b Thld_9b Tdo_9b MIIMDC rising 10.0 1.0 1(ICLK) 3(ICLK) MIIxRXCLK, MIIxTXCLK2 Tper_9c Thigh_9c, Tlow_9c Trise_9c, Tfall_9c None 399.96 140 — 400.4 260 3.0 40.0 26.0 2.0 — — 13 MIIxRXCLK, MIIxTXCLK2 Tper_9d Thigh_9d, Tlow_9d Trise_9d, Tfall_9d None 39.9 14.0 — MIIxRXD[3:0], MIIxRXDV, MIIxRXER MIIxTXD[3:0], MIIxTXENP, MIIxTXER 1. 2. Tsu_9e Thld_9e Tdo_9f MIIxRXCLK rising MIIxTXCLK rising 3.0 2.0 5.0 Table 9 Ethernet AC Timing Characteristics There are two MII interfaces and the timing is the same for each. “x” represents interface 0 or 1 (For example, MIIxRXCLK can be either MII0RXCLK or MII1RXCLK). The ethernet clock (MIIxRXCLK and MIIxTXCLK) frequency must be equal to or less than 1/2 CLK (MIIxRXCLK and MIIxTXCLK 0.6(VccI/O) 0.6(VccI/O) > VOUT > 0.1(VccI/O) VOUT = 0.18(VccI/O) — — — — — IOL(AC) Switching +16(VccI/O) +26.7(VOUT) — VIL VIH Capacitance Leakage CIN I/OLEAK -0.3 0.5(VccI/O) — — μA Table 16 DC Electrical Characteristics Power Consumption Parameter 150MHz Typical IccI/O IccCore Power Dissipation Normal mode Standby mode1 Normal mode Standby mode1 60 710 620 2.07 1.8 Max. 80 750 660 2.2 2.0 mA mA mA W W Unit Conditions CL = 25pF (affects I/O) Ta = 25oC Maximum values use the maximum voltages listed in Table 14. Typical values use the typical voltages listed in Table 14. Table 17 RC32365 Power Consumption 1. RISCore 32300 CPU core enters Standby mode by executing WAIT instructions; however, other logic continues to function. Standby mode reduces power consumption by 0.6 mA per MHz of the CPU pipeline clock, PCLK. 35 of 44 October 5, 2005 RC32365 Power Curve The following graph contains a power curve that shows power consumption at various bus frequencies. T ypical Power Curve 2.9 Power (W @ 3.3v IO & 2.5v core) 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 70 75 80 85 90 95 100 System Bus Speed (MHz) Figure 25 Typical Power Usage Absolute Maximum Ratings Symbol VCCI/O VCCCore VCCPLL Vimin Vi Ta, Industrial Ta, Commercial Tstg 1. Parameter I/O Supply Voltage Core Supply Voltage PLL Supply Voltage Input Voltage - undershoot I/O Input Voltage Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Min1 -0.6 -0.3 -0.3 -0.6 Gnd -40 0 -40 Max1 4.0 3.0 3.0 — VCCI/O+0.6 +85 +70 +125 Unit V V V V V °C °C °C Table 18 Absolute Maximum Ratings Functional and tested operating conditions are given in Table 14. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 36 of 44 October 5, 2005 RC32365 Package Pin-out — 256-Pin CABGA The following table lists the pin numbers and signal names for the RC32365. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 Function MII0RXD[0] MII0RXDV MII0RXER MII0TXCLK MII0TXD[2] MII0CRS VssPLL MII1RXCLK MII1TXD[2] MII1CL JTAG_TCK GPIO[9] GPIO[5] GPIO[3] GPIO[1] MADDR[10] MII0RXD[3] MII0RXD[1] MII0RXCLK MII0TXER MII0TXD[3] MII0CL VccPLL MII1RXDV MII1TXD[3] MII1CRS GPIO[12] GPIO[8] GPIO[4] GPIO[2] MADDR[21] MADDR[20] MIIMDC MIIMDIO 1 1 1 1 1 1 1 1 Alt Pin E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 Function GPIO[15] JTAG_TRST_N JTAG_TDO JTAG_TDI VccCORE VccI/O VccI/O VccI/O VccI/O VccI/O VccI/O VccCORE MADDR[5] MADDR[16] MADDR[17] MADDR[6] GPIO[14] GPIO[13] PCITRDYN PCISTOPN VccCORE VccI/O Vss Vss Vss Vss VccI/O VccCORE MADDR[3] MADDR[14] MADDR[15] MADDR[4] PCIRSTN PCISERRN 1 1 Alt 1 Pin J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 Function PCIGNTN[1] PCIDEVSELN PCIGNTN[0] PCIFRAMEN VccI/O Vss Vss Vss Vss Vss Vss VccI/O SDWEN SDCLKINP BWEN[2] BWEN[3] PCICBEN[1] PCICBEN[2] PCICBEN[0] PCICLK VccI/O Vss Vss Vss Vss Vss Vss VccCORE BWEN[1] RASN CASN BWEN[0] PCIAD[16] PCIAD[1] Alt Pin N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 Function PCIAD[4] PCIAD[20] PCIAD[19] PCIAD[11] PCIAD[13] PCIAD[15] BOEN[0] CSN[2] CSN[3] RWN MDATA[1] MDATA[3] MDATA[12] MDATA[30] MDATA[11] MDATA[27] PCIAD[5] PCIAD[21] PCIAD[23] PCIAD[10] PCIAD[28] PCIAD[30] BDIRN CSN[1] CSN[4] WAITACKN MDATA[17] MDATA[19] MDATA[5] MDATA[9] MDATA[10] MDATA[26] PCIAD[6] PCIAD[7] Alt Table 19: 256-pin CABGA Package Pin-Out (Part 1 of 2) 37 of 44 October 5, 2005 RC32365 Pin C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 Function MII0RXD[2] MII0TXENP MII0TXD[1] MII1RXD[3] MII1RXD[0] MII1RXER MII1TXENP MII1TXD[0] EJTAG_TMS GPIO[10] GPIO[6] GPIO[0] MADDR[9] MADDR[19] SDI COLDRSTN SDO SCK MII0TXD[0] MII1RXD[2] MII1RXD[1] MII1TXER MII1TXCLK MII1TXD[1] JTAG_TMS GPIO[11] GPIO[7] MADDR[7] MADDR[18] MADDR[8] 1 1 1 1 1 Alt Pin G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 Function PCIPERRN PCIREQN[0] VccCORE Vss Vss Vss Vss Vss Vss VccI/O MADDR[1] MADDR[12] MADDR[13] MADDR[2] PCIPAR PCIREQN[1] PCILOCKN PCIRDYN VccI/O Vss Vss Vss Vss Vss Vss VccI/O SDCSN[0] SDCSN[1] MADDR[11] MADDR[0] Alt Pin L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 Function PCIAD[0] PCICBEN[3] VccCORE VccI/O Vss Vss Vss Vss VccI/O VccCORE CLK SDCLKOUT MDATA[15] MDATA[31] PCIAD[18] PCIAD[3] PCIAD[2] PCIAD[17] VccCORE VccI/O VccI/O VccI/O VccI/O VccI/O VccI/O VccCORE MDATA[14] MDATA[13] MDATA[28] MDATA[29] Alt Pin R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Function PCIAD[24] PCIAD[25] PCIAD[27] PCIAD[29] PCIAD[31] BOEN[1] OEN MDATA[16] MDATA[18] MDATA[20] MDATA[21] MDATA[7] MDATA[24] MDATA[25] PCIAD[22] PCIAD[8] PCIAD[9] PCIAD[26] PCIAD[12] PCIAD[14] RSTN CSN[0] CSN[5] MDATA[0] MDATA[2] MDATA[4] MDATA[6] MDATA[22] MDATA[23] MDATA[8] Alt Table 19: 256-pin CABGA Package Pin-Out (Part 2 of 2) 38 of 44 October 5, 2005 RC32365 RC32365 Power Pins VccI/O E6 E7 E8 E9 E10 E11 F6 F11 G12 H5 H12 VccI/O J5 J12 K5 L6 L11 M6 M7 M8 M9 M10 M11 Table 20 RC32365 Power Pins VccCore E5 E12 F5 F12 G5 K12 L5 L12 M5 M12 VccPLL B7 RC32365 Ground Pins Vss F7 F8 F9 F10 G6 G7 G8 G9 G10 G11 H6 Vss H7 H8 H9 H10 H11 J6 J7 J8 J9 J10 J11 Table 21 RC32365 Ground Pins Vss K6 K7 K8 K9 K10 K11 L7 L8 L9 L10 VssPLL A7 39 of 44 October 5, 2005 RC32365 Alternate Pin Functions Pin C14 A15 B14 A14 B13 A13 C13 D13 B12 A12 C12 D12 B11 F2 F1 E1 Primary GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] Alt #1 U0SOUT U0SINP MADDR[22] MADDR[23] MADDR[24] MADDR[25] N/A SDCKENP CEN1 CEN2 REGN IORDN IOWRN PCIREQN[2] PCIGNTN[2] PCIMUNITN Table 22 Alternate Pin Functions 40 of 44 October 5, 2005 RC32365 RC32365 Pinout — Top View 1 A B VccPLL 2 3 4 5 6 7 VssPLL 8 9 10 11 12 13 14 15 16 C D E F G H J K L M N P R T Vss (Ground) VccI/O (Power) VccCore (Power) 41 of 44 October 5, 2005 RC32365 Package Drawing - 256-pin CABGA 42 of 44 October 5, 2005 RC32365 Package Drawing - page two 43 of 44 October 5, 2005 RC32365 Ordering Information 79RCXX Product Type YY Operating Voltage XXXX Device Type 999 Speed A Package A Temp range/ Process Blank I BC BCG 150 Commercial Temperature (0°C to +70°C Ambient) Industrial Temperature (-40° C to +85° C Ambient) 256-pin CABGA 256-pin Green CABGA 150 MHz Pipeline Clk 365 Integrated Core Processor T 79RC32 2.5V +/-5% Core Voltage 32-bit Embedded Microprocessor Valid Combinations 79RC32T365 - 150BC 79RC32T365 - 150BCG 79RC32T365 - 150BCI 79RC32T365 - 150BCGI 256-pin CABGA package, Commercial Temperature 256-pin CABGA package, Commercial Temperature (Green) 256-pin CABGA package, Industrial Temperature 256-pin CABGA package, Industrial Temperature (Green) CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: rischelp@idt.com phone: 408-284-8208 44 of 44 October 5, 2005