Preliminary Datasheet, Version 1.2, Jan 2010
EICEDRIVER®
2ED020I12FA Dual IGBT Driver IC
Power Management & Drives
Never
stop
thinking.
2ED020I12FA Revision History: Previous Version: Page 2010-09-20 1.1 Version 1.2
Subjects (major changes since 1.1)
Edition 2010-09-20 Published by Infineon Technologies AG, Campeon 1-12, 85579 Neubiberg, Germany © Infineon Technologies AG 2010. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
EICEDRIVER®
2ED020I12FA
Dual IGBT Driver IC
Product Highlights
• • • • • Coreless transformer isolated driver Galvanic Insulation Integrated protection features Suitable for operation at high ambient temperature Automotive Qualified (pending)
Features
• • • • • Dual channel isolated IGBT Driver For 600V/1200V IGBTs 2A rail-to-rail output Vcesat-detection Active Miller Clamp
Typical Application
• • • • AC and Brushless DC Motor Drives High Voltage DC/DC-Converter UPS-Systems Welding
VCC2HS VCC1HS DESATHS INHS+, INHS-, /RSTHS /FLTHS, RDYHS
EiceDRIVER TM 2ED020I12FA
High Side
OUTHS CLAMPHS GND2HS VEE2HS
CPU VCC1LS VCC2LS
Low Side
INLS+, INLS-, /RSTLS /FLTLS, RDYLS DESATLS
OUTLS CLAMPLS
GND1
GND2LS
VEE2LS
Figure 1:
Typical Application
Type 2ED020I12FA Preliminary Datasheet
Gate drive current +/- 2A 3
Package PG-DSO-36/32-1 Version 1.2, 2010-09-20
EICEDRIVER® 2ED020I12FA
Preliminary Datasheet
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1 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.4 2.5 2.5.1 2.5.2 2.6 3 3.1 3.2 4 4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 5 5.1 5.2 5.3 6 7
Block Diagram and Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READY status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 External Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insulation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complies with DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation . . . . . . . . . . . . . . . . . . . . . . Complies with UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 18 18 19 19 19 21 21 21 23 23 24 24 24 24
Timing Diagramms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Block Diagram and Application
1
Block Diagram and Application
GND1 1
2V
36 VEE2HS
0
INHS+ 2 INHS- 3
&
0
∆t
0
35 CLAMPHS LOGIC TX RX LOGIC
VEE 2HS VCC2HS
/RSTHS
∆t
34 OUTHS 33 VCC2HS
R DY_ LOOP
High Side
RDYHS 4 /FLTHS 5 /RSTHS 6
/FLTHS UVLO UVLO
VEE2HS
32 GND2HS 31 VEE2HS LOGIC RX TX LOGIC
DESAT
VCC1HS 7 GND1 8 NC 9 NC 10 GND1 11 INLS+ 12
0
K3
I3
30 DESATHS
9V R
29 not existing
GND2HS
28 not existing 27 not existing
2V
26 not existing 25 CLAMPLS
&
0
∆t
0
/RSTLS
LOGIC
∆t
TX
RX LOGIC
RDY_LOOP
Low Side
INLS- 13 RDYLS 14 /FLTLS 15 /RSTLS 16
VEE2LS VCC2LS
24 VEE2LS 23 OUTLS
/FLTLS UVLO UVLO
VEE 2LS
22 VCC2LS 21 GND2LS
LOGIC VCC1LS 17 GND1 18
RX
TX
LOGIC
DESAT
K3
9V
I3 R
20 DESATLS 19 VEE2LS
GND2LS
Figure 1:
Block Diagram 2ED020I12FA
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Block Diagram and Application
+5V SGND INHS RDY FLT RS
VCC1HS
G ND1 INHS+ INHSRDYHS /FLTHS /RSTHS VCC1LS
VCC2HS DESATHS OUTHS CLAMPHS GND2HS VEE2HS VCC2LS DESATLS OUTLS CLAMPLS GND2LS VEE2LS
+15V_2
-8V_2 +15V_1
INLS
INLS+ INLSRDYLS / FLTLS / RSTLS
-8V_1
2ED020I12FA
Figure 2: Application Example
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Functional Description
2
2.1
Functional Description
Introduction
The 2ED020I12FA is an advanced IGBT dual gate driver that can be also used for driving power MOS devices. Control and protection functions are included to make possible the design of high reliability systems. The device consists of two galvanic separated driver. The input can be directly connected to a standard 5V DSP or microcontroller with CMOS in/output and the output driver are connected to the high side and low side switch. The rail-to-rail driver outputs enables the user to provide easy clamping of the IGBTs gate voltage during short circuit of the IGBT. So an increase of short circuit current due to the feedback via the Miller capacitance can be avoided. Further, a rail-torail output reduces power dissipation. The device also includes IGBT desaturation protection with FAULT status outputs. Two READY status outputs reports if the device is supplied and operates correctly.
2.2 2.2.1
Internal Protection Features Undervoltage Lockout (UVLO)
To ensure correct switching of IGBTs the device is equipped with undervoltage lockout for all driver outputs as well as for input section. If the power supply voltage VVCC1xx of the input section drops below VUVLOL1 a turn-off signal is sent to the output driver before power-down. The IGBT is switched off and the signals at INxx+ and INxx- are ignored as long as VVCC1xx reaches the power-up voltage VUVLOH1 . If the power supply voltage VVCC2xx of the output driver goes down below VUVLOL2 the IGBT is switched off and signals from the input chip are ignored as long as VVCC2xx reaches the power-up voltage VUVLOH2 . VEE2 is not monitored, otherwise negative supply voltage range from 0V to -12V would not be possible.
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Functional Description
2.2.2
• • •
READY status output
The READY outputs shows the status of three internal protection features. UVLO of the input chip UVLO of the output chip after a short delay Internal signal transmission
It is not necessary to reset the READY signal since its state only depends on the status of the former protection signals.
2.2.3
Watchdog Timer
During normal operation the internal signal transmission is monitored by a watchdog timer. If the transmission fails for a given time, the IGBT is switched off and the READY output reports an internal error.
2.2.4
Active Shut-Down
The Active Shut-Down feature ensures a safe IGBT off-state if the output chip is not connected to the power supply.
2.3
Non-Inverting and Inverting Inputs
There are two possible input modes to control the IGBT. At non-inverting mode INxx+ controls the driver output while INxxis set to low. At inverting mode INxx- controls the driver output while INxx+ is set to high. A minimum input pulse width is defined to filter occasional glitches.
2.4
Driver Outputs
The output driver sections uses only MOSFETs to provide a rail-to-rail output. This feature permits that tight control of gate voltage during on-state and short circuit can be maintained as long as the drivers supply is stable. Due to the low internal voltage drop, switching behaviour of the IGBT is predominantly governed by the gate resistor. Furthermore, it reduces the power to be dissipated by the driver.
2.5 2.5.1
External Protection Features Desaturation Protection
A desaturation protection ensures the protection of the IGBT at short circuit. When the DESAT voltage goes up and reaches 9V, the output is driven low. Further, the FAULT output is activated. A programmable blanking time is used to allow enough time for IGBT saturation. Blanking time is provided by a highly precise internal current source and an external capacitor.
2.5.2
Short Circuit Clamping
During short circuit the IGBTs gate voltage tends to rise because of the feedback via the Miller capacitance. An additional protection circuit connected to OUTxx limits this voltage to a value slightly higher than the supply voltage. A current of maximum 500 mA for 10us may be fed back to the supply through one of this paths. If higher currents are expected or a tighter clamping is desired external Schottky diodes may be added.
2.6
RESET
The reset inputs have two functions.
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Functional Description Firstly, /RSTxx is in charge of setting back the FAULT output. If /RSTxx is low longer than a given time , /FLTxx will be reseted at the rising edge of /RSTxx; otherwise, it will remain unchanged. Moreover, it works as enable/shutdown of the input logic.
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Pin Configuration and Functionality
3
3.1
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin Configuration and Functionality
Pin Configuration
Symbol GND1 INHS+ INHSRDYHS /FLTHS /RSTHS VCC1HS GND1 NC NC GND1 INLS+ INLSRDYLS /FLTLS /RSTLS VCC1LS GND1LS VEE2LS DESATLS GND2LS VCC2LS OUTLS VEE2LS CLAMPLS Function Signal ground input side Non inverted driver input high side Inverted driver input high side Ready output high side Inverted fault output high side Inverted reset input high side Positive power supply input high side Signal ground input side Not used, internally connected to Pin 10 Not used, internally connected to Pin 9 Signal ground input side Non inverted driver input low side Inverted driver input lowside Ready output low side Inverted fault output low side Inverted reset input low side Positive power supply input low side Signal ground input side Negative power supply low side driver Desaturation protection low side driver Signal ground low side driver Power supply low side driver Output low side driver Negative power supply low side driver Miller clamping low side driver Pin not existing, cut out Pin not existing, cut out Pin not existing, cut out Pin not existing, cut out DESATHS VEE2HS GND2HS VCC2HS OUTHS CLAMPHS VEE2HS Desaturation protection high side driver Negative power supply high side driver Signal ground high side driver Power supply high side driver Output high side driver Miller clamping high side driver Negative power supply high side driver
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Pin Configuration and Functionality
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND1 INHS+ INHSRDYHS /FLTHS /RSTHS VCC1HS GND1 NC NC GND1 INLS+ INLSRDYLS /FLTLS /RSTLS VCC1LS GND1
VEE2HS CLAMPHS OUTHS VCC2HS GND2HS VEE2HS DESATHS
36 35 34 33 32 31 30
CLAMPLS VEE2LS OUTLS VCC2LS GND2LS DESATLS VEE2LS
25 24 23 22 21 20 19
Figure 3:
PG-DSO 36/32-1/32-1 (top view)
3.2
GND1
Pin Functionality
Common ground connection of the input side. INHS+ Non-inverting driver input (High side) INHS+ control signal for the driver output if INHS- is set to low. (The IGBT is on if INHS+ = high and INHS- = low) A minimum pulse width is defined to make the IC robust against glitches at IN+. An internal Pull-Down-Resistor ensures IGBT Off-State. INHS- Inverting driver input (High side) INHS- control signal for driver output if INHS+ is set to high. (IGBT is on if INHS- = low and INHS+ = high) A minimum pulse width is defined to make the IC robust against glitches at INHS-. An internal Pull-Up-Resistor ensures IGBT Off-State.
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Pin Configuration and Functionality /RSTHS (Reset input High side) Function 1: Enable/shutdown of the input chip. (The IGBT is off if /RSTHS = low). A minimum pulse width is defined to make the IC robust against glitches at INHS-. Function 2: Resets the DESAT-FAULT-state of the chip if /RSTHS is low for a time TRST. An internal Pull-Up-Resistor is used to ensure /FLTHS status output. /FLTHS (Fault output High side) Open-drain output to report a desaturation error of the IGBT (/FLTHS is low if desaturation occurs) RDYHS (Ready status High side) Open-drain output to report the correct operation of the device. (RDYHS = high if both chips are above the UVLO level and the internal chip transmission is faultless) VCC1HS (High side) 5V power supply of the input chip VEE2HS (High side) Negative power supply pins of the output chip. If no negative supply voltage is available, both pins have to be connected to GND2HS. DESATHS (Desaturation High side) Monitoring of the IGBT saturation voltage (VCE) to detect desaturation caused by short circuits. If OUT is high, VCE is above a defined value and a certain blanking time has expired, the desaturation protection is activated and the IGBT is switched off. The blanking time is adjustable by an external capacitor. CLAMPHS (Clamping) Ties the gate voltage to ground after the IGBT has been switched off at a defined voltage to avoid a parasitic switch-on of the IGBT.During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below 2V (related to VEE2HS). GND2HS (High side) Reference ground of the output chip. OUTHS (Driver output High side) Output pin to drive an IGBT. The voltage is switched between VEE2HS and VCC2HS. In normal operating mode Vout is controlled by INHS+, INHS- and /RSTHS. During error mode (UVLO, internal error or DESATHS Vout is set to VEE2HS independent of the input control signals. VCC2HS (High side) Positive power supply pin of the output side. GND1LS (Low side) Ground connection of the input side. INLS+ Non-inverting driver input (Low side) INLS+ control signal for the driver output if INLS- is set to low. (The IGBT is on if INLS+ = high and INLS- = low)
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Pin Configuration and Functionality A minimum pulse width is defined to make the IC robust against glitches at IN+. An internal Pull-Down-Resistor ensures IGBT Off-State. INLS- Inverting driver input (Low side) INLS- control signal for driver output if INLS+ is set to high. (IGBT is on if INLS- = low and INLS+ = high) A minimum pulse width is defined to make the IC robust against glitches at INLS-. An internal Pull-Up-Resistor ensures IGBT Off-State. /RSTLS (Reset input Low side) Function 1: Enable/shutdown of the input chip. (The IGBT is off if /RSTLS = low). A minimum pulse width is defined to make the IC robust against glitches at INLS-. Function 2: Resets the DESAT-FAULT-state of the chip if /RSTLS is low for a time TRST. An internal Pull-Up-Resistor is used to ensure /FLTLS status output. /FLTLS (Fault output Low side) Open-drain output to report a desaturation error of the IGBT (/FLTLS is low if desaturation occurs) RDYLS (Ready status Low side) Open-drain output to report the correct operation of the device. (RDYLS = high if both chips are above the UVLO level and the internal chip transmission is faultless) VCC1LS (Low side) 5V power supply of the input chip VEE2LS (Low side) Negative power supply pins of the output chip. If no negative supply voltage is available, both pins have to be connected to GND2LS. DESATLS (Desaturation Low side) Monitoring of the IGBT saturation voltage (VCE) to detect desaturation caused by short circuits. If OUT is high, VCE is above a defined value and a certain blanking time has expired, the desaturation protection is activated and the IGBT is switched off. The blanking time is adjustable by an external capacitor. CLAMPLS (Clamping) Ties the gate voltage to ground after the IGBT has been switched off at a defined voltage to avoid a parasitic switch-on of the IGBT.During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below 2V (related to VEE2LS). GND2LS (Low side) Reference ground of the output chip. OUTLS (Driver output Low side) Output pin to drive an IGBT. The voltage is switched between VEE2LS and VCC2LS. In normal operating mode Vout is controlled by INLS+, INLS- and /RSTLS. During error mode (UVLO, internal error or DESATLS Vout is set to VEE2LS independent of the input control signals. VCC2LS (Low side) Positive power supply pin of the output side. Preliminary Datasheet 15 Version 1.2, 2010-09-20
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Electrical Parameters
4
4.1
Electrical Parameters
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. Unless otherwise noted all parameters refer to GND1. The specification for all driver signals is valid for HS and LS with out special notic, e.g. IN+ covers INHS+ as well as INLS+. The signals from driver output side are measured with respect to their specific GND2HS or GND2LS. Parameter Positive power supply output side Negative power supply output side Maximum power supply voltage output side (VVCC2-VVEE2) Gate driver output Gate driver high output maximum current Gate driver low output maximum current Maximum short circuit clamping time Positive power supply input side Logic input voltages (IN+,IN-,RST) Opendrain Logic output voltage (FLT) Opendrain Logic output voltage (RDY) Opendrain Logic output current (FAULT) Opendrain Logic output current (RDY) Pin DESAT voltage Junction temperature Storage temperature Power dissipation, per input part Power dissipation, per output part Power dissipation, total Thermal resistance (Input part) Symbol VVCC2 VVEE2 Vmax2 VOUT IOUT IOUT tCLP VVCC1 VLogicIN VFLT VRDY IFLT IRDY VDESAT TJ TS PD, IN PD, OUT PD, tot RTHJA,IN Limit Values min. -0.3 -12 max. 20 0.3 28 Vmax2+0.3 2.4 2.4 V V V V A A us V V V V mA mA
1) 1) 1)
Unit Remarks
VVEE2-0.3
t = 2µs t = 2µs ICLAMP/OUT = 500mA
-0.3 -0.3 -0.3 -0.3
10 6.5 6.5 6.5 6.5 10 10 VVCC2 +0.3 150 150 100 400 1000 375
-0.3 -40 -55
VVEE2 = -8V
°C °C mW mW mW K/W
2) 2) 2) 2)
@TA = 25° @TA = 25° @TA = 25°
@TA = 25°C, PD, IN_HS+LS = 200mW, PD, OUT_HS+LS = 800mW
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Electrical Parameters Thermal resistance (Output part) RTHJA,OUT
110
K/W
2)
@TA = 25°C, PD, IN_HS+LS = 200mW, PD, OUT_HS+LS = 800mW Human Body Model3)
ESD Capability
1) With respect to GND2.
VESD
tbd
kV
2) IC power dissipation is derated linearly at 12mW/°C above 65°C. Thermal performance may change significantly with layout and heat dissipation of components in close proximity. 3) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor).
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Electrical Parameters
4.2
Operating Parameters
Note: Within the operating range the IC operates as described in the functional description. Unless otherwise noted all parameters refer to GND1. The specification for all driver signals is valid for HS and LS with out special notic, e.g. IN+ covers INHS+ as well as INLS+. The signals from driver output side are measured with respect to their specific GND2HS or GND2LS Parameter Positive power supply output side Negative power supply output side Maximum power supply voltage output side (VVCC2-VVEE2) Positive power supply input side Logic input voltages (IN+,IN-,RST) Pin DESAT voltage Ambient temperature Common mode transient immunity
1) With respect to GND2. 2) The parameter is not subject to production test - verified by design/characterization
2)
Symbol VVCC2 VVEE2 Vmax2 VVCC1 VLogicIN VDESAT TA |∆VISO/dt|
Limit Values min. 13 -12 max. 20 0 28 5.5 5.5 VVCC2 125 50
Unit V V V V V V °C
Remarks
1) 1)
4.5 -0.3 -0.3 -40 —
1)
kV/µs @ 500V
4.3
Recommended Operating Parameters
Note: Unless otherwise noted all parameters refer to GND1. The specification for all driver signals is valid for HS and LS with out special notic, e.g. IN+ covers INHS+ as well as INLS+. The signals from driver output side are measured with respect to their specific GND2HS or GND2LS Parameter Positive power supply output side Negative power supply output side Positive power supply input side
1) With respect to GND2.
Symbol VVCC2 VVEE2 VVCC1
Values 15 -8 5
Unit V V V
Remarks
1) 1)
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Electrical Parameters
4.4
Electrical Characteristics
Note: The electrical characteristics involve the spread of values for the supply voltages, load and junction temperatures given below. Typical values represent the median values, which are related to production processes at T = 25°C. Unless otherwise noted all voltages are given with respect to GND. The specification for all driver signals is valid for HS and LS with out special notic, e.g. IN+ covers INHS+ as well as INLS+. The signals from driver output side are measured with respect to their specific GND2HS or GND2LS
4.4.1
Parameter
Voltage Supply.
Symbol VUVLOH1 VUVLOL1 3.5 0.15 VHYS1 VUVLOH2 VUVLOL2 VHYS2 IQ1 0.7 Limit Values min. typ. 4.1 3.8 max. 4.3 V Unit Test Conditions
UVLO Threshold Input Chip UVLO Hysteresis Input Chip (VUVLOH1 - VUVLOL1) UVLO Threshold Output Chip UVLO Hysteresis Output Chip (VUVLOH1 - VUVLOL1) Quiescent Current Input Chip
12.0 11.0 0.9
12.6
V V V V V mA VVCC1 =5V IN+ = High, IN- = Low =>OUT = High, RDY = High, /FLT = High VVCC2 =15V VVEE2 =-8V IN+ = High, IN- = Low =>OUT = High, RDY = High, /FLT = High
10.4
9
7
Quiescent Current Output Chip
IQ2
4
6
mA
4.4.2
Parameter
Logic Input and Output
Symbol VIN+L,VINVIN+H,VIN- 3.5 Limit Values min. typ. max. 1.5 V Unit Test Conditions
IN+,IN-, RST Low Input Voltage IN+,IN-, RST High Input Voltage IN-, RST Input Current IN+ Input Current RDY,FLT Pull Up Current Input Pulse Suppression IN+, INInput Pulse Suppression RST for ENABLE/SHUTDOWN Pulse Width RST for Reseting FLT
L,VRSTL HVRSTH
400 400 400
V uA uA uA VIN-=GND1 VRST =GND1 VIN+=VCC1 VRDY=GND1 VFLT=GND1
IIN-,IRST IIN+, IPRDY, IPFLT TMININ+, TMININTMINRST TRST 30 30 800
100 100 100 40 40
ns ns ns
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Electrical Parameters FLT Low Voltage RDY Low Voltage VFLTL VRDYL
300 300
mV mV
ISINK(FLT) = 5mA ISINK(RDY) = 5mA
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Electrical Parameters
4.4.3
Parameter
Gate Driver
Symbol min. VOUTH1 VOUTH2 VOUTH3 VOUTH4 VCC2-1.2 VCC2-2.5 VCC2-9 -1.5 Limit Values typ. VCC2-0.8 VCC2-2 VCC2-5 VCC2-10 -2 VVEE2+0.04 VVEE2+0.3 VVEE2+2.1 VVEE2+7 2 max. Unit Test Conditions
High Level Output Voltage
High Level Output Peak Current Low Level Output Voltage
IOUTH VOUTL1 VOUTL2 VOUTL3 VOUTL4
VVEE2+0.09 VVEE2+0.85 VVEE2+5.0 — —
V V V V A V V V V A
IOUTH = -20mA IOUTH = -200mA IOUTH = -1A IOUTH = -2A IN+ = High, IN- = Low; OUT = High IOUTL = 20mA IOUTL = 200mA IOUTL = 1A IOUTL = 2A IN+ = Low, IN- = Low; OUT = Low, VVCC2 =15V, VVEE2 =-8V
1,5
Low Level Output Peak Current
IOUTL
4.4.4
Parameter
Short Circuit Clamping
Symbol VCLPout Limit Values min. typ. 0.8 max. 1.3 V IN+=High, IN-=Low, OUT=High IOUT = 500mA (pulse test,tCLPmax=10us) Unit Test Conditions
Clamping voltage (OUT) (VOUT-VVCC2)
4.4.5
Parameter
Dynamic Characteristics
Symbol TPDON TPDOFF TPDISTO TPDONt TPDOFFt TPDISTOt Limit Values min. typ. 170 165 -5 190 195 5 max. 190 185 25 220 225 35 ns ns ns ns ns ns VVCC2 =15V,VVEE2 =-8V CLOAD= 100pF VIN+=50%, VOUT=50% @ 125°C VVCC2 =15V,VVEE2 =-8V CLOAD= 100pF VIN+=50%, VOUT=50% @ 25°C 150 145 -35 160 165 -25 Unit Test Conditions
Input IN+ to output propagation delay ON Input IN+ to output propagation delay OFF Input IN+ to output propagation delay distortion (TPDOFF - TPDON) Input IN+ to output propagation delay ON variation due to temp Input IN+ to output propagation delay OFF variation due to temp Input IN+ to output propagation delay distortion (TPDOFF - TPDON)
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Electrical Parameters Input IN+ to output propagation delay ON variation due to temp Input IN+ to output propagation delay OFF variation due to temp Input IN+ to output propagation delay distortion (TPDOFF - TPDON) Input IN- to output propagation delay OFF Input IN- to output propagation delay distortion (TPDOFF - TPDON) TPDONt TPDOFFt TPDISTOt 135 120 -45 135 145 -565 140 165 -770 120 120 -810 10 165 150 -15 155 165 10 170 195 25 150 150 0 30 195 180 15 750 185 40 990 225 55 990 180 30 60 ns ns ns ns ns ns ns ns ns ns ns ns ns VVCC2 =15V,VVEE2 =-8V CLOAD= 100pF VIN-=50%, VOUT=50% @ 125°C VVCC2 =15V,VVEE2 =-8V CLOAD= 100pF VIN+=50%, VOUT=50% @ -40°C
Input IN- to output propagation delay ON TPDON TPDOFF TPDISTO
VVCC2 =15V,VVEE2 =-8V CLOAD= 100pF VIN+=50%, VOUT=50% @ 25°C
Input IN- to output propagation delay ON TPDONt variation due to temp Input IN- to output propagation delay OFF variation due to temp Input IN- to output propagation delay distortion (TPDOFF - TPDON) Input IN- to output propagation delay OFF Input IN- to output propagation delay distortion (TPDOFF - TPDON) Rise Time TPDOFFt TPDISTOt
Input IN- to output propagation delay ON TPDON TPDOFF TPDISTO TRISE
VVCC2 =15V,VVEE2 =-8V CLOAD= 100pF VIN-=50%, VOUT=50% @ -40°C VVCC2 =15V,VVEE2 =-8V CLOAD= 1nF VL 10% ,VH 90% VVCC2 =15V,VVEE2 =-8V CLOAD= 34nF VL 10% ,VH 90% VVCC2 =15V,VVEE2 =-8V CLOAD= 1nF VL 10% ,VH 90% VVCC2 =15V,VVEE2 =-8V CLOAD= 34nF VL 10% ,VH 90%
200
400
800
ns
Fall Time
TFALL
10
50
90
ns
200
350
600
ns
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Electrical Parameters
4.4.6
Parameter
Desaturation protection
Symbol IDESATC IDESATD VDESAT TDESATleb TDESATOUT TDESATFLT VDESATL TDESATleb Limit Values min. typ. 500 13 9 250 350 max. 550 uA VVCC2 =15V,VVEE2 =-8V VDESAT=2V 450 10 8.3 Unit Test Conditions
Blanking Capacitor Charge Current Blanking Capacitor Discharge Current Desaturation Reference Level Desaturation Filter Time Desaturation Sense to OUT Low Delay Desaturation Sense to FLT Low Delay Desaturation Low Voltage Leading edge blanking
9.5 410 2.25
mA VVCC2 =15V,VVEE2 =-8V VDESAT=6V V ns ns us V ns VVCC2 =15V VVCC2 =15V,VVEE2 =-8V VDESAT=9V VOUT =90% CLOAD= 1nF VFLT =10%; IFLT =5mA IN+=Low, IN-=Low, OUT=Low not subject of production test
0.4 -
0.6 400
0.95 -
4.4.7
Parameter
Active Shut Down
Symbol VACTSD1) Limit Values min. typ. max. 4 V IOUT=-200mA, VCC2 open Unit Test Conditions
Active Shut Down Voltage
1) With reference to VEE2
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Insulation Characteristics
5
5.1
Description
Insulation Characteristics
Complies with DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation
Symbol Characteristic I-IV I-III I-II 55/105/21 2 CLR CPG 8 8 tbd 2.81 CTI VIORM VIOTM VIOSM 175 1420 6000 6000 VPEAK VPEAK V mm mm mm mm Unit
Installation classification per EN 60664-1, Table 1 for rated mains voltage ≤ 150 VRMS for rated mains voltage ≤ 300 VRMS for rated mains voltage ≤ 600 VRMS Climatic Classification Pollution Degree (EN 60664-1) Minimum External Clearance between input and driver section Minimum External Creepage between input and driver section Minimum External Clearance between HS- and LS-driver output Minimum External Creepage between HS- and LS-driver output Minimum Comparative Tracking Index Maximum Repetitive Insulation Voltage Highest Allowable Overvoltage Maximum Surge Insulation Voltage
5.2
Description
Complies with UL 1577
Symbol VISO VISO Characteristic 3750 4500 Unit Vrms Vrms
Insulation Withstand Voltage / 1min Insulation Test Voltage / 1sec
5.3
Reliability
For Qualification Report please contact your local Infineon Technologies office.
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Timing Diagramms
6
Timing Diagramms
IN+ IN/RST OUT
Figure 4: Typical Switching Behavior
IN+
TPDON TPDON TPDON
OUT
VDESAT typ. 9V TDESATleb
TDESATfilter TDESATOUT
TDESATleb
DESAT
/FLT
TDESATFLT
/RST
>TRSTmin
Figure 5:
DESAT Switch-Off Behavior
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Package Outlines
7
Package Outlines
Figure 6:
PG-DSO 36/32-1
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www.infineon.com/gatedriver
Published by Infineon Technologies AG
EICEDRIVER® 2ED020I12FA
Preliminary Datasheet
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