BTS4130QGA

D a t a S h e e t , R e v. 1 . 0 , M ar c h 2 00 8 B TS 41 30 Q G A S m a rt H i g h - S i d e P o w e r S w i t c h A u to m o t i v e P o w e r BTS 4130QGA 1 2 3 3.1 3.2 3.3 4 4.1 4.2 4.3 5 5.1 5.2 5.3 5.3.1 5.4 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.6 7 7.1 7.2 7.2.1 7.2.2 7.3 8 8.1 8.2 9 9.1 10 11 Overview 3 Block Diagram 5 Pin Configuration 6 Pin Assignment 6 Pin Definitions and Functions 6 Voltage and Current Definition 7 General Product Characteristics 8 Absolute Maximum Ratings 8 Functional Range 9 Thermal Resistance 9 Power Stage 10 Output ON-State Resistance 10 Turn ON / OFF Characteristics 10 Inductive Output Clamp 11 Maximum Load Inductance 12 Electrical Characteristics Power Stage 13 Protection Mechanisms 14 Loss of Ground Protection 14 Undervoltage Protection 14 Overvoltage Protection 14 Reverse Polarity Protection 15 Overload Protection 15 Current Limitation 16 Electrical Characteristics Protection Functions 17 Diagnostic Mechanism 18 ST 0/1/2/3 Pin 18 ST0/1/2/3 Signal in Case of Failures 18 Diagnostic in Open Load, Channel OFF 19 ST 0/1 Signal in case of Over Temperature 20 Electrical Characteristics Diagnostic Functions 21 Input Pins 22 Input Circuitry 22 Electrical Characteristics 22 Application Information 23 Further Application Information 23 Package Outlines 24 Revision History 25 Datasheet 2 1.0, 2008-27-02 Smart High-Side Power Switch Four Channel Device BTS4130QGA 1 • • • • • • • • • • • Overview Withstand low Cranking Voltage Fit for 12V Application Four Channel device Very low Stand-by Current CMOS Compatible Inputs Electrostatic Discharge Protection (ESD) Optimized Electromagnetic Compatibility Logic ground independent from load ground Very low Leakage Current from OUT to the load in OFF State Green Product (RoHS compliant) AEC Qualified Basic Features PG-DSO-20-32 Description The BTS4130QGA is a quad channel Smart High-Side Power Switch. It is embedded in a PG-DSO-20-32 package, providing protective functions and diagnostics. The power transistor is built by a N-channel power MOSFET with charge pump. The device is monolithically integrated in Smart technology. It is specially designed to drive relays as well as resistive loads in the harsh automotive environment. Table 1 Parameter Operating voltage range Undervoltage switch OFF at Tj = -40°C Maximum load per channel Over voltage protection Max ON State resistance at Tj = 150°C per channel Nominal load current (one channel active) Minimum current limitation Standby current for the whole device with load Maximum reverse battery voltage Electrical Parameters (short form) Symbol Value 5.5V .... 20V 3.2V 2 * R5W, relays or LED 43V 260mΩ 1.8A 5A 16µA 32V VSOP Vs (USO) PBULB VS (AZ) RDS(ON) IL (nom) IL_SCR IS(off) -Vs(REV) Type BTS4130QGA Data Sheet Package PG-DSO-20-32 3 Marking BTS4130QGA Rev. 1.0, 2008-03-18 BTS4130QGA Overview Diagnostic Feature • • • Open load detection in OFF state Feedback of the thermal shutdown in ON state Diagnostic feedback with open drain output Protection Functions • • • • • • • • Short circuit protection Overload protection Current limitation Thermal shutdown Overvoltage protection (including load dump) with external resistor Reverse battery protection with external resistor Loss of ground and loss of VS protection Electrostatic discharge protection (ESD) Application • All types of resistiv, inductive and capacitive loads Data Sheet 4 Rev. 1.0, 2008-03-18 BTS4130QGA Block Diagram 2 Block Diagram Channel 0 voltage sensor over temperature gate control & charge pump T clamp for inductive load over current switch off VS internal power supply IN0 ESD protection ST 0/1 driver logic open load detection OUT 0 VS Channel 1 T IN1 Control and protection circuit equivalent to channel 0 OUT 1 Channel 2 voltage sensor over temperature gate control & charge pump T clamp for inductive load over current switch off VS internal power supply IN2 ESD protection ST 2/3 driver logic open load detection OUT 2 VS Channel 3 T IN3 Control and protection circuit equivalent to channel 0 OUT 3 GND Block diagram .emf Figure 1 Block diagram for the BTS4130QGA Data Sheet 5 Rev. 1.0, 2008-03-18 BTS4130QGA Pin Configuration 3 3.1 Pin Configuration Pin Assignment Vs 1 20 Vs GND0/1 2 19 Vs IN0 3 18 OUT0 ST 0/1 4 17 OUT1 IN1 5 16 Vs GND2/3 6 15 Vs IN2 7 14 OUT2 ST2/3 8 13 OUT3 IN3 9 12 Vs Vs 10 11 Vs Pinout SO20 shared diag.vsd Figure 2 Pin Configuration 3.2 Pin 1, 10, 11, 12, 15, 16, 19, 20 2 3 4 5 6 7 8 9 Pin Definitions and Functions Symbol VS Function Battery voltage; Design the wiring for the simultaneous maximum short circuit currents from channel 0 and 1 and also for low thermal resistance Ground; Ground connection for channel 0 and 1 Input channel 0; Input signal for channel 0. Activate the channel in case of logic high level Diagnostic feedback; of channel 0/1. Open drain. Input channel 1; Input signal for channel 1. Activate the channel in case of logic high level Ground; Ground connection for channel 2 and 3 Input channel 2; Input signal for channel 2. Activate the channel in case of logic high level Diagnostic feedback; of channel 2/3. Open drain. Input channel 3; Input signal for channel 3. Activate the channel in case of logic high level 6 Rev. 1.0, 2008-03-18 GND0/1 IN0 ST 0/1 IN1 GND2/3 IN2 ST 2/3 IN3 Data Sheet BTS4130QGA Pin Configuration Pin 13 14 17 18 Symbol OUT3 OUT2 OUT1 OUT0 Function Output 3; Protected High side power output channel 3 Output 2; Protected High side power output channel 2 Output 1; Protected High side power output channel 1 Output 0; Protected High side power output channel 0 3.3 Voltage and Current Definition Figure 3 shows all terms used in this data sheet, with associated convention for positive values. VS IIN 0 V IN 0 VIN 1 IST0/1 VST0 /1 IIN 2 IIN 3 IST2/3 ST 0/1 IN2 IN3 ST 2/3 IIN 1 VS IN0 IN1 IS VD S0 VD S1 VD S2 VD S3 OUT0 OUT1 IOU T0 IOU T1 OUT2 OUT3 IOU T2 IOU T3 GND IGN D VOU T0 V OU T1 V OU T2 VOU T3 Voltage and current convention quad shared diag.vsd Figure 3 Voltage and current definition Data Sheet 7 Rev. 1.0, 2008-03-18 BTS4130QGA General Product Characteristics 4 4.1 General Product Characteristics Absolute Maximum Ratings Absolute Maximum Ratings 1) TJ = 25°C; (unless otherwise specified) Pos. Voltages 4.1.1 4.1.2 4.1.3 Parameter Symbol Min. Limit values Max. 43 32 20 V V V – – Unit Conditions VS Reverse polarity Voltage - VS(REV) Supply voltage for short circuit protection Vbat(SC) Supply voltage -0.3 – 0 RECU = 20mΩ, RCable = 16mΩ/m, LCable = 1µH/m, l = 0 or 5m 2) Input pins 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 4.1.11 Voltage at INPUT pins Current through INPUT pins Current through INPUT pins pulsed Current through ST 0/1 pin Current through ST 2/3 pin Load current Power dissipation (DC), all channel active Maximum Switchable energy, single pulse Junction Temperature Dynamic temperature increase while switching Storage Temperature ESD Resistivity IN pin ESD Resistivity ST 0/1, 2/3 pins ESD Resistivity OUT to all other pins shorted see Chapter 6 VIN IIN IIN IST0/1 IST2/3 | IL | -10 -0.3 -5 -5 -5 – – – 16 0.3 5 5 5 IL(LIM) 1.4 76 V mA mA mA mA A W mJ – – Only for testing – – – Status pin Power stage PTOT EAS TA = 85°C, Tj V(OL) H L L X X X L L L1) H L1) H H L L H L H L ST 0/1 ST2/3 H Table 2 gives a quick reference for the logical state of the ST 0/1/2/3 pins during device operation. Device operation Normal operation Open Load channel 0/2 Open Load channel 1/3 Over temperature both channel L H X X L X H Over temp channel 0/2 Over temp channel 1/3 L H X X 1) L if potential at the output exceeds the Openload detection voltage Data Sheet 18 Rev. 1.0, 2008-03-18 BTS4130QGA Diagnostic Mechanism 7.2.1 Diagnostic in Open Load, Channel OFF For open load diagnosis in OFF-state, an external output pull-up resistor (ROL) is recommended. For calculation of the pull-up resistor value, the leakage currents and the open load threshold voltage VOL(OFF) has to be taken into account. Figure 13 gives a sketch of the situation and Figure 14 shows the typical timing diagram. Ileakage defines the leakage current in the complete system, including IL(OFF) (see Chapter 5.4) and external leakages e.g. due to humidity, corrosion, etc... in the application. To reduce the stand-by current of the system, an open load resistor switch SOL is recommended. If the channel is OFF, the output is no longer pulled down by the load and VOUT voltage rises to nearly VS. This is recognized by the device as open load. The voltage threshold is given by VOL(OFF). In that case, the ST 0/1 signal is switched to a logical low VST01(L). Vb a t SOL VS R OL OUT OL comp. ILOFF Ileakage GND R GND Rleakage VOL(OFF) O pen Load in O FF.vsd Figure 13 Open load detection in OFF electrical equivalent circuit IN t V(OL) t V OUT IL ST 0/1 or ST 2/3 V ST(HIGH) VST(LOW) t t Diagnostic In Open load quad shared diag.vs d Figure 14 ST 0/1 in open load condition Data Sheet 19 Rev. 1.0, 2008-03-18 BTS4130QGA Diagnostic Mechanism 7.2.2 ST 0/1 Signal in case of Over Temperature In case of over temperature, the junction temperature reaches the thermal shutdown temperature TjSC. In that case, the ST 0/1 signal is toggling between VST01(L) and VST01(H). Figure 15 gives a sketch of the situation. IN t V OUT ST 0/1 t t T JSC ∆ T JSC TJ t Diagnostic In Overload shared toggling.vs d Figure 15 . Sense signal in overtemperature condition Data Sheet 20 Rev. 1.0, 2008-03-18 BTS4130QGA Diagnostic Mechanism 7.3 Electrical Characteristics Diagnostic Functions Electrical Characteristics: Diagnostics VS = 12 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C Pos. Parameter Symbol Min. Load condition threshold for diagnostic 7.3.1 7.3.2 7.3.3 Open Load detection voltage Status output (open drain) High level; Zener limit voltage Status output (open drain) Low level Status change after positive input slope with open load Status change after positive input slope with overload Status change after negative input slope with open load Limit values Typ. 2.8 – – Max. 4.0 – 0.6 V V V – Unit Conditions VOL(OFF) VST (HIGH) VST (LOW) 1.7 5.4 – ST 0/1 or ST 2/3 pin IST= +1.6mA1), Zener Limit voltage IST= +1.6mA1) Diagnostic timing 7.3.4 7.3.5 7.3.6 7.3.7 tdST(ON_OL) tdST(ON_OvL) tdST(OFF_OL) – 30 – – 10 – – – 20 – 500 20 µs µs µs µs –2) –2) – –2) Status change after negative tdST(OFF) input slope with overtemperature 1) If ground resistor RGND is used, the voltage drop across this resistor has to be added 2) Not subject to production test, specified by design Data Sheet 21 Rev. 1.0, 2008-03-18 BTS4130QGA Input Pins 8 8.1 Input Pins Input Circuitry The input circuitry is CMOS compatible. The concept of the Input pin is to react to voltage transition and not to voltage threshold. With the Schmidt trigger, it is impossible to have the device in an un-defined state, if the voltage on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in an linear or undefined state. The input circuitry is compatible with PWM applications. Figure 16 shows the electrical equivalent input circuitry. The pull down current source ensures the channel is OFF with a floating input. RI II ESD Input circuitry.vsd IN To driver’s logic Figure 16 Input pin circuitry 8.2 Electrical Characteristics Electrical Characteristics: Diagnostics VS = 12 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Typical values are given at Tj = 25°C Pos. Parameter Symbol Min. INput pins characteristics 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 Low level input voltage High level input voltage Input voltage hysteresis Low level input current High level input current Input resistance Limit values Typ. – – 0.2 – 35 4 Max. 1 – – 20 60 6 V V V µA µA kΩ –1) –1) –2) Unit Conditions VIN(L) VIN(H) VIN(HYS) IIN(L) IIN(H) RI – 2.5 – 5 10 2.5 VIN = 0.4V VIN = 5V See Figure 16 1) If ground resistor RGND is used, the voltage drop across this resistor has to be added 2) Not subject to production test, specified by design Data Sheet 22 Rev. 1.0, 2008-03-18 BTS4130QGA Application Information 9 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VDD VDD VBAT Vdd OUT OUT IN IN0 IN1 ST0/1 Vs OUT0 OUT1 Microcontroller (e.g. XC22xx) VDD OUT OUT IN IN2 IN3 ST2/3 OUT2 OUT3 GND GND Figure 17 Application diagram with BTS4130QGA Note: This is a very simplified example of an application circuit. The function must be verified in the real application. 9.1 • Further Application Information For further information you may visit http://www.infineon.com/ Data Sheet 23 Rev. 1.0, 2008-03-18 BTS4130QGA Package Outlines 10 Package Outlines 2.65 max 0.35 x 45˚ +0.09 2.45 -0.2 0.2 -0.1 7.6 -0.2 1) 1.27 0.35 +0.15 2) 20 0.2 24x 11 0.1 0.4 +0.8 10.3 ±0.3 GPS05094 1 12.8 1) 10 -0.2 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side Figure 18 PG-DSO-20-32 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pbfree finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Data Sheet 24 0.23 8˚ ma x Rev. 1.0, 2008-03-18 BTS4130QGA Revision History 11 Version 1.0 Revision History Date 2008-03-18 Changes Creation of the data sheet Data Sheet 25 Rev. 1.0, 2008-03-18 Edition 2008-03-18 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.