BTS5460SF

SPI Power Controller SPOC - BTS5460SF For Advanced Front Light Control Data Sheet Rev. 1.0, 2010-04-12 Automotive Power SPOC - BTS5460SF Table of Contents Table of Contents 1 2 2.1 3 3.1 3.2 4 4.1 4.2 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 6.6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2 9.3 9.4 9.5 9.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Assignment SPOC - BTS5460SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inverse Current Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Current Protection at high VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Current Protection for Short Circuit Type 2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load in OFF-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol 8 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 13 14 15 16 17 17 17 19 20 21 25 26 26 28 28 29 31 31 32 32 33 35 36 37 37 39 40 41 44 46 46 47 48 49 51 53 Data Sheet Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Table of Contents 10 11 12 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Package Outlines SPOC - BTS5460SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Data Sheet 3 Rev. 1.0, 2010-04-12 For Advanced Front Light Control SPI Power Controller SPOC - BTS5460SF 1 Features • • • • • • • • Overview 8 bit serial peripheral interface for control and diagnosis 3.3 V and 5 V compatible logic pins Very low stand-by current Enhanced electromagnetic compatibility (EMC) for bulbs as well as LEDs with increased slew rate Stable behavior at under voltage Device ground independent from load ground Green Product (RoHS-Compliant) AEC Qualified PG-DSO-36-43 Description The SPOC - BTS5460SF is a four channel high-side smart power switch in PG-DSO-36-43 package providing embedded protective functions. It is especially designed to control standard exterior lighting in automotive applications. In order to use the same hardware, the device can be configured to bulb or LED mode for channel 2 and channel 3. As a result, both load types are optimized in terms of switching and diagnosis behavior. It is specially designed to drive exterior lamps up to 65W, 27W and 10W and HIDL. Product Summary Operating Voltage Power Switch Logic Supply Voltage Supply Voltage for Load Dump Protection Maximum Stand-By Current at 25 °C Typical On-State Resistance at Tj = 25 °C channel 0, 1 channel 2, 3 Maximum On-State Resistance at Tj = 150 °C channel 0, 1 channel 2, 3 SPI Access Frequency VBB VDD VBB(LD) IBB(STB) RDS(ON,typ) 4.5 … 28 V 3.0 … 5.5 V 40 V 4.5 µA 3.5 mΩ 11 mΩ 9 mΩ 28 mΩ 5 MHz RDS(ON,max) fSCLK(max) Type SPOC - BTS5460SF Data Sheet Package PG-DSO-36-43 4 Marking BTS5460SF Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Overview Configuration and status diagnosis are done via SPI. The SPI is daisy chain capable. The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be enabled and disabled via SPI commands. An over load and over temperature flag is provided in the SPI diagnosis word. A multiplexed switch bypass monitor provides short-circuit to VBB diagnosis. In OFF state a current source can be switched to the output of one selected channel in order to detect an open load. The SPOC - BTS5460SF provides a fail-safe feature via limp home input pin. The power transistors are built by N-channel vertical power MOSFETs with charge pumps. Protective Functions • • • • • • • • • Reverse battery protection with external components ReversaveTM - Reverse battery protection by self turn on of all channels Short circuit protection Over load protection Thermal shutdown with latch and dynamic temperature sensor Over current tripping Over voltage protection Loss of ground protection Electrostatic discharge protection (ESD) Diagnostic Functions • • • • • • • • Multiplexed proportional load current sense signal (IS) Enable function for current sense signal configurable via SPI High accuracy of current sense signal at wide load current range Current sense ratio (kILIS) configurable for LEDs or bulbs for channel 2 and 3 Very fast diagnosis in LED mode Feedback on over temperature and over load via SPI Multiplexed switch bypass monitor provides short circuit to VBB detection Integrated, in two steps programmable current source for open load in OFF-state detection Application Specific Functions • Fail-safe activation via LHI pin Applications • • • • High-side power switch for 12 V grounded loads in automotive applications Especially designed for standard exterior lighting like high beam, low beam, indicator, parking light and equivalent LEDs Load type configuration via SPI (bulbs or LEDs) for optimized load control Replaces electromechanical relays, fuses and discrete circuits Data Sheet 5 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Block Diagram 2 Block Diagram VBB power supply VDD temperature sensor driver logic gate control & charge pump load current sense IN1 IN2 IN3 clamp for inductive load over current protection channel 0 1 2 3 OUT3 OUT2 OUT1 OUT0 IS LHI CS SCLK SO SI ESD protection current sense multiplexer limp home control switch bypass monitor LED mode control SPI GND Figure 1 Block Diagram SPOC - BTS5460SF Data Sheet 6 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Block Diagram 2.1 Terms Figure 2 shows all terms used in this data sheet. VBB IDD VDD VSO VSI V CS VSCLK VLHI ISO I SI ICS I SCLK I LHI IBB VBB VDD S0 SI CS SCLK OUT1 LHI I L2 OUT2 VOUT2 I IN1 VIN1 VIN2 V IN3 I IS IS VIS I IN2 I IN3 IN1 IN2 IN3 OUT3 I L3 V DS3 VOUT3 VDS2 OUT0 I L0 VDS0 VOUT0 I L1 VDS1 VOUT1 GND IGND Terms_STD.emf Figure 2 Terms In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS0 … VDS3). All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.CL). In SPI register description, the values in bold letters (e.g. 0) are default values. Data Sheet 7 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Pin Configuration 3 3.1 Pin Configuration Pin Assignment SPOC - BTS5460SF (top view) VBB VBB OUT0 OUT0 OUT0 OUT0 OUT3 OUT3 VBB LHI SO SI SCLK CS GND IN1 IN2 IN3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VBB VBB OUT1 OUT1 OUT1 OUT1 OUT2 OUT2 VBB n.c. TEST TEST n.c. n.c. GND IS n.c. VDD Figure 3 Pin Configuration PG-DSO-36-43 Data Sheet 8 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Pin Configuration 3.2 Pin Pin Definitions and Functions Symbol VBB VDD GND IN1 IN2 IN3 OUT0 2) I/O – – – I I I O O O O I I I O O I – – Function Positive power supply for high-side power switch Logic supply (5 V) Ground connection Input signal of channel 1 (high active) Input signal of channel 2 (high active) Input signal of channel 3 (high active) Protected high-side power output of channel 0 Protected high-side power output of channel 1 Protected high-side power output of channel 2 Protected high-side power output of channel 3 Chip select of SPI interface (low active); Integrated pull up Serial clock of SPI interface Serial input of SPI interface (high active) Serial output of SPI interface Current sense output signal Limp home activation signal (high active) not connected, internally not bonded Test pins, internally bonded and pulled down, do not connect Power Supply Pins 1, 2, 9, 28, 35, 36 1) 19 15, 22 16 17 18 Power Output Pins 3, 4, 5, 6 2) 31, 32, 33, 34 29, 30 7, 8 14 13 12 11 21 10 Not connected Pins 20, 23, 24, 27 25, 26 n.c. TEST 2) 2) Parallel Input Pins (integrated pull-down, leave unused pins unconnected) OUT1 OUT2 OUT3 CS SCLK SI SO IS LHI SPI & Diagnosis Pins Limp Home Pin (integrated pull-down, pull-down resistor recommended) 1) All VBB pins have to be connected. 2) All outputs pins of each channel have to be connected. Data Sheet 9 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Electrical Characteristics 4 4.1 Electrical Characteristics Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 to +150 °C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values min. Supply Voltage 4.1.1 4.1.2 4.1.3 4.1.4 Power supply voltage Logic supply voltage Reverse polarity voltage according Figure 26 max. 28 5.5 16 V V V – – Unit Conditions VBB VDD -Vbat(rev) -0.3 -0.3 – Supply voltage for short circuit protection (single VBB(SC) pulse) channel 0, 1 channel 2, 3 0 0 24 24 40 25 12 IL(LIM) 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 Supply voltage for load dump protection with connected loads Current through ground pin Current through VDD pin Load current Maximum energy dissipation single pulse channel 0, 1 channel 2, 3 VBB(LD) IGND IDD IL EAS – – -25 -IL(LIM) TjStart = 25 °C t ≤ 2 min. 2) V RECU = 20 mΩ l = 0 o r 5 m 3) RCable = 6 mΩ/m LCable = 1 µH/m RCable = 16 mΩ/m LCable = 1 µH/m V RI = 2 Ω 4) t = 400 ms mA t ≤ 2 min. mA t ≤ 2 min. A mJ 5) 6) Power Stages – – 180 45 8 5.5 0.75 2.0 Tj(0) = 150 °C IL(0) = 5 A IL(0) = 2 A mA t ≤ 2 min. V – Diagnosis Pin 4.1.10 Current through sense pin IS Input Pins 4.1.11 Voltage at input pins 4.1.12 Current through input pins SPI Pins 4.1.13 Voltage at chip select pin 4.1.14 Current through chip select pin 4.1.15 Voltage at serial input pin 4.1.16 Current through serial input pin 4.1.17 Voltage at serial clock pin 4.1.18 Current through serial clock pin 4.1.19 Voltage at serial out pin Data Sheet 10 IIS VIN IIN -8 -0.3 -0.75 -2.0 -0.3 -2.0 -0.3 -2.0 -0.3 -2.0 -0.3 mA – t ≤ 2 min. – – – – Rev. 1.0, 2010-04-12 VCS ICS VSI ISI VSCLK ISCLK VSO VDD + 0.3 V 2.0 2.0 2.0 mA t ≤ 2 min. mA t ≤ 2 min. mA t ≤ 2 min. VDD + 0.3 V VDD + 0.3 V VDD + 0.3 V SPOC - BTS5460SF Electrical Characteristics Absolute Maximum Ratings (cont’d)1) Tj = -40 to +150 °C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values min. 4.1.20 Current through serial output pin SO Limp Home Pin 4.1.21 Voltage at limp home input pin 4.1.22 Current through limp home input pin Temperatures 4.1.23 Junction temperature 4.1.24 Dynamic temperature increase while switching 4.1.25 Storage temperature ESD Susceptibility 4.1.26 ESD susceptibility HBM OUT pins vs. VBB other pins incl. OUT vs. GND max. 2.0 5.5 0.75 2.0 150 60 150 mA t ≤ 2 min. V – -2.0 -0.3 -0.75 -2.0 -40 – -55 Unit Conditions ISO VLHI ILHI mA – t ≤ 2 min. °C K °C kV – – – HBM 7) – – Tj ∆Tj Tstg VESD -4 -2 4 2 1) Not subject to production test, specified by design. 2) Device is mounted on an FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. 3) In accordance to AEC Q100-012 and AEC Q101-006. 4) RI is the internal resistance of the load dump pulse generator. 5) Over current protection is a protection feature. Operation in over current protection is considered as “outside” normal operating range. Protection features are not designed for continuous repetitive operation. 6) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse 7) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5 kΩ, 100 pF) Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 11 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Electrical Characteristics 4.2 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. 4.2.1 4.2.2 Parameter Junction to Soldering Point Junction to Ambient 1) 1) Symbol Min. Limit Values Typ. – 35 Max. 20 – – – Unit K/W K/W Conditions measured to pin 1, 2, 9, 28, 35, 36 2) RthJSP RthJA 1) Not subject to production test, specified by design. 2) Specified RthJA values is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. Data Sheet 12 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Supply 5 Power Supply The SPOC - BTS5460SF is supplied by two supply voltages VBB and VDD. The VBB supply line is used by the power switches. The VDD supply line is used by the SPI related circuitry and for driving the SO line. A capacitor between pins VDD and GND is recommended as shown in Figure 26. There is a power-on reset function implemented for the VDD logic power supply. After start-up of the logic power supply, all SPI registers are reset to their default values. The SPI interface including daisy chain function is active as soon as VDD is provided in the specified range independent of VBB. First SPI data are the output register values with TER = 1. Specified parameters are valid for the supply voltage range according VBB(nor) or otherwise specified. For the extended supply voltage range according VBB(ext) device functionality (switching, diagnosis and protection functions) are still given, parameter deviations are possible. 5.1 Power Supply Modes The following table shows all possible power supply modes for VBB, VDD and the pin LHI. Power Supply Modes Off Off SPI on 0V 5V 0V – – ✓ – – – Reset Off On via Limp Home Normal operation INx mode without SPI 13.5 V 5V 0V ✓ – ✓ ✓5) ✓6) ✓ 0V 0V ✓ – reset ✓4) – – 2) Limp Home mode with SPI 1) 13.5 V 5V 5V ✓2) ✓ reset3) – – ✓7) VBB VDD LHI Power stage, protection Limp home SPI (logic) Stand-by current Idle current Diagnosis 1) 2) 3) 4) 5) 6) 7) 0V 0V 0V – – – – – – 0V 0V 5V – – – – – – 0V 5V 5V – – ✓ – – – 13.5 V 13.5 V 13.5 V 0V 0V – – reset ✓ – – 0V 5V ✓ ✓ reset – – – 2) SPI read only Channel 1, 2 and/or 3 activated according to the state of INx SPI reset only with applied VBB voltage When INx = low When DCR.MUX = 111b and INx = low When all channels are in OFF-state and DCR.MUX ≠ 111b Current sense disabled in limp home mode 5.1.1 Stand-by Mode and Device Wake-up Mechanisms Stand-by mode is entered as soon as the current sense multiplexer (DCR.MUX) is in default (stand-by) position and all input pins are not set. All error latches are cleared automatically in stand-by mode. As soon as stand-by mode is entered, register HWCR.STB is set. To wake-up the device, the current sense multiplexer (DCR.MUX) is programmed different to default (stand-by) position . The power-on wake up time tWU(PO) has to be considered. Idle mode parameters are valid, when all channels are switched off, but the current sense multiplexer is not in default position, and VDD supply is available. Note: A transition from operation to stand-by mode does not reset the SPI registers. So, if VDD is present and SPI is programmed, a changing to MUX = 111b does not reset the SPI registers. An activation of the channels via the input pin INx will wake up the device with the former SPI register settings. Data Sheet 13 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Supply Activating one of the outputs via the input pins (INx = high) will wake-up the device out of stand-by mode. The power stages are working without VDD supply according to the table above. The output turn-on times will be extended by the stand-by channel wake up time tWU(STCH) as long as no other channel is active. If one channel is active already before channel turn-on times ton (6.5.12) can be considered. Note: In the operation with VDD = 0 V and INx = high a switching off of all input signals will turn the device in standby mode. In stand-by mode the error latches are cleared. Limp home (LHI = high) applied for a time longer than tLH(ac) will wake-up the device out of stand-by mode after the power-on wake up time tWU(PO) and it is working without VDD supply. Channels 1, 2 and 3 can be activated via the input pins INx. The error latches can be cleared by a low-high transition at the according input pin. 5.2 Reset There are several reset trigger implemented in the device. They reset the SPI registers including the over temperature latches to their default values. The power stages will switch off, if they are activated via the SPI register OUT.n. If the power stages are activated via the parallel input pins they are not affected by the reset signals. The ERR-flags are cleared by those reset triggers. The over temperature protection and latches are functional after a reset trigger. Note: During a reset only the channels 1, 2 and 3 can be activated via the according input pins. The input assigned mode is not available during a reset. The first SPI transmission after any kind of reset contains at pin SO the read information from the standard diagnosis, the transmission error bit TER is set. Power-On Reset The power-on reset is released, when VDD voltage level is higher than VDD(PO). The SPI interface can be accessed after wake up time tWU(PO). Reset Command There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As soon as HWCR.RST = 1b, a reset is triggered equivalent to power-on reset. The SPI interface can be accessed after transfer delay time tCS(td). Limp Home Mode The limp home mode will be activated as soon as the pin LHI is set to high for a time longer than tLH(ac). The SPI write-registers are reset with applied VBB voltage. The outputs OUTx can be activated via the input pins also during activated limp home mode. The error latches can be cleared by a low-high transition at the according input pin. For application example see Figure 26. The SPI interface is operating normally, so the limp home register bit LHI as well as the error flags can be read, but any write command will be ignored. Data Sheet 14 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Supply 5.3 Electrical Characteristics Electrical Characteristics Power Supply Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter 5.3.1 Supply voltage range for normal operation power switch Symbol Limit Values min. typ. – – max. 17 281) V V µA – – 5.3.4 Idle current for whole device with loads, all channels off 5.3.5 Logic supply voltage 5.3.6 Logic supply current – – 7 – 4.5 28 – 5.5 mA V µA – Parameter deviations possible 8 4.5 Unit Test Conditions VBB(nor) 5.3.2 Extended supply voltage range for operation VBB(ext) power switch 5.3.3 Stand-by current for whole device with loads IBB(STB) IBB(idle) VDD IDD – 3.0 VDD = 0 V VLHI = 0 V 1) Tj = 25 °C 1) Tj ≤ 85 °C VDD = 5 V DCR.MUX = 110 – – – 5.3.7 Logic idle current 140 280 25 – – – µA IDD(idle) – VCS = VLHI = 0 V RIS = 2.7 kΩ VIS = 0 V fSCLK = 0 Hz fSCLK = 5 MHz VCS = VDD fSCLK = 0 Hz Chip in Standby 5.3.8 Operating current for whole device active LHI Input Characteristics 5.3.9 L-input level at LHI pin 5.3.10 H-input level at LHI pin 5.3.11 L-input current through LHI pin 5.3.12 H-input current through LHI pin Reset 5.3.13 Power-On reset threshold voltage 5.3.14 Power-On wake up time 5.3.15 Stand-by channel wake up time 5.3.16 Limp home acknowledgement time 1) Not subject to production test, specified by design. IGND VLHI(L) VLHI(H) ILHI(L) ILHI(H) VDD(PO) tWU(PO) tWU(STCH) tLH(ac) – 0 1.8 3 10 – – – 5 10 – – 12 40 – – – – 25 0.8 5.5 80 80 2.4 200 200 200 mA V V µA µA V µs µs µs fSCLK = 0 Hz – – 1) VLHI = 0.4 V VLHI = 5 V – 1) 1) 1) Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Data Sheet 15 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Supply 5.4 Command Description HWCR Hardware Configuration Register 1) W/R 2) read write RB 2) 1 1 1 1 ADDR 2) 0 0 3 LED3 LED3 2 LED2 LED2 1 STB RST 0 CL CL 1) Shaded cells not mentioned in this chapter. 2) W/R Write/Read, RB Register Bank, ADDR Address Field RST Bits 1 Type w Description Reset Command 0 1) Normal operation 1 Execute reset command Stand-by 0 Device is awake 1 Device is in stand-by mode STB 1 r 1) Bold letters indicate the default values. Data Sheet 16 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Stages 6 Power Stages The high-side power stages are built by N-channel vertical power MOSFETs (DMOS) with charge pumps. There are four channels implemented in the device. Channels can be switched on via an input pin (please refer to Section 6.2) or via SPI register OUT. 6.1 Output ON-State Resistance The on-state resistance RDS(ON) depends on the supply voltage VBB as well as on the junction temperature Tj. Figure 4 shows those dependencies. The behavior in reverse polarity mode is described in Section 7.5. VBB = 13.5 V 50 45 40 35 Tj = 25 °C 50 Channel 0,1 (bulb) Channel 2,3 (bulb) Channel 2,3 (LED) 45 40 35 RDS(ON) [mΩ ] 30 25 20 15 10 5 0 Channel 0, 1 (bulb) channel 2,3 (bulb) channel 2,3 (LED) RDS(ON) [mΩ ] 30 25 20 15 10 5 0 -50 0 50 T j [°C] 100 150 0 5 10 15 VBB [V] 20 25 30 Figure 4 Typical On-State Resistance 6.2 Input Circuit The outputs of the SPOC - BTS5460SF can be activated either via the SPI register OUT.OUTn or via the dedicated input pins. There are two different ways to use the input pins, the direct drive mode and the assigned drive mode. The default setting is the direct drive mode. To activate the assigned drive mode the register bit ICR.INCG needs to be set. Additionally, there are two ways of using the input pins in combination with the OUT register by programming the ICR.COL parameter. • • ICR.COL = 0b: A channel is switched on either by the according OUT register bit or the input pin. ICR.COL = 1b: A channel is switched on by the according OUT register bit only, when the input pin is high. In this configuration, a PWM signal can be applied to the input pin and the channel is activated by the SPI register OUT. Data Sheet 17 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Stages Figure 5 shows the complete input switch matrix. OUT3 OUT2 OUT1 OUT0 OR & Gate Driver 0 IN1 OR & Gate Driver 1 IN2 OR & Gate Driver 2 IN3 OR OR & Gate Driver 3 INCG COL & InputMatrix_STD .emf Figure 5 Input Switch Matrix The current sink to ground ensures that the input signal is low in case of an open input pin. The zener diode protects the input circuit against ESD pulses. 6.2.1 Input Direct Drive This mode is the default after the device’s wake up and reset. The input pins activate the channels during normal operation (with default setting of bit ICR.INCG), stand-by mode and limp home mode. Channel 0 can be activated only via the SPI-bit OUT.OUT0 in direct drive mode. The inputs are linked directly to the channels according to: Table 1 Input Pin IN1 IN2 IN3 Direct Drive Mode Assigned channel, if ICR.INCG = 0b Channel 1 Channel 2 Channel 3 6.2.2 Input Assigned Drive To activate the assigned drive function the register bit ICR.INCG needs to be set. In this mode all output channels can be activated via the input pins. Channel 2 and 3 are assigned to only one input pin. The following mapping is used: Data Sheet 18 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Stages Table 2 Input Pin IN1 IN2 IN3 Assigned Drive Mode Assigned channel, if ICR.INCG = 1b Channel 0 Channel 1 Channel 2, channel 3 6.3 Power Stage Output The power stages are built to be used in high side configuration (Figure 6). VBB VDS VBB OUT GND VOUT Outputemf . Figure 6 Power Stage Output The power DMOS switches with a dedicated slope, which is optimized in terms of EMC emission. Defined slew rates and edge shaping allow lowest EMC emissions during PWM operation at low switching losses. 6.3.1 Bulb and LED mode Channel 2 and channel 3 can be configured in bulb and LED mode via the SPI registers HWCR.LEDn. During LED mode following parameters are changed for an optimized functionality with LED loads: On-state resistance RDS(ON), switching timings (tdelay(ON), tdelay(OFF), tON, tOFF), slew rates dV/dtON and dV/dtOFF, current protections IL(trip) and current sense ratio kILIS. Data Sheet 19 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Stages 6.3.2 Switching Resistive Loads When switching resistive loads the following switching times and slew rates can be considered. IN / OUTx t ON V OUT 90% of V BB 70% of V BB 70% tOFF tON(rise) tdelay(OFF ) t OFF (f all) t t delay(ON ) dV / dtON 30% of V BB 10% of V BB dV / dt OFF 30% t SwitchOn.emf Figure 7 Switching a Load (resistive) 6.3.3 Switching Inductive Loads When switching off inductive loads with high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to high voltages, there is a voltage clamp mechanism implemented, which limits that negative output voltage to a certain level (VDS(CL) (6.5.2)). See Figure 6 for details. The device provides SmartClamp functionality. To increase the energy capability, the clamp voltage VDS(CL) increases with the junction temperature Tj and load current IL. Please refer also to Section 7.6. The maximum allowed load inductance is limited. 6.4 Inverse Current Behavior During inverse currents (VOUT > VBB) the affected channel stays in ON- or in OFF-state. Furthermore, during applied inverse currents no ERR-flag is set. The functionality of unaffected channels is not influenced by inverse currents applied to other channels (except effects due to junction temperature increase). Influences on the diagnostic function of unaffected channels are possible only for the current sense ratio, please refer to ∆kILIS(IC) (8.5.3). Note: No protection mechanism like temperature protection or current protection is active during applied inverse currents. Inverse currents cause power losses inside the DMOS, which increase the overall device temperature, which could lead to a switch off of the unaffected channels due to over temperature. Data Sheet 20 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Stages 6.5 Electrical Characteristics Electrical Characteristics Power Stages Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Output Characteristics 6.5.1 On-state resistance channel 0, 1 – – channel 2, 3 – – 11 22 – 28 3.5 7 – 9 Symbol Limit Values min. typ. max. Unit Test Conditions RDS(ON) mΩ IL = 7.5 A 1) Tj = 25 °C Tj = 150 °C HWCR.LEDn = 0 IL = 2.6 A 1) Tj = 25 °C Tj = 150 °C HWCR.LEDn = 1 – – 6.5.2 Output clamp channel 0, 1 39 78 – – – – – 100 V 54 55 54 55 µA IL = 0.6 A 1) Tj = 25 °C Tj = 150 °C Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 6 A Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 2 A OUT.OUTn = 0 DCR.MUX = 111 VDS(CL) 32 40 channel 2, 3 32 40 6.5.3 Output leakage current per channel in stand-by channel 0, 1 IL(OFFSTB) – – – – – – – – – – – – 2 10 50 1 4 20 channel 2, 3 Tj = 25 °C 1) Tj = 85 °C 1) Tj = 105 °C Tj = 25 °C 1) Tj = 85 °C 1) Tj = 105 °C µA OUT.OUTn = 0 DCR.MUX ≠ 111 1) 1) 6.5.4 Output leakage current per channel in idle IL(OFFidle) mode channel 0, 1 – – – – – – – – – – – – 60 80 530 45 50 230 channel 2, 3 Tj = 150 °C 1) Tj = 85 °C 1) Tj = 105 °C Tj = 150 °C Tj = 85 °C Tj = 105 °C Data Sheet 21 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Stages Electrical Characteristics Power Stages (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter 6.5.5 Inverse current capability per channel channel 0, 1 channel 2, 3 Input Characteristics 6.5.6 L-input level 6.5.7 H-input level 6.5.8 L-input current 6.5.9 H-input current Symbol Limit Values min. typ. max. Unit Test Conditions A 6 2 – – – – No influences on switching functionality of unaffected channels, kILIS influence according ∆kILIS(IC) (8.5.3) – – 1) 1) -IL(IC) VIN(L) VIN(H) IIN(L) IIN(H) 0 1.8 3 10 – – 12 40 0.8 5.5 80 80 V V µA µA VIN = 0.4 V VIN = 5 V Data Sheet 22 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Stages Electrical Characteristics Power Stages (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Timings 6.5.10 Turn-ON delay to 10% VBB channel 0, 1 channel 2, 3 6.5.11 Turn-OFF delay to 90% VBB channel 0, 1 channel 2, 3 6.5.12 Turn-ON time to 90% VBB including turn-ON delay channel 0, 1 channel 2, 3 Symbol Limit Values min. typ. max. Unit Test Conditions tdelay(ON) – – – 25 20 12 75 50 20 – – – µs 1) VBB = 13.5 V – HWCR.LEDn = 0 HWCR.LEDn = 1 µs 1) tdelay(OFF) – – – – – – VBB = 13.5 V – HWCR.LEDn = 0 HWCR.LEDn = 1 µs tON – – – – – – 100 100 50 VBB = 13.5 V RL = 2.2 Ω DCR.MUX ≠ 111 HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω µs 6.5.13 Turn-OFF time to 10% VBB including turn-OFF delay channel 0, 1 channel 2, 3 tOFF – – – – – – 150 110 50 VBB = 13.5 V RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω 6.5.14 Turn-ON rise time from 10% to 90% VBB channel 0, 1 channel 2, 3 tON(rise) – – – – – – 55 55 11 µs VBB = 13.5 V RL = 2.2 Ω DCR.MUX ≠ 111 HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω µs 6.5.15 Turn-OFF fall time from 90% to 10% VBB channel 0, 1 channel 2, 3 tOFF(fall) – – – – – – 55 55 11 VBB = 13.5 V RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω Data Sheet 23 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Stages Electrical Characteristics Power Stages (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter 6.5.16 Turn-ON/OFF matching channel 0, 1 channel 2, 3 Symbol |tON tOFF| Limit Values min. typ. max. Unit Test Conditions µs VBB = 13.5 V RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω – – – – – – 90 70 50 6.5.17 Turn-ON slew rate 30% to 70% VBB channel 0, 1 channel 2, 3 dV/ dtON 0.2 0.2 0.6 0.7 0.9 2.5 2.0 2.5 6.0 V/µs VBB = 13.5 V RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω V/µs VBB = 13.5 V 6.5.18 Turn-OFF slew rate 70% to 30% VBB channel 0, 1 channel 2, 3 -dV/ dtOFF 0.2 0.2 0.6 0.7 0.9 2.5 2.0 2.5 6.0 RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω 1) Not subject to production test, specified by design. Data Sheet 24 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Power Stages 6.6 Command Description OUT Output Configuration Registers W/R read/write RB 0 5 0 4 0 3 OUT3 2 OUT2 1 OUT1 0 OUT0 Field OUTn n = 3 to 0 Bits n Type rw Description Set Output Mode for Channel n 0 Channel n is switched off 1 Channel n is switched on HWCR Hardware Configuration Register W/R read/write RB 1 1 ADDR 0 3 LED3 2 LED2 1 RST 0 CL Field LEDn n = 3 to 2 Bits n Type rw Description Set LED Mode for Channel n 0 Channel n is in bulb mode 1 Channel n is in LED mode ICR Input and Current Source Configuration Register W/R read/write RB 1 0 ADDR 1 3 COL 2 INCG 1 CSL 0 0 Field INCG Bits 2 Type rw Description Input Drive Configuration 0 Direct drive mode 1 Assigned drive mode Input Combinatorial Logic Configuration 0 Input signal OR-combined with according OUT register bit 1 Input signal AND-combined with according OUT register bit COL 3 rw Data Sheet 25 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Protection Functions 7 Protection Functions The device provides embedded protective functions, which are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered as “outside” normal operating range. Protective functions are neither designed for continuous nor for repetitive operation. 7.1 Over Current Protection The maximum load current IL is switched off in case of exceeding the over current trip level IL(trip) by the device itself. Depending on the total short circuit impedance higher current over shoots may occur. A limited auto-restart function is implemented. The number of restarts is dependent of the VDS voltage. Please refer to following figures for details. normal operation t V DS V DS(Vtrip) over current IN / OUTx t IL I L(trip) Switch off by over current switch off T j(SC) Tj Latch OFF due maximum number of retries reached Restart by dynamic temperature sensor t T j(startn) + ∆T j(res) T j(start2) + ∆ T j(res) Tj(start1) + ∆ Tj(res) Tj(start1) IIS n=1 n = n retry t t ERR * * ERR-flag will be reset by standard diagnosis readout during restart t CL = 1 over load removed CurrentTrippingDeltaT_nretry.emf Figure 8 Over current protection with latch due to reaching maximum number of retries nretry Data Sheet 26 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Protection Functions over current IN / OUTx V DS V DS(Vtrip) normal operation t t IL I L(trip) Switch off by over current switch off T j(SC) T j(startn) + ∆T j(res) Tj Restart by dynamic temperature sensor Latch OFF due to over temperature t T j(start2) + ∆ T j(res) Tj(start1) + ∆ Tj(res) Tj(start1) IIS n=1 n < nretry t t ERR * * ERR-flag will be reset by standard diagnosis readout during restart CL = 1 over load removed t CurrentTrippingDeltaT_OT.emf Figure 9 Over current protection with latch due to reaching over temperature Tj(SC) The ERR-flag will be set during over current shut down. It can be reset by reading the ERR-flag. If the channel is still in over current shut down, the ERR-flag will be set again. During the automatic restart of the channel the ERRflag can be cleared by reading the ERR-flag. It will be set again as soon as the over current protection is activated again. The number of restarts nretry is depending on the VDS voltage according to the following figure and Chapter 7.2. IL(trip) IL(Vtrip) IL n = n retry(LV) n = nretry(MV) no retry 5 10 15 20 VDS CurrentTrippingVsVDS.emf Figure 10 Number of retries and trip levels dependent of VDS The retry latch or over temperature latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately after the command HWCR.CL = 1b. Data Sheet 27 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Protection Functions 7.2 Over Current Protection at high VDS The SPOC - BTS5460SF provides an over current protection for VDS > VDS(Vtrip) (7.9.5). For VDS > VDS(Vtrip) and IL > IL(Vtrip) during turn on the channel switches off and latches immediately. For details please refer to parameter IL(VTRIP) (7.9.4). The current trip level IL(Vtrip) is below the current trip level IL(trip) at VDS = 7V. The ratio between IL(trip) and IL(Vtrip) is defined by the parameter ∆kTR (7.9.6). The over current latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately after the command HWCR.CL = 1b. normal operation t VDS VDS(Vtrip) IN / OUTx high V DS over current t IL I L(Vtrip) t I IS t ERR over load removed CL = 1 t CurrentTrippingHighVDS.emf Figure 11 Over current protection in case of high VDS voltages 7.3 Over Current Protection for Short Circuit Type 2 Protection After activation of the channels without over temperature shutdown and after the delay time tdelay(trip) (7.9.2) the over current protection threshold IL(trip) is reduced to IL(Itrip). The delay time tdelay(trip) is reset by an dynamic temperature sensor or over current shutdown and any INor OUTx. In case of a short circuit to GND event with IL > IL(Itrip) (7.9.3), which occurs in the on state, the channel is switched off and latched immediately. For more details, please refer to the figure Figure 12. The current trip level IL(Itrip) is below the current trip level IL(trip) at VDS = 7V. The ratio between IL(trip) and IL(Itrip) is defined by the parameter ∆kTR (7.9.6). The over current latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately after the command HWCR.CL = 1b. Data Sheet 28 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Protection Functions IN / OUTx IL normal operation over current normal operation t IL(Itrip) t IIS t ERR t > tdelay(trip) over load removed CL = 1 t CurrentTrippingLowVDS .emf Figure 12 Shut Down by Over Current due to Short Circuit Type 2 7.4 Over Temperature Protection Each channel has its own temperature sensor. If the temperature at the channel exceeds the thermal shutdown temperature Tj(SC), the channel will switch off and latch to prevent destruction (also in case of VDD = 0V). In order to reactivate the channel, the temperature at the output must drop by at least the thermal hysteresis ∆Tj and the over temperature latch must be cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately after the command HWCR.CL = 1b. IN / OUTx t IL I L(trip) t Tj(start1) + ∆ Tj(SW) T j(SC) Tj Latch OFF due to over temperature Latch OFF due to over temperature Tj(start1) I IS t t ERR CL = 1 CL = 1 t OverLoad.emf Figure 13 Shut Down by Over Temperature 7.4.1 Dynamic Temperature Sensor Protection Additionally, each channel has its own dynamic temperature sensor. The dynamic temperature sensor improves short circuit robustness by limiting sudden increases in the junction temperature. The dynamic temperature sensor turns off the channel if its sudden temperature increase exceeds the dynamic temperature sensor threshold ∆Tj(SW). The number of automatic reactivations is limited by nretry (7.9.7). If this number of retries is exceeded the channel turns off and latches. The retry latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately after the command HWCR.CL = 1b. For the condition n < nretrythe counter of automatic reactivations will be reset by every low to high transition on the input pin or the bit in SPI register OUT. Please refer to Figure 12 for details. Data Sheet 29 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Protection Functions over load IN / OUTx VDS VDS(Vtrip) normal operation t t IL IL(trip) T j(SC) Tj Switch off by dynamic temperature sensor Restart by dynamic temperature sensor Latch OFF due maximum number of retries reached t T j(startn) + ∆T j(res) Tj(start1) + ∆ Tj(SW) T j(start1) + ∆ T j(res) Tj(start1) I IS ∆ T jSW n=1 n = nretry t t ERR * * ERR-flag will be reset by standard diagnosis readout during restart t CL = 1 over load removed DeltaT_nretry.emf Figure 14 Dynamic Temperature Sensor Operations with latch due to reaching maximum number of retries nretry Data Sheet 30 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Protection Functions over load IN / OUTx VDS VDS(Vtrip) normal operation t t IL IL(trip) T j(SC) T j(startn) + ∆T j(res) Tj Switch off by dynamic temperature sensor Restart by dynamic temperature sensor Latch OFF due to over temperature t Tj(start1) + ∆ Tj(SW) T j(start1) + ∆ T j(res) Tj(start1) I IS ∆ T jSW n=1 n < nretry t t ERR * * ERR-flag will be reset by standard diagnosis readout during restart CL = 1 over load removed t DeltaT_OT.emf Figure 15 Dynamic Temperature Sensor Operations with latch due to reaching over temperature Tj(SC) The ERR-flag will be set during dynamic temperature sensor shut down. It can be reset by reading the ERR-flag. If the channel is still in dynamic temperature sensor shut down, the ERR-flag will be set again. During the automatic restart of the channel the ERR-flag can be cleared by reading the ERR-flag. It will be set again as soon as the dynamic temperature sensor is activated again. 7.5 Reverse Polarity Protection In reverse polarity mode, power dissipation is caused by the intrinsic body diode of each DMOS channel as well as each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected loads.The current through the ground pin, sense pin IS, the logic power supply pin VDD, the SPI pins, input pins and the limp home input pin has to be limited as well (please refer to the maximum ratings listed on Page 10). For reducing the power loss during reverse polarity ReversaveTM functionality is implemented for all channels. They are turned on to almost forward condition in reverse polarity condition, see parameter RDS(REV). Note: No protection mechanism like temperature protection or current protection is active during reverse polarity. 7.6 Over Voltage Protection In the case of supply voltages between VBB(SC) max and VBB(CL) the output transistors are still operational and follow the input or the OUT register. Parameters are not warranted and lifetime is reduced compared to normal mode. In addition to the output clamp for inductive loads as described in Section 6.3, there is a clamp mechanism available for over voltage protection for the logic and all channels. Data Sheet 31 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Protection Functions 7.7 Loss of Ground In case of complete loss of the device ground connections, but connected load ground, the SPOC - BTS5460SF securely changes to or stays in OFF-state. 7.8 Loss of VBB In case of loss of VBB connection in on-state, all inductances of the loads have to be demagnetized through the ground connection or through an additional path from VBB to ground. For example, a suppressor diode is recommended between VBB and GND. Data Sheet 32 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Protection Functions 7.9 Electrical Characteristics Electrical Characteristics Protection Functions Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Over Load Protection 7.9.1 Load current trip level channel 0, 1 Symbol Limit Values min. typ. max. A 71 – 67 29 – 23 7 – 5.5 Over Current Protection 7.9.2 Over current tripping activation time 7.9.3 Load current trip level after tdelay(trip) channel 0, 1 channel 2, 3 17 15.5 3.8 3.8 7.9.4 Load current trip level at high VDS channel 0, 1 channel 2, 3 17 15.5 3.8 3.8 7.9.5 Over current tripping at high VDS activation level – – – – – 1.5 35 30 9 8 – – V – – – – – – 35 30 9 8 A 40 35 78 70 – 90 – – 30 – – 8.5 – – – – 120 – 100 44 – 39 12 – 11 14 78 70 ms A Unit Test Conditions IL(trip) VDS < 7 V Tj = -40 °C 1) Tj = 25 °C Tj = 150 °C HWCR.LEDn = 0 channel 2, 3 Tj = -40 °C 1) Tj = 25 °C Tj = 150 °C HWCR.LEDn = 1 Tj = -40 °C 1) Tj = 25 °C Tj = 150 °C 1) tdelay(trip) 7 IL(Itrip) 40 35 Tj = -40 °C Tj = 150 °C HWCR.LEDn = 0 Tj = -40 °C Tj = 150 °C HWCR.LEDn = 1 Tj = -40 °C Tj = 150 °C 1) IL(Vtrip) Tj = -40 °C Tj = 150 °C HWCR.LEDn = 0 Tj = -40 °C Tj = 150 °C HWCR.LEDn = 1 Tj = -40 °C Tj = 150 °C 1) VDS(Vtrip) 15 1.2 7.9.6 Current trip at VDS = 7 V to current trip at ∆kTR VDS = 20 V ratio 1) Data Sheet 33 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Protection Functions Electrical Characteristics Protection Functions (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Over Temperature Protection 7.9.7 Number of automatic retries at over nretry(LV) current or dynamic temperature sensor shut down at low VDS – 32 – 1) Symbol Limit Values min. typ. max. Unit Test Conditions VDS = 9 V nretry(MV) – 7.9.8 Number of automatic retries at over current or dynamic temperature sensor shut down at medium VDS 7.9.9 Thermal shut down temperature 8 – 1) VDS = 13 V Tj(SC) 7.9.10 Thermal hysteresis of thermal shutdown ∆Tj 7.9.11 Dynamic temperature increase ∆Tj(SW) limitation while switching 7.9.12 Dynamic temperature sensor restart Reverse Battery 7.9.13 On-state resistance channel 0, 1 ∆Tj(res) 150 – – – 175 10 60 20 195 – – – °C K K K mΩ 1) 1) 1) 1) RDS(REV) – – channel 2, 3 – – 14.7 29.5 – – 4.7 9.5 – – 1) VBB = -13.5 V IL = -7.5 A Tj = 25 °C Tj = 150 °C IL = -2.6 A Tj = 25 °C Tj = 150 °C V Over Voltage 7.9.14 Over voltage protection VBB to GND channel 0, 1 VBB(CL) 40 32 40 channel 2, 3 32 40 55 – – – – 70 54 55 54 55 IGND = 5 mA Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 6 A Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 2 A 1) Not subject to production test, specified by design. Data Sheet 34 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Protection Functions 7.10 Command Description HWCR Hardware Configuration Register W/R write RB 1 1 ADDR 0 3 LED 2 LED 1 RST 0 CL Field CL Bits 0 Type rw Description Clear Latch 0 Thermal and over current latches are untouched 1 Command: Clear all thermal and over current latches Standard Diagnosis 7 TER 6 0 5 LHI 4 SBM 3 ERR3 2 ERR2 1 ERR1 0 ERR0 Field ERRn n = 0 to 3 Bits 3:0 Type r Description Error Flag for Channel n 0 No error 1 Error occurred Data Sheet 35 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Diagnosis 8 Diagnosis For diagnosis purpose, the SPOC - BTS5460SF provides a current sense signal at pin IS and the diagnosis word via SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. In OFF-state a current source is able to be switched on for a selected channel with the DCR.CSOL bit. This allows open load / short circuit detection to VBB in OFF-state. The current value can be configured to a low or a high value by programming the bit IECR.CSL. Please refer to parameter IL(OL) (8.5.15). Please refer to Figure 16 for details on diagnosis function: VBB IIS0 latch gate control OR temperature sensor T CSOL IL(OL) over current protection load current sense latch ERR0 OUT3 OUT2 OUT1 OUT0 channel 0 DCR.MUX VBB V DS(SB) DCR. SBM current sense multiplexer IS RIS Diagnosis_STD .emf Figure 16 Block diagram: Diagnosis Data Sheet 36 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Diagnosis For diagnosis feedback at different operation modes, please see following table. Table 3 Operation Modes 1) Input Level Output OUT.OUTn Level VOUT L/0 GND (OFF-state) GND Z VBB Operation Mode Normal Operation (OFF) Short Circuit to GND Thermal shut down Short Circuit to VBB Open Load Inverse Current Normal Operation (ON) Short Circuit to GND Dynamic Temperature Sensor shut down Over Current shut down Thermal shut down Short Circuit to VBB Open Load Inverse Current 1) 2) 3) 4) 5) 6) Current Sense IIS Z Z Z Z Z Z IL / kILIS Error Flag ERRn2) 0 0 0 0 0 0 0 1 1 1 1 5) 6) SBM DCR.SBM 1 1 x 0 03) 04) 0 1 x x x 0 0 0 Z > VBB H/1 (ON-state) ~ VBB ~ GND Z Z Z VBB VBB Z Z Z Z < IL / kILIS Z Z 0 0 0 > VBB L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit x = undefined The error flags are latched until they are transmitted in the standard diagnosis word via SPI If the current sense multiplexer is set to Channel 0 to 3 and DRC.CSOL bit set If the current sense multiplexer is set to Channel 0 to 3 The over current latch off flag is set latched and can be cleared by SPI command HWCR.CL The over temperature flag is set latched and can be cleared by SPI command HWCR.CL 8.1 Diagnosis Word at SPI The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard diagnosis bits ERRn. The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal. The over temperature flags, which cause an overheated channel to latch off, are latched directly at the gate control block. The over current flags, which cause an channel 0 or 1 driving a too high current to switch off, are latched like the over temperature flags. Those latches are cleared by SPI command HWCR.CL. Please note: The over temperature and over current information is latched twice. When transmitting a clear latch command (HWCR.CL), the error flag is cleared during command transmission of the next SPI frame and ready for latching after the third raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CL command will indicate a failure mode at the previously affected channels although the thermal latches have been cleared already. In case of continuous over load, the error flags are set again immediately because of the over load monitoring signal. 8.2 Load Current Sense Diagnosis There is a current sense signal available at pin IS which provides a current proportional to the load current of one selected channel. The selection is done by a multiplexer which is configured via SPI. Data Sheet 37 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Diagnosis Current Sense Signal The current sense signal (ratio kILIS = IL / IS) is provided during on-state as long as no failure mode occurs.The ratio kILIS can be adjusted to the load type (LED or bulb) via SPI register HWCR for channel 2 and 3. The accuracy of the ratio kILIS depends on the load current.Usually a resistor RIS is connected to the current sense pin. It is recommended to use resistors 1.5 kΩ < RIS < 5 kΩ. A typical value is 2.7 kΩ. 60000 50000 kilis Tj = -40 °C kilis typ Tj = 25 °C kilis Tj = 25 °C, 150 °C 40000 k ilis v alue 30000 20000 10000 0 0 1 2 3 4 Load current IL [A] 5 6 7 8 Figure 17 Current Sense Ratio kILIS Channel 0, 1 1) 4000 kilis bulb Tj = 25 °C, 150 °C 3500 3000 2500 k ilis v alue 2000 1500 1000 500 0 0 0.5 1 1.5 2 2.5 3 kilis bulb typ Tj = 25 °C kilis bulb Tj = -40 °C kilis LED Tj = 25 °C, 150 °C kilis LED typ Tj = 25 °C kilis LED Tj = -40 °C 3.5 4 4.5 Load current IL [A] Figure 18 Current Sense Ratio kILIS Channel 2, 3 2) In case of off-state, over current, dynamic temperature sensor shut down (n < nretry), dynamic temperature sensor latch (n = nretry) as well as over temperature, the current sense signal of the affected channel is switched off. To distinguish between over temperature or over current and over load, the SPI diagnosis word can be used. Whereas the over load and dynamic temperature sensor shut down (n < nretry) flag is cleared every time the diagnosis is transmitted. The over temperature, dynamic temperature sensor latch (n = nretry) and over current flag is cleared by a dedicated SPI command (HWCR.CL). 1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in Section 8.5 (Position 8.5.1). 2) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in Section 8.5 (Position 8.5.1). Data Sheet 38 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Diagnosis Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL can be found in Figure 19. OUTx V OUT OFF ON tON OFF tOFF t t IL IIS tsIS(ON) tsIS(LC) tdIS(OFF) t t SenseTiming .emf Figure 19 Timing of Current Sense Signal Current Sense Multiplexer There is a current sense multiplexer implemented in the SPOC - BTS5460SF that routes the sense current of the selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current also can be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please refer to Figure 20. CS DCR.MUX 110 IIS 000 tsIS(EN) 010 tsIS(MUX) 110 tdIS(MUX) t t MuxTiming.emf Figure 20 Timing of Current Sense Multiplexer 8.3 Switch Bypass Diagnosis To detect short circuit to VBB, there is a switch bypass monitor implemented. In case of short circuit between the output pin OUT and VBB in ON-state, the current will flow through the power transistor as well as through the short circuit (bypass) with undefined ratio. As a result, the current sense signal will show lower values than expected by the load current. In OFF-state, the output voltage will stay close to VBB potential which means a small VDS. The switch bypass monitor compares the voltage VDS across the power transistor of that channel, which is selected by the current sense multiplexer (DCR.MUX) with threshold VDS(SB). The result of comparison can be read in SPI register DCR.SBM or in the standard diagnosis. Data Sheet 39 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Diagnosis 8.4 Open Load in OFF-State For performing a dedicated open load in OFF-state detection a current source can be switched in parallel to the DMOS according to the Figure 16. The current source current can be programmed in two steps by the bit ICR.CSL. The following procedure is recommended to use: • • • • Select the dedicated channel with the multiplexer Enable the open load current with the DCR.CSOL bit Read the DCR.SBM or the standard diagnosis Disable the open load current with the DCR.CSOL bit Data Sheet 40 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Diagnosis 8.5 Electrical Characteristics Electrical Characteristics Diagnosis Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Load Current Sense 8.5.1 Current sense ratio channel 0, 1: 0.600 A 1.3 A 2.6 A 4.0 A 7.5 A channel 2, 3 (bulb): 0.300 A 0.600 A 1.3 A 2.6 A 4.0 A channel 2, 3 (LED): 0.050 A 0.150 A 0.300 A 0.600 A 1.0 A 8.5.2 Current sense ratio channel 0, 1: 0.600 A 1.3 A 2.6 A 4.0 A 7.5 A channel 2, 3 (bulb): 0.300 A 0.600 A 1.3 A 2.6 A 4.0 A channel 2, 3 (LED): 0.050 A 0.150 A 0.300 A 0.600 A 1.0 A 165 300 350 385 400 400 440 450 460 500 805 640 580 555 555 990 1240 1400 1540 1540 1670 1750 1800 1830 1840 2690 2300 2100 2110 2110 3120 4420 5030 5130 5490 5840 6140 6350 6430 6480 10960 10010 8660 8240 7710 – – – – – HWCR.LEDn = 0 – – – – – HWCR.LEDn = 1 – – – – – 165 300 350 385 400 400 440 450 460 500 1305 675 580 555 555 990 1240 1400 1540 1540 1670 1750 1800 1830 1840 3710 2710 2210 2110 2110 2190 3990 4690 5130 5490 5840 6140 6350 6430 6480 50010 12510 9210 8510 7710 – – – – – HWCR.LEDn = 0 – – – – – HWCR.LEDn = 1 – – – – – Symbol Limit Values min. typ. max. Unit Test Conditions kILIS Tj = -40 °C kILIS Tj = 25 °C to 150 °C Data Sheet 41 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Diagnosis Electrical Characteristics Diagnosis (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values min. 8.5.3 Current sense drift of unaffected channel ∆kILIS(IC) during inverse current of other channels channel 0, 1 -20 % – -20 % – channel 2, 3 (bulb) -20 % – -20 % – channel 2, 3 (LED) -20 % – -20 % – 8.5.4 Current sense voltage limitation 20 % 20 % 1.1 × V 20 % 20 % 20 % 20 % typ. max. 1) Unit Test Conditions DCR.MUX ≠ 111 IL0, 1 = 7.5 A IL1, 0 (IC) = 7.5 A IL2, 3 (IC) = 2.6 A HWCR.LEDn = 0 IL2, 3 = 2.6 A IL0, 1 (IC) = 7.5 A IL3, 2 (IC) = 2.6 A HWCR.LEDn = 1 IL2, 3 = 0.6 A IL0, 1 (IC) = 7.5 A IL3, 2 (IC) = 2.6 A DCR.MUX = 011 VIS(LIM) 0.9 × VDD 5.5 VDD VDD – mA µA 8.5.5 Maximum steady state current sense output current 8.5.6 Current sense leakage / offset current channel 0, 1 channel 2, 3 8.5.7 Current sense leakage, while diagnosis disabled IIS(MAX) IIS(en) – IL3 = 2 A RIS = 2.7 kΩ 1) VIS = 0 V IL = 0 A DCR.MUX ≠ 111 – – – – – 76 76 1 µA µs DCR.MUX = 110 IIS(dis) – 8.5.8 Current sense settling time after channel tsIS(ON) activation channel 0, 1 channel 2, 3 – – – – – – 150 150 100 µs VBB = 13.5 V RIS = 2.7 kΩ RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 8.5.9 Current sense desettling time after channel deactivation tdIS(OFF) – – – – 25 25 RL = 33 Ω 1) VBB = 13.5 V RIS = 2.7 kΩ HWCR.LEDn = 0 HWCR.LEDn = 1 1) 8.5.10 Current sense settling time after change tsIS(LC) of load current channel 0, 1 channel 2, 3 µs – – – – – – 30 30 30 RIS = 2.7 kΩ IL = 7.5 A to 4.0 A HWCR.LEDn = 0 IL = 2.6 A to 1.3 A HWCR.LEDn = 1 IL = 0.6 A to 0.3 A VBB = 13.5 V Data Sheet 42 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Diagnosis Electrical Characteristics Diagnosis (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter 8.5.11 Current sense settling time after current sense activation 8.5.12 Current sense settling time after multiplexer channel change Symbol Limit Values min. typ. – max. 25 µs – Unit Test Conditions tsIS(EN) RIS = 2.7 kΩ DCR.MUX: 110 -> 000 tsIS(MUX) – – 30 µs RIS = 2.7 kΩ RL0 = 2.2 Ω RL2 = 33 Ω DCR.MUX: 010 -> 000 1) 8.5.13 Current sense deactivation time tdIS(MUX) – – 25 µs RIS = 2.7 kΩ DCR.MUX: 000 -> 110 – IECR.CSL = 0 IECR.CSL = 1 Switch Bypass Monitor 8.5.14 Switch bypass monitor threshold Open load in off current source 8.5.15 Current source in OFF-state 1) Not subject to production test, specified by design. VDS(SB) IL(OL) 1.5 100 3.0 – – – 4 450 7.5 V µA mA Data Sheet 43 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Diagnosis 8.6 Command Description DCR Diagnosis Control Register W/R read write RB 1 1 1 1 ADDR 1 1 3 SBM CSOL 2 1 MUX MUX 0 Output state OUT.OUTn 0 (OFF-state) Field MUX Bits 2:0 Type r/w Description Set Current Sense Multiplexer Configuration 000 IS pin is high impedance 001 IS pin is high impedance 010 IS pin is high impedance 011 IS pin is high impedance 100 IS pin is high impedance 101 IS pin is high impedance 110 IS pin is high impedance 111 Stand-by mode (IS pin is high impedance) Switch Bypass Monitor 1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) Set Current Sense Multiplexer Configuration 000 Current sense of channel 0 is routed to IS pin 001 Current sense of channel 1 is routed to IS pin 010 Current sense of channel 2 is routed to IS pin 011 Current sense of channel 3 is routed to IS pin 100 IS pin is high impedance 101 IS pin is high impedance 110 IS pin is high impedance 111 Stand-by mode (IS pin is high impedance)) Switch Bypass Monitor 1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) SBM 3 r 1 (ON-state) MUX 2:0 r/w SBM 3 r 1) Invalid in stand-by mode Field CSOL Bits 3 Type w Description Current Source Switch for Open Load Detection 0 OFF 1 ON Data Sheet 44 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Diagnosis Standard Diagnosis CS TER 7 0 6 LHI 5 SBM 4 0 3 ERR3 2 ERR2 1 ERR1 0 ERR0 Field ERRn n = 3 to 0 SBM Bits n Type r Description Error flag Channel n 0 normal operation 1 failure mode occurred Switch Bypass Monitor 1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) 5 r 1) Invalid in stand-by mode ICR Input and Current Source Configuration Register W/R read/write RB 1 0 ADDR 1 3 COL 2 INCG 1 CSL 0 0 Field CSL Bits 1 Type rw Description Level for Current Source for Open Load Detection 0 Low level 1 High level Data Sheet 45 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Serial Peripheral Interface (SPI) 9 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability. SO SI CS SCLK time CS MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB SPI.emf Figure 21 Serial Peripheral Interface 9.1 SPI Signal Description CS - Chip Select: The system micro controller selects the SPOC - BTS5460SF by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: • • The requested information is transferred into the shift register. SO changes from high impedance state to high or low state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration, a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK. TER SI OR 1 0 SO SI CS SCLK S SPI SO S TER.emf Figure 22 Combinatorial Logic for TER Flag CS Low to High transition: • Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored. Data from shift register is transferred into the addressed register. • Data Sheet 46 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Serial Peripheral Interface (SPI) SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 9.5 for further information. SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.5 for further information. 9.2 Daisy Chain Capability The SPI of SPOC - BTS5460SF provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 23), in order to build a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain. device 1 SI SO SI device 2 SO SI device 3 SO MO SPI SPI SPI CS CS SCLK SCLK CS MI MCS MCLK Figure 23 Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out occurs at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high (see Figure 24). Data Sheet 47 Rev. 1.0, 2010-04-12 SCLK SPI_DaisyChain .emf SPOC - BTS5460SF Serial Peripheral Interface (SPI) MI MO MCS MCLK time SO device 1 SI device 1 SO device 2 SI device 2 SO device 3 SI device 3 SPI_DaisyChain2.emf Figure 24 Data Transfer in Daisy Chain Configuration 9.3 Timing Diagrams tCS(lead) tCS(lag) tSCLK(P) tSCLK(H) tSCLK(L) 0.7VDD tCS(td) 0.7VDD 0.2VDD CS SCLK tSI(su) tSI(h) 0.2VDD SI tSO(en) tSO(v) tSO(dis) 0.7VDD 0.2VDD SO 0.7VDD 0.2VDD SPI Timing.emf Figure 25 Timing Diagram SPI Access Data Sheet 48 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Serial Peripheral Interface (SPI) 9.4 Electrical Characteristics Electrical Characteristics Serial Peripheral Interface (SPI) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Input Characteristics (CS, SCLK, SI) 9.4.1 L level of pin CS VCS(L) SCLK VSCLK(L) SI VSI(L) 9.4.2 H level of pin CS VCS(H) SCLK VSCLK(H) SI VSI(H) 9.4.3 Pull-up resistor at CS pin 9.4.4 Pull-down resistor at pin SCLK RSCLK SI RSI Output Characteristics (SO) 9.4.5 L level output voltage 9.4.6 H level output voltage 9.4.7 Output tristate leakage current Timings 9.4.8 Serial clock frequency 9.4.9 Serial clock period 9.4.10 Serial clock high time 9.4.11 Serial clock low time 9.4.12 Enable lead time (falling CS to rising SCLK) 0.4* – 0 – 0.2* V Symbol Limit Values min. typ. max. Unit Test Conditions VDD VDD = 4.3 V VDD VDD V VDD = 4.3 V RCS 50 50 120 120 180 180 kΩ kΩ ICS = 100 µA – ISCLK = 100 µA ISI = 100 µA 0 0.4 V – 0.4 V V µA MHz ns ns ns ns ns ns ns ns VSO(L) VSO(H) ISO(OFF) fSCLK tSCLK(P) tSCLK(H) tSCLK(L) tCS(lead) VDD - – -10 0 0 200 333 100 166 100 166 200 333 200 333 200 333 20 33 20 33 – – – – – – – – – – – – – – – – – – – VDD 10 5 3 – – – – – – – – – – – – – – – – ISO = -0.5 mA ISO = 0.5 mA VDD = 4.3 V VCS = VDD 1) 2) 9.4.13 Enable lag time (falling SCLK to rising tCS(lag) CS) 9.4.14 Transfer delay time (rising CS to falling CS) 9.4.15 Data setup time (required time SI to falling SCLK) 9.4.16 Data hold time (falling SCLK to SI) tCS(td) tSI(su) tSI(h) VDD = 4.3 V VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V Data Sheet 49 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Serial Peripheral Interface (SPI) Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter 9.4.17 Output enable time (falling CS to SO valid) 9.4.18 Output disable time (rising CS to SO tri-state) Symbol Limit Values min. typ. – – – – – – max. ns – – 200 333 ns – – – – 200 333 ns 100 166 2) Unit Test Conditions tSO(en) tSO(dis) 9.4.19 Output data valid time with capacitive tSO(v) load VDD = 4.3 V VDD = 3.0 V 2) CL = 20 pF VDD = 4.3 V VDD = 3.0 V 2) CL = 20 pF VDD = 4.3 V VDD = 3.0 V CL = 20 pF 1) Not subject to production test, specified by design. SPI functional test is performed at fSCLK = 5 MHz. 2) Not subject to production test, specified by design. Data Sheet 50 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Serial Peripheral Interface (SPI) 9.5 SPI Protocol 8 Bit CS1) 7 1 0 1 0 0 TER TER TER 0 1 1 6 0 0 1 1 x LHI 0 1 x SBM 0 ADDR 5 0 x ADDR ADDR x x 0 x x ERR3 OUT3 x x ERR2 OUT2 DATA 4 0 x 3 OUT3 x 2 OUT2 x DATA 1 OUT1 x 0 OUT0 0 Write OUT Register SI SI SI SI SI SO SO SO Read OUT Register Write Configuration and Control Registers Read Configuration and Control Registers x x ERR1 OUT1 0 1 ERR0 OUT0 Read Standard Diagnosis Standard Diagnosis Second Frame of Read Command 1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition. Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame. The standard diagnosis can be accessed either by sending the standard diagnosis read command or it is transmitted after each write command. Field W/R RB Bits 7 6 Type w r Description 0 1 Read Write Register Bank 0 Read / write to the OUTx channel 1 Read / write to the other register Transmission Error 0 Previous transmission was successful (modulo 8 clocks received) 1 Previous transmission failed or first transmission after reset Output Control Register of Channel n 0 OFF 1 ON Address Pointer to register for read and write command Data Data written to or read from register selected by address ADDR Diagnosis of Channel n 0 No failure 1 Over temperature, over current (only channel 0 and 1) over load or short circuit 51 Rev. 1.0, 2010-04-12 TER CS r OUTn n = 3 to 0 ADDR DATA ERRn n = 3 to 0 n rw 6:5 4:0 n rw rw r Data Sheet SPOC - BTS5460SF Serial Peripheral Interface (SPI) Field SBM Bits 5 Type r Description Switch Bypass Monitor 1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) Limp Home Enable 2) 0 H-input signal at LHI pin 1 L-input signal at LHI pin LHI 6 r 1) Invalid in stand-by mode 2) Not latching information, read of LHI-status during falling CS Data Sheet 52 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Serial Peripheral Interface (SPI) 9.6 Bit Name OUT Name ICR HWCR DCR Register Overview 7 W/R W/R W/R W/R R W R W 6 RB 0 RB 1 1 1 1 1 0 1 1 1 1 5 5 0 ADDR 1 0 0 1 1 COL LED3 LED3 SBM CSOL 4 4 0 3 3 OUT3 2 2 OUT2 1 1 OUT1 0 0 OUT0 default 1) 00H default1) 0 CL CL 00H 02H 07H - DATA INCG LED2 LED2 CSL STB RST MUX MUX 1) The default values are set after reset. Note: A readout of an unused register will return the standard diagnosis. Field CSL Bits 1 Type rw Description Level for Current Source for Open Load Detection 0 Low level 1 High level Input Drive Configuration 0 Direct drive mode 1 Assigned drive mode Input Combinatorial Logic Configuration 0 Input signal OR-combined with according OUT register bit 1 Input signal AND-combined with according OUT register bit Clear Latch 0 Thermal and over current latches are untouched 1 Command: Clear all thermal and over current latches Reset Command 0 Normal operation 1 Execute reset command Standby Mode 0 Device is awake 1 Device is in Standby mode Set LED Mode for Channel n 0 Channel n is in bulb mode 1 Channel n is in LED mode INCG 2 rw COL 3 rw CL 0 rw RST 1 w STB 1 r LEDn n = 3 to 2 n rw Data Sheet 53 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Serial Peripheral Interface (SPI) Field MUX Bits 2:0 Type rw Description Set Current Sense Multiplexer Configuration in OFF-state 000 IS pin is high impedance 001 IS pin is high impedance 010 IS pin is high impedance 011 IS pin is high impedance 100 IS pin is high impedance 101 IS pin is high impedance 110 IS pin is high impedance 111 Stand-by mode (IS pin is high impedance) Set Multiplexer Configuration in ON-state 000 Current sense of channel 0 is routed to IS pin 001 Current sense of channel 1 is routed to IS pin 010 Current sense of channel 2 is routed to IS pin 011 Current sense of channel 3 is routed to IS pin 100 IS pin is high impedance 101 IS pin is high impedance 110 IS pin is high impedance 111 Stand-by mode (IS pin is high impedance)) Switch Bypass Monitor 1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) Current Source Switch for Open Load Detection 0 OFF 1 ON SBM 3 r CSOL 3 w 1) Invalid in stand-by mode Data Sheet 54 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Application Description 10 Application Description V bat 1 5V W D- OUT 500 Ω 100nF 68nF VDD VBB VCC GPIO GPIO 8kΩ 8kΩ IN1 IN2 IN3 IS OUT0 OUT1 OUT2 OUT3 GND VDD SPI LHI 8k Ω 10kΩ W D- OUT 65W 65W 27W 10W 1kΩ AD 1nF 2.7k Ω µC e . g. X C2 2 6 7 3.9k Ω CS SCLK SO SI SPI 3.9k Ω 3.9k Ω 3.9k Ω GND VSS 10 Ω 2 1 2 For filtering and protec tion purpos es For inc reas ed ISO-puls e robus tnes s Circ uit_STD.emf Figure 26 Application Circuit Example Data Sheet 55 Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Package Outlines SPOC - BTS5460SF 11 Package Outlines SPOC - BTS5460SF 2.65 MAX. 0.35 x 45˚ 7.6 -0.2 2.45 -0.2 0.23 +0.09 0.7 ±0.2 10.3 ±0.3 0.2 -0.1 1) 0.65 0.33 ±0.08 2) 0.1 C 0.17 M C A-B D 36x D A 36 19 Bottom View 19 36 Ejector Mark 1 18 18 1 B 1) 12.8 -0.2 Index Marking Dimensions in mm Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side GPS01089 Figure 27 PG-DSO-36-43 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 56 8˚ MAX. Rev. 1.0, 2010-04-12 SPOC - BTS5460SF Revision History 12 Revision 1.0 Revision History Date 2010-04-12 Changes Initial Data Sheet Data Sheet 57 Rev. 1.0, 2010-04-12 Edition 2010-04-12 Published by Infineon Technologies AG 81726 Munich, Germany © 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.