BTS5566G

Data Sheet, Rev. 1.3, October 2007 SPOC - BTS5566G SPI Power Controller Automotive Power SPI Power Controller SPOC - BTS5566G Table of Contents 1 2 2.1 3 3.1 3.2 4 4.1 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.2 9.3 9.4 9.5 9.6 10 11 12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Assignment SPOC - BTS5566G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 14 15 16 16 16 17 18 20 21 21 22 22 22 22 22 23 24 25 26 26 28 29 31 32 32 33 33 34 36 37 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package Outlines SPOC - BTS5566G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data Sheet 2 Rev. 1.3, 2007-10-30 SPI Power Controller for Advanced Light Control SPOC - BTS5566G 1 Overview The SPOC - BTS5566G is a five channel high-side smart power switch in PG-DSO-36-34 package providing embedded protective functions. It is especially designed to control standard exterior lighting in automotive applications. It is designed to drive lamps up to 3*27W + 2*10W. Configuration and status diagnosis is done via SPI. Additionally, there is a current sense signal available for each channel that is routed via a multiplexer to a single diagnosis pin. The SPOC - BTS5566G provides a fail-safe function via limp home input pin. PG-DSO-36-34 Product Summary Operating Voltage Power Switch Logic Supply Voltage Over Voltage Protection Maximum Stand-By Current at 25 °C On-State Resistance at Tj = 150 ° channel 0, 1 channel 2 channel 3,4 VBB VDD VBB(AZ,min) IBB(OFF) RDS(ON) max 4.5 … 28 V 3.8 … 5.5 V 40 V 3 µA 49 mΩ 64 mΩ 180 mΩ 2 MHz SPI Access Frequency fSCLK(max) Type SPOC - BTS5566G Data Sheet Package PG-DSO-36-34 3 Marking BTS5566G Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Overview Basic Features • • • • • • • • • 8 bit serial peripheral interface (daisy chain capable SPI) for control and diagnostics CMOS compatible parallel input pins for each channel provide straightforward PWM operation Selectable AND- / OR-combination for parallel inputs (PWM control) Very low stand-by current Optimized electromagnetic compatibility (EMC) for bulbs Stable behavior at under voltage Device ground independent from load ground Green Product (RoHS-Compliant) AEC Qualified Protective Functions • • • • • • • • Reverse battery protection with external components Short circuit protection Over load protection Multi step current limitation Thermal shutdown with latch Over voltage protection Loss of ground protection Electrostatic discharge protection (ESD) Diagnostic Functions • • • • • Multiplexed proportional load current sense signals (IS) Enable function for current sense signal configurable via SPI High accuracy of current sense signal at wide load current range Feedback on over temperature and over load via SPI Multiplexed switch bypass monitor provides short circuit to Vbb detection Application Specific Functions • Fail-safe activation via LHI pin and configuration via input pins Applications • • • High-side power switch for 12 V grounded loads in automotive application Especially designed for standard exterior lighting like tail light, brake light, reverse light, parking light, license plate lighting and turn signal indicators Replaces electromechanical relays, fuses and discrete circuits Data Sheet 4 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Overview watchdog fail safe system limp home control limp home control SPOC - BTS5566G 180 mΩ 49 mΩ 49 mΩ 64 mΩ 180 mΩ SPOC - BTS5566G 180 mΩ 64 mΩ 49 mΩ 49 mΩ 180 mΩ BL IND TL RL LIC SPOC RL BL IND TL Application rear .emf Figure 1 Application Example Abbreviations: BL RL TL LIC IND Brake Light (21 W, 27 W) Reverse Light (21 W, 27 W) Tail Light (5 W, 7 W, 10 W) License plate lighting (5 W, 10 W) Indicator / Flasher (21 W, 27 W) Data Sheet 5 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Block Diagram 2 Block Diagram The SPOC - BTS5566G is a five channel high-side power switch in PG-DSO-36-34 package providing embedded protective functions. An 8 bit serial peripheral interface (SPI) is used for configuration and diagnosis. The SPI can be used in daisy chain configuration. The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be enabled and disabled via SPI commands. An over load and over temperature flag is provided in the SPI diagnosis word. A multiplexed switch bypass monitor provides diagnosis at short-circuit to VBB. The power transistors are built by N-channel vertical power MOSFETs with charge pumps. The device is monolithically integrated in SMART SIPMOS technology. VBB power supply IN0 IN1 IN2 IN3 IN4 temperature sensor driver logic gate control & charge pump load current sense clamp for inductive load load current limitation channel 0 OUT4 34 12 OUT3 OUT2 OUT1 OUT0 IS LHI CS SCLK SO SI ESD protection current sense multiplexer limp home control switch bypass monitor PWM control SPI GND Figure 2 Block Diagram SPOC - BTS5566G Data Sheet 6 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Block Diagram 2.1 Terms The following figure shows all terms used in this data sheet. VBB IIN 0 VIN 0 VIN 1 VIN 2 VIN 3 VIN 4 Vdd VSO VSI VC S VSC LK VIS VLH I GND IGN D IIN 1 IIN 2 IIN 3 IIN 4 ID D ISO I SI IC S ISC LK I IS ILH I IBB VBB IN0 IN1 IN2 IN3 IN4 VDD SO SI CS SCLK IS LHI OUT3 OUT2 OUT1 I L1 VD S1 VOU T1 I L2 VD S2 VOU T2 I L3 VD S3 VOU T3 OUT4 I L4 VD S4 VOU T4 OUT0 I L0 VD S0 VOU T0 Figure 3 Terms In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS0 … VDS4). All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.CTL). In SPI register description, the values in bold letters (e.g. 0) are default values. Data Sheet 7 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Pin Configuration 3 3.1 Pin Configuration Pin Assignment SPOC - BTS5566G (top view) VBB GND VDD SO SI SCLK CS IN0 IN1 IN2 IN3 IN4 IS LHI n.c. VBB n.c. VBB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VBB OUT0 OUT0 OUT0 OUT0 OUT1 OUT1 OUT1 OUT1 OUT2 OUT2 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 VBB Figure 4 Pin Configuration PG-DSO-36-34 Data Sheet 8 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Pin Configuration 3.2 Pin Pin Definitions and Functions Symbol VBB VDD GND IN0 IN1 IN2 IN3 IN4 OUT0 OUT1 OUT2 OUT3 OUT4 CS SCLK SI SO IS LHI n.c. I/O Function – – – I I I I I O O O O O I I I O O I – Positive power supply for high-side power switch and limp home block Logic supply (5 V) Ground connection Input signal of channel 0 Input signal of channel 1 Input signal of channel 2 Input signal of channel 3 Input signal of channel 4 Protected high-side power output of channel 0 Protected high-side power output of channel 1 Protected high-side power output of channel 2 Protected high-side power output of channel 3 Protected high-side power output of channel 4 Chip select of SPI interface (low active) Serial clock of SPI interface Serial input of SPI interface Serial output of SPI interface Diagnosis output signal Limp home mode activation not connected, floating Power Supply Pins 1, 16, 18, 19, 36 1) 3 2 Parallel Input Pins 8 9 10 11 12 Power Output Pins 32, 33, 34, 35 2) 28, 29,30, 31 24, 25,26, 27 22, 23 2) 2) 2) 20, 21 2) SPI & Diagnosis Pins 7 6 5 4 13 Limp Home Pins 14 Other Pins 15, 17 1) All VBB pins have to be connected. 2) All output pins of each channel have to be connected. Data Sheet 9 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Electrical Characteristics 4 4.1 Electrical Characteristics Absolute Maximum Ratings Absolute Maximum Ratings1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin. (unless otherwise specified). Pos. Parameter Symbol Limit Values min. Supply Voltage 4.1.1 4.1.2 4.1.3 4.1.4 Power supply voltage Logic supply voltage Reverse polarity voltage according Figure 23 VBB VDD Unit Conditions max. 28 5.5 16 20 V V V V – – TjStart = 25 °C t ≤ 2 min 2) -0.3 -0.3 – 0 -VBAT(rev) Supply voltage for full short circuit protection (single VBB(SC) pulse) (Tj(0) = -40 °C … 150 °C) RECU = 20mΩ RCable= 16mΩ/m l = 0 or 5m 3) LCable= 1µH/m 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 Voltage at power transistor Supply Voltage for Load Dump protection Current through ground pin Current through VDD pin Load current VDS VBB(LD) IGND IDD IL IIS VIN IIN – – -100 -25 -IL(LIM) 54 41 25 12 IL(LIM) V V mA mA A mA V mA – RI = 2 Ω 4) t = 400ms t ≤ 2 min t ≤ 2 min 5) Power Stages Diagnosis Pin 4.1.10 Current through sense pin IS Input Pins 4.1.11 Voltage at input pins 4.1.12 Current through input pins SPI Pins 4.1.13 Voltage at chip select pin 4.1.14 Current through chip select pin 4.1.15 Voltage at serial input pin 4.1.16 Current through serial input pin 4.1.17 Voltage at serial clock pin 4.1.18 Current through serial clock pin 4.1.19 Current through serial output pin SO Limp Home Pins 4.1.20 Voltage at limp home input pin 4.1.21 Current through limp home input pin VLHI ILHI VCS ICS VSI ISI VSCLK ISCLK ISO -10 -0.3 -0.75 -2.0 -0.3 -2.0 -0.3 -2.0 -0.3 -2.0 -2.0 -0.3 -0.75 -2.0 10 8.0 0.75 2.0 5.7 2.0 5.7 2.0 5.7 2.0 2.0 8.0 0.75 2.0 t ≤ 2 min – – t ≤ 2 min – t ≤ 2 min V mA V mA V mA mA V mA – t ≤ 2 min – t ≤ 2 min t ≤ 2 min – – t ≤ 2 min Data Sheet 10 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Electrical Characteristics Absolute Maximum Ratings1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin. (unless otherwise specified). Pos. Parameter Symbol Limit Values min. Temperatures 4.1.22 Junction temperature 4.1.23 Dynamic temperature increase while switching 4.1.24 Storage temperature ESD Susceptibility 4.1.25 ESD resistivity HBM OUT pins other pins VESD Tj ∆Tj TSTG Unit Conditions max. 150 60 150 °C K °C kV – – – HBM6) – – -40 – -55 -4 -2 4 2 1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). 3) In accordance to AEC Q100-012 and AEC Q101-006. 4) RI is the internal resistance of the load dump pulse generator. 5) Current limitation is a protection feature. Operation in current limitation is considered as “outside” normal operating range. Protection features are not designed for continuous repetitive operation. 6) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5kΩ, 100pF). Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 11 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Power Supply 5 Power Supply The SPOC - BTS5566G is supplied by two supply voltages VBB and VDD. The VBB supply line is used by the power switches. The VDD supply line is used by the SPI related circuitry and for driving the SO line. A capacitor between pins VDD and GND is recommended. There is a power-on reset function implemented for the VDD logic supply voltage. After start-up of the logic power supply, all SPI registers are reset to their default values. The SPI interface including daisy chain function is active as soon as VDD is provided in the specified range independent of VBB. 5.1 Power Supply Modes The following table shows all possible power supply modes for VBB, VDD and the pin LHI. Power Supply Modes VBB VDD LHI PROFET operating Limp home mode SPI (logic) Stand-by current Idle current Diagnosis 0V 0V 0V – – reset – – – 0V 0V 5V – – reset – – – 0V 5V 0V – – ✓ – – – 0V 5V 5V – – ✓ – – – 13.5 V 0V 0V ✓ – reset ✓ – – 13.5 V 0V 5V ✓ ✓ reset – – – 13.5 V 5V 0V ✓ – ✓ – ✓ ✓ 1) 13.5 V 5V 5V ✓ ✓ reset – – ✓ 2) 1) When all channels are in OFF-state and all SPI registers are at default values. 2) Current sense diagnosis not available in limp home mode. To achieve stand-by mode, the limp home block must be disabled (LHI = 0 V), all channels must be switched off and the thermal latches have to be cleared. As a result the stand-by current IBB(OFF) is valid as listed. In case of active VDD supply, the idle mode parameters are valid only, when additionally all SPI registers are at default values (see Section 9.6) e.g. after a reset command. Data Sheet 12 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Power Supply 5.2 Reset There are several reset trigger implemented in the device. They reset the SPI registers to their default values. The power stages as well as the analog watchdog block are not affected by the reset signals. The first SPI transmission after any kind of reset contains at pin SO the read information from register OUT, and the transmission error bit TER is set. Power-On Reset The power-on reset is released, when VDD voltage level is higher than VDD(PO). The SPI interface can be accessed after wake up time tWU(PO). Reset Command There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As soon as HWCR.RST = 1, a reset is triggered equivalent to power-on reset. The SPI interface can be accessed after transfer delay time tCS(td). Limp Home Mode In limp home mode, the SPI write-registers are reset. The SPI interface is operating normally, so the limp home register bit LHI as well as the error flags can be read. Data Sheet 13 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Power Supply 5.3 Electrical Characteristics Electrical Characteristics Power Supply Unless otherwise specified: VBB = 9 V to 16 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C. typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C. Pos. 5.3.1 5.3.2 Parameter Operating voltage Stand-by current for whole device with loads Symbol Limit Values min. typ. – max. 28 V µA – VDD = 0 V VLHI = 0 V VIN = 0 V T j = 25 ° C Tj ≤ 85 °C 1) Tj = 150 °C VDD = 5 V VLHI = 0 V VIN = 0 V T j = 25 ° C Tj ≤ 85 °C 1) Tj = 150 °C Unit Test Conditions VBB IBB(OFF) 4.5 – – – Idle current for whole device with loads IBB(idle) 1.2 – – 3 3 50 µA – – – 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 Logic supply voltage Logic supply current Logic idle current Operating current for whole device Power-On reset threshold voltage Power-On wake up time – – – – 45 15 10 – – 3 3 50 5.5 150 35 20 3.8 500 V µA µA mA V µs VDD IDD IDD(idle) IGND VDD(PO) tWU(PO) 3.8 – – – – – – VCS = 0 V fSCLK = 0 Hz VCS = Vdd fSCLK = 0 Hz fSCLK = 0 Hz – – 1) Not subject to production test, specified by design. Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected from manufacturing at VBB = 13.5 V, VDD = 4.3 V and Tj = 25 °C. Data Sheet 14 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Power Supply 5.4 Command Description HWCR Hardware Configuration Register W/R read write 4 RST RST 3 0 0 2 SBM 0 1 PWM PWM 0 CTL CTL Field RST Bits 4 Type Description r Reset Command 0 Normal operation 1 Device in reset due to limp home mode Reset Command 0 Normal operation 1 Execute reset command RST 4 w Data Sheet 15 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Power Stages 6 Power Stages The high-side power stages are built by N-channel vertical power MOSFETs (DMOS) with charge pumps. There are five channels implemented in the device. Each channel can be switched on via an input pin or via SPI register OUT. 6.1 Output ON-State Resistance The on-state resistance RDS(ON) depends on the supply voltage VBB as well as on the junction temperature Tj. Figure 5 shows those dependencies. The behavior in reverse polarity mode is described in Section 7.3. Vbb = 13.5 V 250 200 RDS(ON) /mΩ 150 100 50 0 -50 -25 channel 0, 1 (bulb) channel 2 (bulb) channel 3, 4 RDS(ON) /mΩ 250 200 150 100 50 0 25 50 75 100 125 150 T /°C 0 5 10 15 Vbb /V 20 25 channel 0, 1 (bulb) channel 2 (bulb) channel 3, 4 Tj = 25 °C Figure 5 Typical On-State Resistance 6.2 Input Circuit There are two ways of using the input pins in combination with the OUT SPI register by programming the HWCR.PWM parameter. • • HWCR.PWM = 0: A channel is switched on either by the according OUT register bit or the input pin. HWCR.PWM = 1: A channel is switched on by the according OUT register bit only, when the input pin is high. In this configuration, a PWM signal can be given to the input pin and the channel is activated by the SPI register OUT. Figure 6 shows the complete input switch matrix. OUT4 IN0 IIN0 IN1 IIN1 IN2 IIN2 IN3 IIN3 IN4 IIN4 PWM InputMatrix.emf OR OR OR OR OUT3 OUT2 OUT1 OUT0 OR & Gate Driver 0 & Gate Driver 1 & Gate Driver 2 & Gate Driver 3 & Gate Driver 4 Figure 6 Input Switch Matrix The current sink to ground at the input pins ensures that the input signal is low in case of an open input pin. The zener diode protects the input circuit against ESD pulses. Data Sheet 16 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Power Stages 6.3 Power Stage Output The power stages are built to be used in high side configuration (Figure 7). VBB V ON V bb OUT GND V OUT Output.emf Figure 7 Power Stage Output The power DMOS switches with a dedicated slope, which is optimized in terms of EMC emission. IN tON tOFF t VOUT 90% 70% 70% 30% 10% dV / dtON dV / dtOFF 30% t SwitchOn.emf Figure 8 Switching a Load (resistive) When switching off inductive loads with high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent destruction of the device, there is a voltage clamp mechanism implemented that limits that negative output voltage to a certain level (VON(CL) (6.4.3)). See Figure 7 for details. The maximum allowed load inductance is limited. Data Sheet 17 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Power Stages 6.4 Electrical Characteristics Electrical Characteristic Power Stages Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C. typical values: VBB = 13.5 V, Tj = 25 °C. Pos. Parameter Output Characteristics 6.4.1 On-State resistance channel 0, 1 channel 2 channel 3, 4 6.4.2 Output voltage drop limitation at small load currents channel 0, 1, 2 channel 3, 4 6.4.3 Output clamp 6.4.4 Output leakage current per channel channel 0, 1 channel 2 channel 3, 4 6.4.5 Inverse current capability per channel channel 0, 1, 2 channel 3, 4 Thermal Resistance 6.4.6 Junction to Case 6.4.7 Junction to Ambient, all channels active Input Characteristics 6.4.8 L-input level 6.4.9 H-input level 6.4.10 L-input current 6.4.11 H-input current -IL(IC) Symbol min. Limit Values typ. max. Unit Test Conditions RDS(ON) – – – – – – 22.3 38 25.2 49 72.9 141 – 49 – 64 – 180 mΩ 1) Tj = 25 °, IL = 2.6 A Tj = 150 °, IL = 2.6 A 1) Tj = 25 °C, IL = 2.6 A Tj = 150 °C, IL = 2.6 A 1) Tj = 25 °C, IL = 1 A Tj = 150 °C,IL = 1 A VDS(NL) – – 35 35 47 – – 54 mV IL = 35 mA IL = 35 mA VON(CL) IL(OFF) 40 V µA IL = 20 mA VIN = 0 V OUT.OUTn = 0 – – – – – – 0.1 – 0.1 – 0.1 – 10 40 10 40 8 40 A stand-by not stand-by stand-by not stand-by stand-by not stand-by No influence on functionality of unaffected channels 1) – – K/W K/W 1) 1) 2) – – 2.5 1.0 – 40 – – 20 – RthJC RthJA – – VIN(L) VIN(H) IIN(L) IIN(H) -0.3 2.6 3 10 – – 25 40 1.0 5.5 75 75 V V µA µA – – VIN = 0.4 V VIN = 5 V Data Sheet 18 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Power Stages Electrical Characteristic Power Stages Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C. typical values: VBB = 13.5 V, Tj = 25 °C. Pos. Parameter Timings 6.4.12 Turn-on time to 90% VBB channel 0, 1, 2 channel 3, 4 6.4.13 Turn-off time to 10% VBB channel 0, 1, 2 channel 3, 4 6.4.14 Turn-on slew rate 30% to 70% VBB dV/ dtON channel 0, 1, 2 channel 3, 4 6.4.15 Turn-off slew rate 70% to 30% VBB -dV/ dtOFF channel 0, 1, 2 channel 3, 4 0.1 0.1 – – 0.5 0.5 0.1 0.1 – – 0.5 0.5 Symbol min. Limit Values typ. max. µs – – – – – – 250 250 µs – – 290 290 VBB = 13.5 V RL = 6.8 Ω RL = 18 Ω VBB = 13.5 V RL = 6.8 Ω RL = 18 Ω Unit Test Conditions tON tOFF V/µs VBB = 13.5 V RL = 6.8 Ω RL = 18 Ω V/µs VBB = 13.5 V RL = 6.8 Ω RL = 18 Ω 1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Data Sheet 19 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Power Stages 6.5 Command Description OUT Output Configuration Registers W/R read/write RB 0 5 0 4 OUT4 3 OUT3 2 OUT2 1 OUT1 0 OUT0 Field OUTn n = 4 to 0 Bits n Type r/w Description Set Output Mode for Channel n 0 Channel n is switched off 1 Channel n is switched on HWCR Hardware Configuration Register W/R read write 4 RST RST 3 0 0 2 SBM 0 1 PWM PWM 0 CTL CTL Field PWM Bits 1 Type rw Description PWM Configuration 0 Input signal OR-combined with according OUT register bit 1 Input signal AND-combined with according OUT register bit Data Sheet 20 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Protection Functions 7 Protection Functions The device provides embedded protective functions, which are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered as “outside” normal operating range. Protective functions are neither designed for continuous nor for repetitive operation. 7.1 Over Load Protection The load current IL is limited by the device itself in case of over load or short circuit to ground. There are multiple steps of current limitation which are selected automatically depending on the voltage VDS across the power DMOS. Please note that the voltage at the OUT pin is VBB - VDS. Please refer to following figures for details. IL 25 20 15 10 5 5 10 15 20 25 V DS CurrentLimitation01 .emf Figure 9 IL 25 20 15 10 5 Current Limitation Channels 0, 1 (minimum values) 5 10 15 20 25 V DS CurrentLimitation2 .emf Figure 10 IL 12 10 8 6 4 2 Current Limitation Channels 2 (minimum values) 5 10 15 20 25 V DS CurrentLimitation34 .emf Figure 11 Current Limitation Channels 3, 4 (minimum values) Current limitation to the value IL(LIM) is realized by increasing the resistance of the output channel, which leads to rapid temperature rise inside. Data Sheet 21 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Protection Functions 7.2 Over Temperature Protection A temperature sensor for each channel causes an overheated channel to switch off latched to prevent destruction ( also even in case of VDD = 0V). All over temperature latches are cleared by SPI command HWCR.CTL = 1. IN t IL IL(LIM) t IIS t ERR CTL = 1 t OverLoad.emf Figure 12 Shut Down by Over Temperature 7.3 Reverse Polarity Protection In reverse polarity mode, power dissipation is caused by the intrinsic body diode of each DMOS channel as well as each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected loads. The current trough the ground pin, sense pin IS, the logic power supply pin VDD, the SPI pins and the watchdog pins has to be limited as well (please refer to the maximum ratings listed on Page 10). Note: No other protection mechanism such as temperature protection or current limitation is active during reverse polarity. 7.4 Over Voltage Protection In addition to the output clamp for inductive loads as described in Section 6.3, there is a clamp mechanism available for over voltage protection. The current through the ground connection has to be limited during over voltage. Please note that in case of over voltage the pin GND may have a high voltage offset to the module ground. 7.5 Loss of Ground In case of complete loss of the device ground connections, but connected load ground, the SPOC - BTS5566G securely changes to or stays in off-state. 7.6 Loss of Vbb In case of loss of Vbb connection in on-state, all inductance of the loads has to be demagnetized through the ground connection or through an additional path from VBB to ground. When a diode is used in the ground path for reverse polarity reasons, the ground connection is not available for demagnetization. Then for example, a resistor can be placed in parallel to the diode or a suppressor diode can be used between VBB and GND. Data Sheet 22 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Protection Functions 7.7 Electrical Characteristics Electrical Characteristics Protection Functions Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, Tj = 25 °C Pos. Parameter Over Load Protection 7.7.1 Load current limitation channel 0 channel 1 channel 2 channel 3 channel 4 7.7.2 Initial short circuit shut down time channel 0, 1 channel 2 channel 3, 4 Over Temperature Protection 7.7.3 Thermal shut down temperature 7.7.4 Thermal hysteresis Reverse Battery 7.7.5 Drain-Source diode voltage (VOUT > Vbb) channel 0, 1 channel 2 channel 3, 4 Over Voltage 7.7.6 Overvoltage protection Loss of GND protection 7.7.7 Output current while GND disconnected -VDS(rev) Symbol min. Limit Values typ. max. Unit Test Conditions IL(LIM) 24 24 24 12 12 – – – – – 550 400 400 1701) 7 481) 48 48 27 27 1) 1) 1) 1) A VDS = 7 V – – – – – µs TjStart = 25 °C 1) tOFF(SC) – – – – – – – – – – – °C K mV – 1) Tj(SC) ∆ Tj 150 – Tj = 150 °C IL = -2.5 A IL = -2.5 A IL = -1 A – – – 600 620 600 47 – – – – 54 1 V mA VBB(AZ) IL(GND) 40 – IBB = 4 mA 1) 1) Not subject to production test, specified by design. Data Sheet 23 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Protection Functions 7.8 Command Description HWCR Hardware Configuration Register W/R read write 4 RST RST 3 0 0 2 SBM 0 1 PWM PWM 0 CTL CTL Field CTL Bits 0 Type Description rw Clear Thermal Latch 0 Thermal latches are untouched 1 Command: Clear all thermal latches Data Sheet 24 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Diagnosis 8 Diagnosis For diagnosis purpose, the SPOC - BTS5566G provides a current sense signal and the diagnosis word at SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. Please refer to Figure 13 for details. VBB IIS 0 latch gate control OR temperature sensor T load current limitation OUT4 OUT3 OUT2 OUT1 OUT0 channel 0 load current sense latch ERR0 DCR.MUX VBB VDS (S B ) HWCR. SBM current sense multiplexer IS R IS Diagnosis.emf Figure 13 Block Diagram: Diagnosis For diagnosis feedback at different operation modes, please see following table. Table 1 Operation Modes 1) Input Level OUT.OUTn L/0 (OFF-state) Output Level VOUT GND GND Z VBB Operation Mode Normal Operation (OFF) Short Circuit to GND Over Temperature Short Circuit to VBB Open Load Normal Operation (ON) Current Limitation Short Circuit to GND Over Temperature Short Circuit to VBB Open Load Current Sense IIS Z Z Z Z Z IL / kILIS Error Flag ERRn2) 0 0 0 0 0 0 1 1 1 3) HWCR. SBM 1 1 x 0 x 0 x 1 x 0 0 Z H/1 (ON-state) ~VBB < VBB ~GND Z VBB VBB Z Z Z < IL / kILIS Z 0 0 1) L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit x = undefined 2) The error flags are latched until they are transmitted in the standard diagnosis word via SPI 3) The over temperature flag is set latched and can be cleared by SPI command HWCR.CTL Data Sheet 25 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Diagnosis 8.1 Diagnosis Word at SPI The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard diagnosis bits ERRn. The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal. The over temperature flags, which cause an overheated channel to stay switched off, are latched directly at the gate control block. The latches are cleared by SPI command HWCR.CTL. Please note: The over temperature information is latched twice. When transmitting a clear thermal latch command (HWCR.CLT), the error flag is cleared during command transmission of the next SPI frame and ready for latching after the third raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CTL command will indicate a failure mode at the previously affected channels although the thermal latches have been cleared already. In case of continuous over load, the error flags are set again immediately because of the over load monitoring signal. In case of high duty cyle (off state of output < toff-state_min) the VDS might not be equal to VDD during the off state of the power Mosfet. The over load monitoring signals might be set and latched in the error flags. See Application Note “Software Strategy for Diagnosis during PWM-Operation“ for more details. 8.2 Load Current Sense Diagnosis There is a current sense signal available at pin IS which provides a current proportional to the load current of one selected channel. The selection is done by a multiplexer which is configured via SPI. The current sense signal (ratio kILIS = IL / IS) is provided as long as no failure mode occurs. Usually a resistor RIS is connected from the current sense pin to GND. It is recommended to use resistors 2.5 kΩ 000B RIS = 4.7 kΩ DCR.MUX:000B -> 001B 1) Unit Test Conditions tsIS(MUX) tdIS(MUX) toff state_min RIS = 4.7 kΩ DCR.MUX: 001B -> 111B – VDS(SB) 0.7 – 2.5 V – 1) Not subject to production test, specified by design. Data Sheet 30 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Diagnosis 8.5 Command Description DCR Diagnosis Control Registers 4 0 3 0 2 1 MUX 0 Field MUX Bits 2:0 Type Description rw Set Current Sense Multiplexer Configuration 000 current sense of channel 0 is routed to IS pin 001 current sense of channel 1 is routed to IS pin 010 current sense of channel 2 is routed to IS pin 011 current sense of channel 3 is routed to IS pin 100 current sense of channel 4 is routed to IS pin 101 IS pin is high impedance 110 IS pin is high impedance 111 IS pin is high impedance HWCR Hardware Configuration Register W/R read write 4 RST RST 3 0 0 2 SBM 0 1 PWM PWM 0 CTL CTL Field SBM Bits 2 Type Description r Switch Bypass Monitor1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) 1) Invalid in stand-by mode Standard Diagnosis CS TER 7 0 6 LHI 5 0 4 ERR4 3 ERR3 2 ERR2 1 ERR1 0 ERR0 Field ERRn n = 4 to 0 Bits n Type Description r Error flag Channel n 0 normal operation 1 failure mode occurred Data Sheet 31 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Serial Peripheral Interface (SPI) 9 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability. SO SI CS SCLK time SPI.emf CS MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB Figure 19 Serial Peripheral Interface 9.1 SPI Signal Description CS - Chip Select: The system micro controller selects the SPOC - BTS5566G by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: • • The requested information is transferred into the shift register. SO changes from high impedance state to high or low state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration, a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK. CS Low to High transition: • Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored. Data from shift register is transferred into the addressed register. • SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shifted-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 9.5 for further information. SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.5 for further information. Data Sheet 32 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Serial Peripheral Interface (SPI) 9.2 Daisy Chain Capability The SPI of SPOC - BTS5566G provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 20), in order to build a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain. device 1 MO SI SPI SO SI device 2 SPI SO SI device 3 SPI SO CS CS SCLK SCLK CS MI MCS MCLK Figure 20 Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out occures at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high (see Figure 21). MI MO MCS MCLK time SPI_DasyChain2.emf SO device 3 SI device 3 SO device 2 SI device 2 SO device 1 SI device 1 Figure 21 Data Transfer in Daisy Chain Configuration 9.3 Timing Diagrams tCS(lead) tCS(lag) tSCLK(P) tSCLK(H) tSCLK(L) 0.7Vdd 0.2Vdd tCS(td) 0.7Vdd 0.2Vdd CS SCLK tSI(su) tSI(h) SI tSO(en) tSO(v) tSO(dis) 0.7Vdd 0.2Vdd SO 0.7Vdd 0.2Vdd SPI Timing.emf Figure 22 Timing Diagram SPI Access Data Sheet 33 SCLK SPI_DasyChain.emf Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Serial Peripheral Interface (SPI) 9.4 Electrical Characteristics Electrical Characteristics SPI Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 °C to +150 °C, Vdd = 3.8 V to 5.5 V typical values: Vbb = 13.5 V, Tj = 25 °C, Vdd = 4.3 V Pos. Parameter Symbol Limit Values min. Input Characteristics (CS, SCLK, SI) 9.4.1 L level of pin CS VCS(L) SCLK VSCLK(L) SI VSI(L) 9.4.2 H level of pin CS VCS(H) SCLK VSCLK(H) SI VSI(H) 9.4.3 9.4.4 9.4.5 L-input pull-up current at CS pin H-input pull-up current at CS pin ICS(L) ICS(H) Unit Test Conditions typ. max. V VDD = 4.3 V – – – VDD = 4.3 V – – – VDD = 4.3 V,VCS = 0 V VDD = 4.3 V,VCS = 2.6 V VDD = 4.3 V VSCLK = 0.4 V VSI = 0.4 V VDD = 4.3 V VSCLK = 4.3 V VSI = 4.3 V ISO = -0.5 mA ISO = 0.5 mA,VDD = 4.3 V VCS =VDD -0.3 -0.3 -0.3 2.6 2.6 2.6 10 3 3 3 10 10 0 VDD 0.5 V – – – – – – 30 – – – 30 30 – – – – – – – – – – – – – 1.0 1.0 1.0 V 5.5 5.5 5.5 85 85 75 75 µA 75 75 0.5 VDD µA µA µA L-input pull-down current at pin SCLK ISCLK(L) SI ISI(L) H-input pull-down current at pin SCLK ISCLK(H) SI ISI(H) L level output voltage H level output voltage Output tristate leakage current VSO(L) VSO(H) ISO(OFF) fSCLK tSCLK(P) tSCLK(H) tSCLK(L) 9.4.6 Output Characteristics (SO) 9.4.7 9.4.8 9.4.9 V V µA -10 0 500 250 250 1 1 1 100 100 – 10 2 – – – – – – – – 1 Timings 9.4.10 Serial clock freqency 9.4.11 Serial clock period 9.4.12 Serial clock high time 9.4.13 Serial clock low time MHz – ns ns ns µs µs µs ns ns µs – – – – – – – – CL = 20 pF 1) 9.4.14 Enable lead time (falling CS to rising tCS(lead) SCLK) 9.4.15 Enable lag time (falling SCLK to rising CS) 9.4.16 Transfer delay time (rising CS to falling CS) tCS(lag) tCS(td) 9.4.17 Data setup time (required time SI to tSI(su) falling SCLK) 9.4.18 Data hold time (falling SCLK to SI) tSI(h) 9.4.19 Output enable time (falling CS to SO tSO(en) valid) Data Sheet 34 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Serial Peripheral Interface (SPI) Electrical Characteristics SPI Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 °C to +150 °C, Vdd = 3.8 V to 5.5 V typical values: Vbb = 13.5 V, Tj = 25 °C, Vdd = 4.3 V Pos. Parameter Symbol – – Limit Values min. 9.4.20 Output disable time (rising CS to SO tSO(dis) tri-state) 9.4.21 Output data valid time with capacitive load tSO(v) Unit Test Conditions 1 µs ns CL = 20 pF 1) CL = 20 pF 1) typ. – – max. 250 1) Not subject to production test, specified by design. Data Sheet 35 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Serial Peripheral Interface (SPI) 9.5 SPI Protocol CS1) 7 Write Register 1 Read Register 0 0 TER TER 0 1 x LHI ADDR 6 ADDR ADDR x X x x ERR4 x x ERR3 5 4 3 2 DATA x x ERR2 DATA x x ERR1 0 1 ERR0 1 0 SI SI SI SO SO Read Standard Diagnosis Standard Diagnosis Second Frame of Read Command 1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition. Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame. Field TER Bits CS Type Description r Transmission Error 0 Previous transmission was successful (modulo 8 clocks received) 1 Previous transmission failed or first transmission after reset Address Pointer to register for read and write command Data Data written to or read from register selected by address ADDR Limp Home Input Pin 0 L-input signal at pin LHI 1 H-input signal at pin LHI Diagnosis of Channel x 0 No failure 1 Over temperature, over load or short circuit ADDR DATA LHI 6:5 4:0 6 rw rw r ERRx x = 4 to 0 x r Data Sheet 36 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Serial Peripheral Interface (SPI) 9.6 Name OUT HWCR DCR Register Overview W/R W/R R W W/R Addr 00B 10B 10B 11B 4 OUT4 RST RST 0 3 OUT3 X 0 0 2 OUT2 SBM 0 1 OUT1 PWM PWM MUX 0 OUT0 CTL CTL default1) 00H 00H 00H 07H 1) The default values are set after reset. Data Sheet 37 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Application Description 10 Application Description Vbat 68nF 500 Ω 100nF 5V VDD VCC GPIO GPIO LHI 8k Ω 8k Ω VBB IN0 IN1 IN2 IN3 IN4 IS OUT0 OUT1 OUT2 OUT3 GND 3.3k Ω 27W 27W 27W 10W 10W µC AD 1k Ω 1nF OUT4 VDD SPI 2k Ω CS SCLK SO SI GND VBB Limp Home LHI 8k Ω LHI SPI 2k Ω 2kΩ 2kΩ VSS Schottky 10nF.. 100nF Circuit .emf Figure 23 Application Circuit Example Data Sheet 38 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Package Outlines SPOC - BTS5566G 11 Package Outlines SPOC - BTS5566G 2.65 MAX. 0.35 x 45˚ 7.6 -0.2 0.23 +0.09 1) 0.2 -0.1 2.45 -0.2 0.65 0.33 ±0.08 2) 0.1 C 0.7 ±0.2 10.3 ±0.3 0.17 M C A-B D 36x D A 36 19 Bottom View 19 36 Ejector Mark 1 18 18 1 B 1) 12.8 -0.2 Index Marking Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side GPS01089 Figure 24 PG-DSO-36-34 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. 8˚ MAX. Dimensions in mm Data Sheet 39 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5566G Revision History 12 Revision 1.3 1.2 Revision History Date 07-10-30 07-08-28 Changes • • • Chapter 11 Package outline drawing changed 4.1 Conditions updated 4.1 and 6.4 : footnote change to : Specified RthJA value is according to Jedec JESD512,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). • • • • • • 1.1 07-03-05 • • • • • • • • 4.1.4 Conditions updated 4.1.28 Definition change 5.2 Reset Command : tCS(td) change to : tCS(td). 8.4.1 Kilis : updated values for Channel 2-3 8.4.3 New parameter : Current sense leakage / offset current Max Input Voltage value change to 40 Volts Product summary Green Product (ROHS compliant) and AEC Qualified added 4.1.12 Current through input pins min value change to -0.75mA 4.1.21 Current through limp home input pin min value change to -0.75mA Chapter 2 Test pin change to Vbb Chapter 6 Ron definition changed Chapter 7.2 (also even in case of Vdd = 0V) added. Basic Feature : Green Logo added Chapter 8.1 In case of high duty cyle ( off state of output < toff state_min) the VDS might not be equal to VBB during the off state of the power Mosfet. The over load monitoring signals might be set and latched in the error flags. See Application Note “ Software Strategy for Diagnosis during PWM-Operation“ for more details Table 8.4.10 Off stateTime during PWM operation definition Chapter 11 68nF added between VBB and Gnd page 18: register read value added New template DIN A4 V1.2 • • • • Data Sheet 40 Rev. 1.3, 2007-10-30 Edition 2007-10-30 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2007. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.infineon.com Published by Infineon Technologies AG