BTS5576G

Data Sheet, Rev. 1.3, October 2007 SPOC - BTS5576G SPI Power Controller Automotive Power SPI Power Controller SPOC - BTS5576G Table of Contents 1 2 2.1 3 3.1 3.2 4 4.1 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.2 9.3 9.4 9.5 9.6 10 11 12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Assignment SPOC - BTS5576G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 14 15 16 16 16 17 18 20 21 21 22 22 22 22 22 23 24 25 26 26 28 29 31 32 32 33 33 34 36 37 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package Outlines SPOC - BTS5576G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data Sheet 2 Rev. 1.3, 2007-10-30 SPI Power Controller for Advanced Light Control with Integrated LED Mode SPOC - BTS5576G 1 Overview The SPOC - BTS5576G is a five channel high-side smart power switch in PG-DSO-36-34 package providing embedded protective functions. It is especially designed to control standard exterior lighting in automotive applications. In order to use the same hardware with bulbs and LEDs, the device can be configured to bulb or LED mode. As a result, both load types are handeled optimized in switching and diagnosis accuracy. It is designed to drive lamps up to 3*27W + 2*10W. Configuration and status diagnosis is done via SPI. Additionally, there is a current sense signal available for each channel that is routed via a multiplexer to a single diagnosis pin. The SPOC - BTS5576G provides a fail-safe function via limp home input pin. PG-DSO-36-34 Product Summary Operating Voltage Power Switch Logic Supply Voltage Over Voltage Protection Maximum Stand-By Current at 25 °C On-State Resistance at Tj = 150 ° channel 0, 1 channel 2 channel 3,4 VBB VDD VBB(AZ,min) IBB(OFF) RDS(ON) max 4.5 … 28 V 3.8 … 5.5 V 40 V 3 µA 49 mΩ 64 mΩ 180 mΩ 2 MHz SPI Access Frequency fSCLK(max) Type SPOC - BTS5576G Data Sheet Package PG-DSO-36-34 3 Marking BTS5576G Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Overview Basic Features • • • • • • • • • 8 bit serial peripheral interface (daisy chain capable SPI) for control and diagnostics CMOS compatible parallel input pins for each channel provide straightforward PWM operation Selectable AND- / OR-combination for parallel inputs (PWM control) Very low stand-by current Optimized electromagnetic compatibility (EMC) for bulbs as well as LEDs Stable behavior at under voltage Device ground independent from load ground Green Product (RoHS-Compliant) AEC Qualified Protective Functions • • • • • • • • Reverse battery protection with external components Short circuit protection Over load protection Multi step current limitation Thermal shutdown with latch Over voltage protection Loss of ground protection Electrostatic discharge protection (ESD) Diagnostic Functions • • • • • • • Multiplexed proportional load current sense signals (IS) Enable function for current sense signal configurable via SPI High accuracy of current sense signal at wide load current range Current sense ratio (kILIS) configurable for LEDs or bulbs Very fast diagnosis in LED mode ( Vbb) channel 0, 1 channel 2 channel 3, 4 Over Voltage 7.7.6 Overvoltage protection Loss of GND protection 7.7.7 Output current while GND disconnected -VDS(rev) Symbol min. Limit Values typ. max. Unit Test Conditions IL(LIM) 24 7 24 7 24 7 12 12 – – – – – – – – 550 500 400 350 400 1701) 7 481) 181) 481) 181) 481) 181) 271) 27 1) A VDS = 7 V LCR.LEDn = 0 LCR.LEDn = 1 LCR.LEDn = 0 LCR.LEDn = 1 LCR.LEDn = 0 LCR.LEDn = 1 – – µs TjStart = 25 °C 1) tOFF(SC) – – – – – – – – – – – – LCR.LEDn = 0 LCR.LEDn = 1 LCR.LEDn = 0 LCR.LEDn = 1 – °C K mV – 1) Tj(SC) ∆ Tj 150 – Tj = 150 °C IL = -2.5 A IL = -2.5 A IL = -1 A – – – 600 620 600 47 – – – – 54 1 V mA VBB(AZ) IL(GND) 40 – IBB = 4 mA 1) 1) Not subject to production test, specified by design. Data Sheet 23 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Protection Functions 7.8 Command Description HWCR Hardware Configuration Register W/R read write 4 RST RST 3 0 0 2 SBM 0 1 PWM PWM 0 CTL CTL Field CTL Bits 0 Type Description rw Clear Thermal Latch 0 Thermal latches are untouched 1 Command: Clear all thermal latches Data Sheet 24 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Diagnosis 8 Diagnosis For diagnosis purpose, the SPOC - BTS5576G provides a current sense signal and the diagnosis word at SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. Please refer to Figure 13 for details. VBB IIS 0(LE D) IIS 0 latch gate control OR temperature sensor T LED0 load current sense latch ERR0 load current limitation OUT4 OUT3 OUT2 OUT1 OUT0 channel 0 1 0 DCR.MUX VBB VDS (S B ) HWCR. SBM current sense multiplexer IS R IS DiagnosisL.emf Figure 13 Block Diagram: Diagnosis For diagnosis feedback at different operation modes, please see following table. Table 1 Operation Modes 1) Input Level OUT.OUTn L/0 (OFF-state) Output Level VOUT GND GND Z VBB Operation Mode Normal Operation (OFF) Short Circuit to GND Over Temperature Short Circuit to VBB Open Load Normal Operation (ON) Current Limitation Short Circuit to GND Over Temperature Short Circuit to VBB Open Load Current Sense IIS Z Z Z Z Z IL / kILIS Error Flag ERRn2) 0 0 0 0 0 0 1 1 1 3) HWCR. SBM 1 1 x 0 x 0 x 1 x 0 0 Z H/1 (ON-state) ~VBB < VBB ~GND Z VBB VBB Z Z Z < IL / kILIS Z 0 0 1) L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit x = undefined 2) The error flags are latched until they are transmitted in the standard diagnosis word via SPI 3) The over temperature flag is set latched and can be cleared by SPI command HWCR.CTL Data Sheet 25 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Diagnosis 8.1 Diagnosis Word at SPI The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard diagnosis bits ERRn. The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal. The over temperature flags, which cause an overheated channel to stay switched off, are latched directly at the gate control block. The latches are cleared by SPI command HWCR.CTL. Please note: The over temperature information is latched twice. When transmitting a clear thermal latch command (HWCR.CLT), the error flag is cleared during command transmission of the next SPI frame and ready for latching after the third raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CTL command will indicate a failure mode at the previously affected channels although the thermal latches have been cleared already. In case of continuous over load, the error flags are set again immediately because of the over load monitoring signal. In case of high duty cyle (off state of output < toff-state_min) the VDS might not be equal to VDD during the off state of the power Mosfet. The over load monitoring signals might be set and latched in the error flags. See Application Note “Software Strategy for Diagnosis during PWM-Operation“ for more details. 8.2 Load Current Sense Diagnosis There is a current sense signal available at pin IS which provides a current proportional to the load current of one selected channel. The selection is done by a multiplexer which is configured via SPI. The current sense signal (ratio kILIS = IL / IS) is provided as long as no failure mode occurs. The ratio kILIS can be adjusted to the load type (LED or bulb) via SPI register LCR for channels 0 to 2. Usually a resistor RIS is connected from the current sense pin to GND. It is recommended to use resistors 2.5 kΩ 000B RIS = 4.7 kΩ DCR.MUX:000B -> 001B 1) 8.4.7 Current sense settling time after change tsIS(LC) of load current channel 0, 1, 2 channel 3, 4 8.4.8 Current sense settling time after current tsIS(EN) sense activation 8.4.9 Current sense settling time after multiplexer channel change 8.4.10 Current sense deactivation time 8.4.11 Off state time during PWM operation Switch Bypass Monitor 8.4.12 Switch bypass monitor threshold – – – – – 350 150 0.7 – – – – – – – – 30 30 25 30 25 – – 2.5 µs µs µs µs µs V tsIS(MUX) tdIS(MUX) toff state_min RIS = 4.7 kΩ DCR.MUX: 001B -> 111B LCR.LEDn = 0 LCR.LEDn = 1 – VDS(SB) 1) Not subject to production test, specified by design. Data Sheet 30 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Diagnosis 8.5 Command Description DCR Diagnosis Control Registers 4 0 3 0 2 1 MUX 0 Field MUX Bits 2:0 Type Description rw Set Current Sense Multiplexer Configuration 000 current sense of channel 0 is routed to IS pin 001 current sense of channel 1 is routed to IS pin 010 current sense of channel 2 is routed to IS pin 011 current sense of channel 3 is routed to IS pin 100 current sense of channel 4 is routed to IS pin 101 IS pin is high impedance 110 IS pin is high impedance 111 IS pin is high impedance HWCR Hardware Configuration Register W/R read write 4 RST RST 3 0 0 2 SBM 0 1 PWM PWM 0 CTL CTL Field SBM Bits 2 Type Description r Switch Bypass Monitor1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) 1) Invalid in stand-by mode Standard Diagnosis CS TER 7 0 6 LHI 5 0 4 ERR4 3 ERR3 2 ERR2 1 ERR1 0 ERR0 Field ERRn n = 4 to 0 Bits n Type Description r Error flag Channel n 0 normal operation 1 failure mode occurred Data Sheet 31 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Serial Peripheral Interface (SPI) 9 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability. SO SI CS SCLK time SPI.emf CS MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB Figure 20 Serial Peripheral Interface 9.1 SPI Signal Description CS - Chip Select: The system micro controller selects the SPOC - BTS5576G by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: • • The requested information is transferred into the shift register. SO changes from high impedance state to high or low state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration, a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK. CS Low to High transition: • Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored. Data from shift register is transferred into the addressed register. • SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shifted-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 9.5 for further information. SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.5 for further information. Data Sheet 32 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Serial Peripheral Interface (SPI) 9.2 Daisy Chain Capability The SPI of SPOC - BTS5576G provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 21), in order to build a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain. device 1 MO SI SPI SO SI device 2 SPI SO SI device 3 SPI SO CS CS SCLK SCLK CS MI MCS MCLK Figure 21 Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out occures at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high (see Figure 22). MI MO MCS MCLK time SPI_DasyChain2.emf SO device 3 SI device 3 SO device 2 SI device 2 SO device 1 SI device 1 Figure 22 Data Transfer in Daisy Chain Configuration 9.3 Timing Diagrams tCS(lead) tCS(lag) tSCLK(P) tSCLK(H) tSCLK(L) 0.7Vdd 0.2Vdd tCS(td) 0.7Vdd 0.2Vdd CS SCLK tSI(su) tSI(h) SI tSO(en) tSO(v) tSO(dis) 0.7Vdd 0.2Vdd SO 0.7Vdd 0.2Vdd SPI Timing.emf Figure 23 Timing Diagram SPI Access Data Sheet 33 SCLK SPI_DasyChain.emf Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Serial Peripheral Interface (SPI) 9.4 Electrical Characteristics Electrical Characteristics SPI Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 °C to +150 °C, Vdd = 3.8 V to 5.5 V typical values: Vbb = 13.5 V, Tj = 25 °C, Vdd = 4.3 V Pos. Parameter Symbol Limit Values min. Input Characteristics (CS, SCLK, SI) 9.4.1 L level of pin CS VCS(L) SCLK VSCLK(L) SI VSI(L) 9.4.2 H level of pin CS VCS(H) SCLK VSCLK(H) SI VSI(H) 9.4.3 9.4.4 9.4.5 L-input pull-up current at CS pin H-input pull-up current at CS pin ICS(L) ICS(H) Unit Test Conditions typ. max. V VDD = 4.3 V – – – VDD = 4.3 V – – – VDD = 4.3 V,VCS = 0 V VDD = 4.3 V,VCS = 2.6 V VDD = 4.3 V VSCLK = 0.4 V VSI = 0.4 V VDD = 4.3 V VSCLK = 4.3 V VSI = 4.3 V ISO = -0.5 mA ISO = 0.5 mA,VDD = 4.3 V VCS =VDD -0.3 -0.3 -0.3 2.6 2.6 2.6 10 3 3 3 10 10 0 VDD 0.5 V – – – – – – 30 – – – 30 30 – – – – – – – – – – – – – 1.0 1.0 1.0 V 5.5 5.5 5.5 85 85 75 75 µA 75 75 0.5 VDD µA µA µA L-input pull-down current at pin SCLK ISCLK(L) SI ISI(L) H-input pull-down current at pin SCLK ISCLK(H) SI ISI(H) L level output voltage H level output voltage Output tristate leakage current VSO(L) VSO(H) ISO(OFF) fSCLK tSCLK(P) tSCLK(H) tSCLK(L) 9.4.6 Output Characteristics (SO) 9.4.7 9.4.8 9.4.9 V V µA -10 0 500 250 250 1 1 1 100 100 – 10 2 – – – – – – – – 1 Timings 9.4.10 Serial clock freqency 9.4.11 Serial clock period 9.4.12 Serial clock high time 9.4.13 Serial clock low time MHz – ns ns ns µs µs µs ns ns µs – – – – – – – – CL = 20 pF 1) 9.4.14 Enable lead time (falling CS to rising tCS(lead) SCLK) 9.4.15 Enable lag time (falling SCLK to rising CS) 9.4.16 Transfer delay time (rising CS to falling CS) tCS(lag) tCS(td) 9.4.17 Data setup time (required time SI to tSI(su) falling SCLK) 9.4.18 Data hold time (falling SCLK to SI) tSI(h) 9.4.19 Output enable time (falling CS to SO tSO(en) valid) Data Sheet 34 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Serial Peripheral Interface (SPI) Electrical Characteristics SPI Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 °C to +150 °C, Vdd = 3.8 V to 5.5 V typical values: Vbb = 13.5 V, Tj = 25 °C, Vdd = 4.3 V Pos. Parameter Symbol – – Limit Values min. 9.4.20 Output disable time (rising CS to SO tSO(dis) tri-state) 9.4.21 Output data valid time with capacitive load tSO(v) Unit Test Conditions 1 µs ns CL = 20 pF 1) CL = 20 pF 1) typ. – – max. 250 1) Not subject to production test, specified by design. Data Sheet 35 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Serial Peripheral Interface (SPI) 9.5 SPI Protocol CS1) 7 Write Register 1 Read Register 0 0 TER TER 0 1 x LHI ADDR 6 ADDR ADDR x X x x ERR4 x x ERR3 5 4 3 2 DATA x x ERR2 DATA x x ERR1 0 1 ERR0 1 0 SI SI SI SO SO Read Standard Diagnosis Standard Diagnosis Second Frame of Read Command 1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition. Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame. Field TER Bits CS Type Description r Transmission Error 0 Previous transmission was successful (modulo 8 clocks received) 1 Previous transmission failed or first transmission after reset Address Pointer to register for read and write command Data Data written to or read from register selected by address ADDR Limp Home Input Pin 0 L-input signal at pin LHI 1 H-input signal at pin LHI Diagnosis of Channel x 0 No failure 1 Over temperature, over load or short circuit ADDR DATA LHI 6:5 4:0 6 rw rw r ERRx x = 4 to 0 x r Data Sheet 36 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Serial Peripheral Interface (SPI) 9.6 Name OUT LCR HWCR DCR Register Overview W/R W/R W/R R W W/R Addr 00B 01B 10B 10B 11B 4 OUT4 X RST RST 0 3 OUT3 X X 0 0 2 OUT2 LED2 SBM 0 1 OUT1 LED1 PWM PWM MUX 0 OUT0 LED0 CTL CTL default1) 00H 18H 00H 00H 07H 1) The default values are set after reset. Data Sheet 37 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Application Description 10 Application Description Vbat 68nF 500 Ω 100nF 5V VDD VCC GPIO GPIO LHI 8k Ω 8k Ω VBB IN0 IN1 IN2 IN3 IN4 IS OUT0 OUT1 OUT2 OUT3 GND 3.3k Ω 27W 27W 27W 10W 10W µC AD 1k Ω 1nF OUT4 VDD SPI 2k Ω CS SCLK SO SI GND VBB Limp Home LHI 8k Ω LHI SPI 2k Ω 2kΩ 2kΩ VSS Schottky 10nF.. 100nF Circuit .emf Figure 24 Application Circuit Example Data Sheet 38 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Package Outlines SPOC - BTS5576G 11 Package Outlines SPOC - BTS5576G 2.65 MAX. 0.35 x 45˚ 7.6 -0.2 0.23 +0.09 1) 0.2 -0.1 2.45 -0.2 0.65 0.33 ±0.08 2) 0.1 C 0.7 ±0.2 10.3 ±0.3 0.17 M C A-B D 36x D A 36 19 Bottom View 19 36 Ejector Mark 1 18 18 1 B 1) 12.8 -0.2 Index Marking Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side GPS01089 Figure 25 PG-DSO-36-34 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. 8˚ MAX. Dimensions in mm Data Sheet 39 Rev. 1.3, 2007-10-30 SPI Power Controller SPOC - BTS5576G Revision History 12 Revision 1.3 1.2 Revision History Date 07-10-30 07-08-28 Changes • • • Chapter 11 Package outline drawing changed 4.1 Conditions updated 4.1 and 6.4 : footnote change to : Specified RthJA value is according to Jedec JESD512,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). • • • • • • 1.1 07-03-05 • • • • • • • • 4.1.4 Conditions updated 4.1.28 Definition change 5.2 Reset Command : tCS(td) change to : tCS(td). 8.4.1 Kilis : updated values for Channel 2-3 8.4.3 New parameter : Current sense leakage / offset current Max Input Voltage value change to 40 Volts Product summary Green Product (ROHS compliant) and AEC Qualified added 4.1.12 Current through input pins min value change to -0.75mA 4.1.21 Current through limp home input pin min value change to -0.75mA Chapter 2 Test pin change to Vbb Chapter 6 Ron definition changed Chapter 7.2 (also even in case of Vdd = 0V) added. Basic Feature : Green Logo added Chapter 8.1 In case of high duty cyle ( off state of output < toff state_min) the VDS might not be equal to VBB during the off state of the power Mosfet. The over load monitoring signals might be set and latched in the error flags. See Application Note “ Software Strategy for Diagnosis during PWM-Operation“ for more details Table 8.4.10 Off stateTime during PWM operation definition Chapter 11 68nF added between VBB and Gnd page 18: register read value added New template DIN A4 V1.2 • • • • Data Sheet 40 Rev. 1.3, 2007-10-30 Edition 2007-10-30 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2007. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.infineon.com Published by Infineon Technologies AG