BTS5590G

Data Sheet, Rev. 1.3, October 2007 SPOC - BTS5590G SPI Power Controller Automotive Power SPOC - BTS5590G Table of Contents 1 2 2.1 3 3.1 3.2 4 4.1 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.2 9.3 9.4 10 10.1 10.2 10.3 10.4 10.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Assignment SPOC - BTS5590G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limp Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trigger State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 13 14 15 16 17 17 17 18 19 21 22 22 23 23 23 23 23 24 25 26 27 27 29 30 32 33 33 34 35 36 37 37 38 38 39 41 Data Sheet Rev. 1.3, 2007-10-30 SPOC - BTS5590G 10.6 11 12 13 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Package Outlines SPOC - BTS5590G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Data Sheet 3 Rev. 1.3, 2007-10-30 SPI Power Controller for Advanced Light Control with Integrated LED Mode and Watchdog SPOC - BTS5590G 1 Overview The SPOC - BTS5590G is a five channel high-side smart power switch in PG-DSO-36-34 package providing embedded protective functions. It is especially designed to control standard exterior lighting in automotive applications. In order to use the same hardware with bulbs and LEDs, the device can be configured to bulb or LED mode. As a result, both load types are handeled optimized in switching and diagnosis accuracy. It is designed to drive lamps up to 3*27W + 2*10W. Configuration and status diagnosis is done via SPI. Additionally, there is a current sense signal available for each channel that is routed via a multiplexer to a single diagnosis pin. PG-DSO-36-34 The SPOC - BTS5590G provides a fail-safe function with integrated watchdog. The watchdog is served via SPI by a sophisticated state machine providing secure limp home functionality. Product Summary Operating Voltage Power Switch Logic Supply Voltage Over Voltage Protection Maximum Stand-By Current at 25 °C On-State Resistance at Tj = 150 ° channel 0, 1 channel 2 channel 3,4 VBB VDD VBB(AZ,min) IBB(OFF) RDS(ON) max 4.5 … 28 V 3.8 … 5.5 V 40 V 3 µA 50 mΩ 80 mΩ 200 mΩ 1 MHz SPI Access Frequency fSCLK(max) Type SPOC - BTS5590G Data Sheet Package PG-DSO-36-34 4 Marking BTS5590G Rev. 1.3, 2007-10-30 SPOC - BTS5590G Overview Basic Features • • • • • • • • • 8 bit serial peripheral interface (daisy chain capable SPI) for control and diagnostics CMOS compatible parallel input pins for each channel provide straightforward PWM operation Selectable AND- / OR-combination for parallel inputs (PWM control) Very low stand-by current Optimized electromagnetic compatibility (EMC) for bulbs as well as LEDs Stable behavior at under voltage Device ground independent from load ground Green Product (RoHS-Compliant) AEC Qualified Protective Functions • • • • • • • • Reverse battery protection with external components Short circuit protection Over load protection Multi step current limitation Thermal shutdown with latch Over voltage protection Loss of ground protection Electrostatic discharge protection (ESD) Diagnostic Functions • • • • • • • Multiplexed proportional load current sense signals (IS) Enable function for current sense signal configurable via SPI High accuracy of current sense signal at wide load current range Current sense ratio (kILIS) configurable for LEDs or bulbs Very fast diagnosis in LED mode ( Vbb) channel 0, 1 channel 2 channel 3, 4 Over Voltage 7.7.6 Overvoltage protection Loss of GND protection 7.7.7 Output current while GND disconnected -VDS(rev) Symbol min. Limit Values typ. max. Unit Test Conditions IL(LIM) 24 7 24 7 24 7 12 12 – – – – – – – – 550 500 400 350 400 1701) 7 481) 181) 481) 181) 481) 181) 271) 27 1) A VDS = 7 V WDLR.LEDn = 0 WDLR.LEDn = 1 WDLR.LEDn = 0 WDLR.LEDn = 1 WDLR.LEDn = 0 WDLR.LEDn = 1 – – µs TjStart = 25 °C 1) tOFF(SC) – – – – – – – – – – – – WDLR.LEDn = 0 WDLR.LEDn = 1 WDLR.LEDn = 0 WDLR.LEDn = 1 – °C K mV – 1) Tj(SC) ∆ Tj 150 – Tj = 150 °C IL = -2.5 A IL = -2.5 A IL = -1 A – – – 600 620 600 47 – – – – 54 1 V mA VBB(AZ) IL(GND) 40 – IBB = 4 mA 1) 1) Not subject to production test, specified by design. Data Sheet 24 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Protection Functions 7.8 Command Description HWCR Hardware Configuration Register W/R read write 4 LHO RST 3 WDL WDL 2 SBM 0 1 PWM PWM 0 CTL CTL Field CTL Bits 0 Type Description rw Clear Thermal Latch 0 Thermal latches are untouched 1 Command: Clear all thermal latches Data Sheet 25 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Diagnosis 8 Diagnosis For diagnosis purpose, the SPOC - BTS5590G provides a current sense signal and the diagnosis word at SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. Please refer to Figure 13 for details. VBB IIS 0(LE D) IIS 0 latch gate control OR temperature sensor T LED0 load current sense latch ERR0 load current limitation OUT4 OUT3 OUT2 OUT1 OUT0 channel 0 1 0 DCR.MUX VBB VDS (S B ) HWCR. SBM current sense multiplexer IS R IS DiagnosisL.emf Figure 13 Block Diagram: Diagnosis For diagnosis feedback at different operation modes, please see following table. Table 1 Operation Modes 1) Input Level OUT.OUTn L/0 (OFF-state) Output Level VOUT GND GND Z VBB Operation Mode Normal Operation (OFF) Short Circuit to GND Over Temperature Short Circuit to VBB Open Load Normal Operation (ON) Current Limitation Short Circuit to GND Over Temperature Short Circuit to VBB Open Load Current Sense IIS Z Z Z Z Z IL / kILIS Error Flag ERRn2) 0 0 0 0 0 0 1 1 1 3) HWCR. SBM 1 1 x 0 x 0 x 1 x 0 0 Z H/1 (ON-state) ~VBB < VBB ~GND Z VBB VBB Z Z Z < IL / kILIS Z 0 0 1) L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit x = undefined 2) The error flags are latched until they are transmitted in the standard diagnosis word via SPI 3) The over temperature flag is set latched and can be cleared by SPI command HWCR.CTL Data Sheet 26 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Diagnosis 8.1 Diagnosis Word at SPI The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard diagnosis bits ERRn. The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal. The over temperature flags, which cause an overheated channel to stay switched off, are latched directly at the gate control block. The latches are cleared by SPI command HWCR.CTL. Please note: The over temperature information is latched twice. When transmitting a clear thermal latch command (HWCR.CLT), the error flag is cleared during command transmission of the next SPI frame and ready for latching after the third raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CTL command will indicate a failure mode at the previously affected channels although the thermal latches have been cleared already. In case of continuous over load, the error flags are set again immediately because of the over load monitoring signal. In case of high duty cyle (off state of output < toff-state_min) the VDS might not be equal to VDD during the off state of the power Mosfet. The over load monitoring signals might be set and latched in the error flags. See Application Note “Software Strategy for Diagnosis during PWM-Operation“ for more details. 8.2 Load Current Sense Diagnosis There is a current sense signal available at pin IS which provides a current proportional to the load current of one selected channel. The selection is done by a multiplexer which is configured via SPI. The current sense signal (ratio kILIS = IL / IS) is provided as long as no failure mode occurs. The ratio kILIS can be adjusted to the load type (LED or bulb) via SPI register WDLR for channels 0 to 2. Usually a resistor RIS is connected from the current sense pin to GND. It is recommended to use resistors 2.5 kΩ 000B RIS = 4.7 kΩ DCR.MUX:000B -> 001B 1) 8.4.7 Current sense settling time after change tsIS(LC) of load current channel 0, 1, 2 channel 3, 4 8.4.8 Current sense settling time after current tsIS(EN) sense activation 8.4.9 Current sense settling time after multiplexer channel change 8.4.10 Current sense deactivation time 8.4.11 Off state time during PWM operation Switch Bypass Monitor 8.4.12 Switch bypass monitor threshold – – – – – 350 150 0.7 – – – – – – – – 30 30 25 30 25 – – 2.5 µs µs µs µs tsIS(MUX) tdIS(MUX) toff state_min RIS = 4.7 kΩ DCR.MUX: 001B -> 111B WDLR.LEDn = 0 WDLR.LEDn = 1 – VDS(SB) V 1) Not subject to production test, specified by design. Data Sheet 31 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Diagnosis 8.5 Command Description DCR Diagnosis Control Registers 4 0 3 0 2 1 MUX 0 Field MUX Bits 2:0 Type Description rw Set Current Sense Multiplexer Configuration 000 current sense of channel 0 is routed to IS pin 001 current sense of channel 1 is routed to IS pin 010 current sense of channel 2 is routed to IS pin 011 current sense of channel 3 is routed to IS pin 100 current sense of channel 4 is routed to IS pin 101 IS pin is high impedance 110 IS pin is high impedance 111 IS pin is high impedance HWCR Hardware Configuration Register W/R read write 4 LHO RST 3 WDL WDL 2 SBM 0 1 PWM PWM 0 CTL CTL Field SBM Bits 2 Type Description r Switch Bypass Monitor1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) 1) Invalid in stand-by mode Standard Diagnosis CS TER 7 0 6 LHEN 5 WDL 4 ERR4 3 ERR3 2 ERR2 1 ERR1 0 ERR0 Field ERRn n = 4 to 0 Bits n Type Description r Error flag Channel n 0 normal operation 1 failure mode occurred Data Sheet 32 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Limp Home 9 Limp Home The SPOC - BTS5590G provides a sophisticated watchdog function with trigger state machine to build a secure limp home signalling. The fail safe block is supplied via VBB and provides an output signal at pin LHO in case of watchdog overrun independently of VDD. There is an enable pin LHEN available which is usually connected to the ignition signal of the car. As soon as the limp home function is enabled, the watchdog is started and must be served. The timing can be adjusted in a wide range by choosing the appropriate capacitor. For calculation of the watchdog timing, please refer to Section 9.1. The watchdog is served via a trigger state machine, which starts at a defined state when limp home has been enabled. As a result, the state machine might also be reset to this startup state due to a voltage drop at pin LHEN. A watchdog overrun causes the LHO pin to turn from tri-state to a high signal. This signal can be utilized to switch on dedicated channels by connecting LHO to the appropriate input pins and it is suitable to turn other hardware of the system into limp home mode as well. Once the watchdog has been overrun, it can be reset by a low signal at pin LHEN only. There is no software reset mechanism implemented for this function to make sure, a faulty software can not turn off the limp home mode. The status of the watchdog as well as the trigger state machine can be read via SPI. As a result, the micro controller can perform a watchdog check via SPI. Please see following Figure 19 for details. VBB LHEN power supply VLHD(O) ILHD(C) ILHD(D) sub WDC += 1 OR OR trigger state machine LHEN LHO WDL WDTR WDC & & 1 0 LHO LHD CWD V LHD(R) GND LimpHome .emf Figure 19 Block Diagram: Limp Home 9.1 Watchdog The watchdog function is built as analog trigger watchdog with external capacitor CWD as time base. A high signal at pin LHEN enables the watchdog. A constant current loads the external capacitor, so the voltage rise is linear. When the watchdog is served, the capacitor is discharged to level VLHD(R) and the cycle starts again. Please see following figure for details. LHEN trigger VLHD WDTR == WDC t t V LHD(O) VLHD(R) WDC += 1 VLHO t Watchdog.emf t Figure 20 Data Sheet Watchdog Behavior 33 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Limp Home The limp home out signal (LHO) is generated, when the voltage at pin LHD exceeds threshold VLHD(O). In this case, all SPI registers are reset, but the read-only parameters (LHO, ERRn) are still available. The SPI interface including daisy chain capability is not affected by this reset signal. As a result it can be accessed normally. The maximum watchdog serve time which is the minimum watchdog overrun time tWD(O,min) is calculated by following formula: C WD(min) ⋅ ( V LHD(O,min) – V LHD(R,max) ) t WD(O,min) = ------------------------------------------------------------------------------------------------I LHD(C,max) (1) The maximum watchdog overrun time tWD(O,max) is calculated by following formula: C WD(max) ⋅ ( V LHD(O,max) – V LHD(R,min) ) t WD(O,max) = -------------------------------------------------------------------------------------------------I LHD(C,min) (2) There is an under voltage reset implemented in the watchdog block. In case of VBB lower than the operating voltage range of the watchdog (Position 5.3.2, Vbb(WD)), the LHO driver is deactivated and the external capacitor CWD is discharged. As soon as the voltage rises above the under voltage threshold, the capacitor is charged again and the LHO driver is activated. In case of fast VBB transients between VBB(WD memory)min and VBB(WD) min voltage and VLHD > VLHD(R) the watchdog capacitor CWD is only discharged as long as the voltage is below VBB(WD) min. I.e. in case of very short transients the charging or discharging process will continue after the disturbance with the same mode (charging or discharging) as before the voltage break down as long as VLHD > VLHD(R). 9.2 Trigger State Machine A trigger state machine is implemented to ensure secure limp home signalling. LHO 1 V LH WDC 0 D V LHD ≤ VLHD(R) TR D W WDC 1 < >W DC LH EN (L ) W DC W DL =0 =V LH EN LHEN 0 VLHEN = V LHEN(H) WDC 3 VLHD ≤ V LHD(R) W DT R V V LHEN = V LHEN(L) DC W V LHD ≤ VLHD(R) W DT R WDL 1 W DL = R DT W DC W 0 ≥V D LH ) (O =0 DL W V LHD ≤V LHD(R) =0 DL W WDC 2 TriggerSM .emf Figure 21 Trigger State Machine There are two bits in the SPI register block (WDLR.WDTR) that have to be subsequently increased to serve the watchdog. The WDLR.WDC parameter is increased by the device itself as soon as the capacitor is discharged below threshold VLHD(R). The watchdog lock (HWCR.WDL) is set, when an incorrect WDLR.WDTR value (WDLR.WDTR WDLR.WDC) has been written via SPI. To serve the watchdog then, the lock bit has to be cleared and the correct WDLR.WDTR value (WDLR.WDTR = WDLR.WDC) has to be written. The HWCR.WDL bit is also part of the standard diagnosis (WDL) and can be monitored at each SPI access. The lock of the state machine trigger ensures that only correct handling will serve the watchdog. Any incorrect WDLR.WDTR value will lock the trigger for the watchdog, which will overrun after the specified timings. Data Sheet 34 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Limp Home The trigger state machine is reset to the default values (see Section 10.6) by the following events: • • • Pin LHEN = low Pin LHO = 1 (limp home mode) The reset sources described in Section 5.2 9.3 Electrical Characteristics Electrical Characteristics Limp Home Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C, VLHEN = 5 V. typical values: VBB = 13.5 V, Tj = 25 °C. Pos. Parameter Limp Home 9.3.1 H-output voltage level of pin LHO 9.3.2 Current limitation of pin LHO Watchdog 9.3.3 Charge current for CWD 9.3.4 Discharge current for CWD 9.3.5 Overrun threshold voltage at pin LHD 9.3.6 Recharge threshold voltage at pin LHD Input Characteristics 9.3.7 L-input level at pin LHEN 9.3.8 H-input level at pin LHEN 9.3.9 L-input current through pin LHEN 9.3.10 H-input current through pin LHEN VLHEN(L) VLHEN(H) ILHEN(L) ILHEN(H) ILHD(C) -ILHD(D) VLHD(O) VLHD(R) VLHO(H) ILHO(lim) Symbol Limit Values min. 5 2 15 300 4.0 0.4 -0.3 2.6 3 7 typ. – – 22 – 4.4 0.5 – – – 30 max. 9 – 30 – 4.8 0.6 1.0 5.5 85 85 Unit Test Conditions V mA µA µA V V V V µA µA VLHD = 5 V ILHO = 1 mA VLHD = 5 V – – – – – – VLHEN = 0.4 V VLHEN = 5 V Data Sheet 35 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Limp Home 9.4 Command Description WDLR Watchdog and LED Mode Configuration Register W/R read write 4 WDC WDTR 3 2 LED2 LED2 1 LED1 LED1 0 LED0 LED0 Field WDC WDTR Bits 4:3 4:3 Type r w Description Watchdog trigger state machine counter (default value 11) Watchdog trigger register (default value 00) HWCR Hardware Configuration Register W/R read write 4 LHO RST 3 WDL WDL 2 SBM 0 1 PWM PWM 0 CTL CTL Field LHO Bits 4 Type Description r Limp Home Out 0 Device is in normal operation mode 1 Device is in limp home mode Watchdog Lock 0 Watchdog can be served 1 Watchdog state machine trigger is locked WDL 3 rw Standard Diagnosis CS TER 7 0 6 LHEN 5 WDL 4 ERR4 3 ERR3 2 ERR2 1 ERR1 0 ERR0 Field LHEN Bits 6 Type r Description Limp Home Enable 0 L-input signal at pin LHEN 1 H-input signal at pin LHEN Watchdog Lock 0 Watchdog can be served 1 Watchdog trigger state machine is locked WDL 5 r Data Sheet 36 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Serial Peripheral Interface (SPI) 10 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability. SO SI CS SCLK time SPI.emf CS MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB Figure 22 Serial Peripheral Interface 10.1 SPI Signal Description CS - Chip Select: The system micro controller selects the SPOC - BTS5590G by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: • • The requested information is transferred into the shift register. SO changes from high impedance state to high or low state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration, a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK. CS Low to High transition: • Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored. Data from shift register is transferred into the addressed register. • SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shifted-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 10.5 for further information. SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 10.5 for further information. Data Sheet 37 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Serial Peripheral Interface (SPI) 10.2 Daisy Chain Capability The SPI of SPOC - BTS5590G provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 23), in order to build a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain. device 1 MO SI SPI SO SI device 2 SPI SO SI device 3 SPI SO CS CS SCLK SCLK CS MI MCS MCLK Figure 23 Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out occures at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high (see Figure 24). MI MO MCS MCLK time SPI_DasyChain2.emf SO device 3 SI device 3 SO device 2 SI device 2 SO device 1 SI device 1 Figure 24 Data Transfer in Daisy Chain Configuration 10.3 Timing Diagrams tCS(lead) tCS(lag) tSCLK(P) tSCLK(H) tSCLK(L) 0.7Vdd 0.2Vdd tCS(td) 0.7Vdd 0.2Vdd CS SCLK tSI(su) tSI(h) SI tSO(en) tSO(v) tSO(dis) 0.7Vdd 0.2Vdd SO 0.7Vdd 0.2Vdd SPI Timing.emf Figure 25 Timing Diagram SPI Access Data Sheet 38 SCLK SPI_DasyChain.emf Rev. 1.3, 2007-10-30 SPOC - BTS5590G Serial Peripheral Interface (SPI) 10.4 Electrical Characteristics Electrical Characteristics SPI Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 °C to +150 °C, Vdd = 3.8 V to 5.5 V typical values: Vbb = 13.5 V, Tj = 25 °C, Vdd = 4.3 V Pos. Parameter Symbol Limit Values min. Input Characteristics (CS, SCLK, SI) 10.4.1 L level of pin CS VCS(L) SCLK VSCLK(L) SI VSI(L) 10.4.2 H level of pin CS VCS(H) SCLK VSCLK(H) SI VSI(H) 10.4.3 L-input pull-up current at CS pin 10.4.4 H-input pull-up current at CS pin ICS(L) ICS(H) Unit Test Conditions typ. max. V VDD = 4.3 V – – – VDD = 4.3 V – – – VDD = 4.3 V,VCS = 0 V VDD = 4.3 V,VCS = 2.6 V VDD = 4.3 V VSCLK = 0.4 V VSI = 0.4 V VDD = 4.3 V VSCLK = 4.3 V VSI = 4.3 V ISO = -0.5 mA ISO = 0.5 mA,VDD = 4.3 V VCS =VDD -0.3 -0.3 -0.3 2.6 2.6 2.6 10 3 3 3 10 10 0 VDD 0.5 V – – – – – – 30 – – – 30 30 – – – – – – – – – – – – – 1.0 1.0 1.0 V 5.5 5.5 5.5 85 85 75 75 µA 75 75 0.5 VDD µA µA µA 10.4.5 L-input pull-down current at pin SCLK ISCLK(L) SI ISI(L) 10.4.6 H-input pull-down current at pin SCLK ISCLK(H) SI ISI(H) Output Characteristics (SO) 10.4.7 L level output voltage 10.4.8 H level output voltage 10.4.9 Output tristate leakage current Timings 10.4.10 Serial clock freqency 10.4.11 Serial clock period 10.4.12 Serial clock high time 10.4.13 Serial clock low time fSCLK tSCLK(P) tSCLK(H) tSCLK(L) VSO(L) VSO(H) ISO(OFF) V V µA -10 0 1 500 500 1 1 2 100 100 – 10 1 – – – – – – – – 1 MHz – µs ns ns µs µs µs ns ns µs – – – – – – – – CL = 20 pF 1) 10.4.14 Enable lead time (falling CS to rising tCS(lead) SCLK) 10.4.15 Enable lag time (falling SCLK to rising CS) 10.4.16 Transfer delay time (rising CS to falling CS) tCS(lag) tCS(td) 10.4.17 Data setup time (required time SI to tSI(su) falling SCLK) 10.4.18 Data hold time (falling SCLK to SI) tSI(h) 10.4.19 Output enable time (falling CS to SO tSO(en) valid) Data Sheet 39 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Serial Peripheral Interface (SPI) Electrical Characteristics SPI Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 °C to +150 °C, Vdd = 3.8 V to 5.5 V typical values: Vbb = 13.5 V, Tj = 25 °C, Vdd = 4.3 V Pos. Parameter Symbol – – Limit Values min. 10.4.20 Output disable time (rising CS to SO tSO(dis) tri-state) 10.4.21 Output data valid time with capacitive load tSO(v) Unit Test Conditions 1 µs ns CL = 20 pF 1) CL = 20 pF 1) typ. – – max. 500 1) Not subject to production test, specified by design. Data Sheet 40 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Serial Peripheral Interface (SPI) 10.5 SPI Protocol CS1) 7 Write Register 1 Read Register 0 0 TER TER 0 1 x LHEN ADDR 6 ADDR ADDR x WDL x x ERR4 x x ERR3 5 4 3 2 DATA x x ERR2 DATA x x ERR1 0 1 ERR0 1 0 SI SI SI SO SO Read Standard Diagnosis Standard Diagnosis Second Frame of Read Command 1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition. Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame. Field TER Bits CS Type Description r Transmission Error 0 Previous transmission was successful (modulo 8 clocks received) 1 Previous transmission failed or first transmission after reset Address Pointer to register for read and write command Data Data written to or read from register selected by address ADDR Limp Home Enable 0 L-input signal at pin LHEN 1 H-input signal at pin LHEN Watchdog Lock 0 Watchdog can be served 1 Watchdog trigger state machine is locked Diagnosis of Channel x 0 No failure 1 Over temperature, over load or short circuit ADDR DATA LHEN 6:5 4:0 6 rw rw r WDL 5 r ERRx x = 4 to 0 x r Data Sheet 41 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Serial Peripheral Interface (SPI) 10.6 Name OUT WDLR HWCR DCR Register Overview W/R W/R R W R W W/R Addr 00B 01B 01B 10B 10B 11B LHO RST 0 4 OUT4 WDC WDTR WDL WDL 0 2) 3 OUT3 2 OUT2 LED2 LED2 SBM 0 1 OUT1 LED1 LED1 PWM PWM MUX 0 OUT0 LED0 LED0 CTL CTL default1) 00H 18H 00H 00H 00H 07H 1) The default values are set after reset. 2) Can be cleared only via SPI. The bit is set by internal signals. Data Sheet 42 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Application Description 11 Application Description Vbat 5V 500 Ω 100nF 68nF VDD VCC GPIO GPIO LHO 8k Ω 8k Ω VBB IN0 IN1 IN2 IN3 IN4 IS OUT0 OUT1 OUT2 OUT3 GND 3.3k Ω 27W 27W 27W 10W 10W µC AD 1k Ω 1nF OUT4 VDD SPI 2kΩ VBB Limp Home LHEN LHO LHD 470nF 2kΩ Ignition 20k Ω CS SCLK SO SI GND SPI 2kΩ 2kΩ 2kΩ LHO 10k Ω VSS 10k Ω Schottky 10nF.. 100nF CircuitWD .emf Figure 26 Application Circuit Example Data Sheet 43 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Package Outlines SPOC - BTS5590G 12 Package Outlines SPOC - BTS5590G 2.65 MAX. 0.35 x 45˚ 7.6 -0.2 0.23 +0.09 1) 0.2 -0.1 2.45 -0.2 0.65 0.33 ±0.08 2) 0.1 C 0.7 ±0.2 10.3 ±0.3 0.17 M C A-B D 36x D A 36 19 Bottom View 19 36 Ejector Mark 1 18 18 1 B 1) 12.8 -0.2 Index Marking Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side GPS01089 Figure 27 PG-DSO-36-34 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. 8˚ MAX. Dimensions in mm Data Sheet 44 Rev. 1.3, 2007-10-30 SPOC - BTS5590G Revision History 13 Revision 1.3 1.2 Revision History Date 07-10-30 07-08-28 Changes • • • • Chapter 7.1 Current limitation curves channels 0, 1 added Chapter 11 Package outline drawing changed 4.1 Conditions updated 4.1 and 6.4 : footnote change to : Specified RthJA value is according to Jedec JESD512,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). • • • • • 1.1 07-03-05 • • • • 4.1.4 Conditions updated 4.1.28 Definition change 5.2 Reset Command : tCS(td) change to : tCS(td). 8.4.3 New parameter : Current sense leakage / offset current Max Input Voltage value change to 40 Volts Product summary Green Product (ROHS compliant) and AEC Qualified added 4.1.12 Current through input pins min value change to -0.75mA 4.1.21 Current through limp home enable pin min value change to -0.75mA Chapter9.1 In case of fast VBB transients between VBB(WD memory)min and VBB(WD) min voltage and VLHD > VLHD(R) the watchdog capacitor CWD is only discharged as long as the voltage is below VBB(WD) min. I.e. in case of very short transients the charging or discharging process will continue after the disturbance with the same mode (charging or discharging) as before the voltage break down as long as VLHD > VLHD(R). Chapter 5.3 New parameter defined : VBB(WD memory) Chapter 6 Ron definition changed Chapter 9.2 DCR change to WDLR Chapter 7.2 (also even in case of Vdd = 0V) added. Basic Feature : Green Logo added Chapter 8.1 In case of high duty cyle ( off state of output < toff state_min) the VDS might not be equal to VBB during the off state of the power Mosfet. The over load monitoring signals might be set and latched in the error flags. See Application Note “ Software Strategy for Diagnosis during PWM-Operation“ for more details Table 8.4.10 Off stateTime during PWM operation definition Chapter 11 68nF added between VBB and Gnd page 18: register read value added New template DIN A4 V1.2 • • • • • • • • • • Data Sheet 45 Rev. 1.3, 2007-10-30 Edition 2007-10-30 Published by Infineon Technologies AG 81726 Munich, Germany © 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.