BTS6480SF

SPI Power Controller SPOC - BTS6480SF For Advanced Front Light Control Data Sheet Rev. 1.0, 2010-04-12 Automotive Power SPOC - BTS6480SF Table of Contents Table of Contents 1 2 2.1 3 3.1 3.2 4 4.1 4.2 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9 9.1 9.2 9.3 9.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Assignment SPOC - BTS6480SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inverse Current Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Phase Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Operation with PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Current Protection at high VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Current Protection for Short Circuit Type 2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Synchronization during Automatic PWM Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Measurement without Synchronization Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 13 14 15 16 17 17 17 19 20 21 22 26 27 27 27 28 28 29 31 32 35 35 37 37 38 40 40 41 41 42 44 45 46 46 49 50 Data Sheet Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Table of Contents 9.5 9.6 9.7 9.8 9.9 10 10.1 10.2 10.3 10.4 10.5 10.6 11 12 13 Automatic Current Sense Multiplexer Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load in OFF-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol 16Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 51 52 53 56 59 59 60 61 62 64 66 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Package Outlines SPOC - BTS6480SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Data Sheet 3 Rev. 1.0, 2010-04-12 For Advanced Front Light Control SPI Power Controller SPOC - BTS6480SF 1 Features • • • • • • • • • • Overview 16 bit serial peripheral interface for control and diagnosis Integrated PWM generator Integrated control for two external smart power switches 3.3 V and 5 V compatible logic pins Very low stand-by current Enhanced electromagnetic compatibility (EMC) for bulbs as well as LEDs with increased slew rate Stable behavior at under voltage Device ground independent from load ground Green Product (RoHS-Compliant) AEC Qualified PG-DSO-36-43 Description The SPOC - BTS6480SF is a four channel high-side smart power switch in PG-DSO-36-43 package providing embedded protective functions. It is especially designed to control standard exterior lighting in automotive applications. In order to use the same hardware, the device can be configured to bulb or LED mode for channel 2 and channel 3. As a result, both load types are optimized in terms of switching and diagnosis behavior. It is specially designed to drive exterior lamps up to 65W, 27W and 10W and HIDL. Product Summary Operating Voltage Power Switch Logic Supply Voltage Supply Voltage for Load Dump Protection Maximum Stand-By Current at 25 °C Typical On-State Resistance at Tj = 25 °C channel 0, 1 channel 2, 3 Maximum On-State Resistance at Tj = 150 °C channel 0, 1 channel 2, 3 SPI Access Frequency VBB VDD VBB(LD) IBB(STB) RDS(ON,typ) 4.5 … 28 V 3.0 … 5.5 V 40 V 4.5 µA 3.5 mΩ 11 mΩ 9 mΩ 28 mΩ 5 MHz RDS(ON,max) fSCLK(max) Type SPOC - BTS6480SF Data Sheet Package PG-DSO-36-43 4 Marking BTS6480SF Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Overview Configuration and status diagnosis are done via SPI. The SPI is daisy chain capable. The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be enabled and disabled via SPI commands. An over load and over temperature flag is provided in the SPI diagnosis word. A multiplexed switch bypass monitor provides short-circuit to VBB diagnosis. In OFF state a current source can be switched to the output of one selected channel in order to detect an open load. Additionally, there is an integrated PWM generator implemented, which allows autonomous PWM operation with programmable phase shifts, duty cycles and PWM frequencies. The status diagnosis and the current sense signal is available for each channel. The device provides an external driver capability for two external devices. For each external driver there are two control outputs available: one output for controlling the input and one output for diagnosis enable input. The current sense output of the external smart power drivers can be connected to the IS pin. The external drivers can be controlled by the automatic PWM generator as well. The SPOC - BTS6480SF provides a fail-safe feature via limp home input pin. The power transistors are built by N-channel vertical power MOSFETs with charge pumps. Protective Functions • • • • • • • • • Reverse battery protection with external components ReversaveTM - Reverse battery protection by self turn on of channels 0, 1, 2 and 3 Short circuit protection Over load protection Thermal shutdown with latch and dynamic temperature sensor Over current tripping Over voltage protection Loss of ground protection Electrostatic discharge protection (ESD) Diagnostic Functions • • • • • • • • Multiplexed proportional load current sense signal (IS) Enable function for current sense signal configurable via SPI High accuracy of current sense signal at wide load current range Current sense ratio (kILIS) configurable for LEDs or bulbs for channel 2 and 3 Very fast diagnosis in LED mode Feedback on over temperature and over load via SPI Multiplexed switch bypass monitor provides short circuit to VBB detection Integrated, in two steps programmable current source for open load in OFF-state detection Application Specific Functions • • Fail-safe activation via LHI pin Control of two additional loads with external smart power switches Applications • • • • High-side power switch for 12 V grounded loads in automotive applications Especially designed for standard exterior lighting like high beam, low beam, indicator, parking light and equivalent LEDs Load type configuration via SPI (bulbs or LEDs) for optimized load control Replaces electromechanical relays, fuses and discrete circuits Data Sheet 5 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Block Diagram 2 Block Diagram VBB power supply VDD temperature sensor driver logic gate control & charge pump load current sense IN1 IN2 IN3 clamp for inductive load over current protection channel 0 1 2 3 OUT3 OUT2 OUT1 OUT0 EDO0 IS ISSY PCLK LHI CS SCLK SO SI SPI ESD protection current sense multiplexer limp home control PWM generator switch bypass monitor LED mode control external driver control ESD protection EDD0 EDO1 EDD1 GND Figure 1 Block Diagram SPOC - BTS6480SF Data Sheet 6 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Block Diagram 2.1 Terms Figure 2 shows all terms used in this data sheet. VBB I DD VDD VSO VSI V CS VSCLK VLHI VPCLK I SO I SI ICS ISCLK ILHI IPCLK I BB VBB VDD S0 SI CS SCLK OUT1 LHI I L2 PCLK OUT2 VOUT2 OUT3 I L3 VDS3 VOUT3 EDO0 EDD0 IS ISSY GND I GND EDO1 EDD1 I EDO0 I EDD0 I EDO1 I EDD1 V EDO0 VEDD0 VEDO1 VEDD1 VDS2 OUT0 I L0 VDS0 VOUT0 I L1 V DS1 VOUT1 I IN1 VIN1 V IN2 VIN3 I IS VIS IISSY VISSY I IN2 I IN3 IN1 IN2 IN3 Terms_PWM_EXT .emf Figure 2 Terms In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS0 … VDS3). All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.CL). In SPI register description, the values in bold letters (e.g. 0) are default values. Data Sheet 7 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Pin Configuration 3 3.1 Pin Configuration Pin Assignment SPOC - BTS6480SF (top view) VBB VBB OUT0 OUT0 OUT0 OUT0 OUT3 OUT3 VBB LHI SO SI SCLK CS GND IN1 IN2 IN3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VBB VBB OUT1 OUT1 OUT1 OUT1 OUT2 OUT2 VBB PCLK EDO0 EDD0 EDO1 EDD1 GND IS ISSY VDD Figure 3 Pin Configuration PG-DSO-36-43 Data Sheet 8 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Pin Configuration 3.2 Pin Pin Definitions and Functions Symbol VBB VDD GND IN1 IN2 IN3 OUT0 2) I/O – – – I I I O O O O I I I O I O O I O O O O Function Positive power supply for high-side power switch Logic supply (5 V) Ground connection Input signal of channel 1 (high active) Input signal of channel 2 (high active) Input signal of channel 3 (high active) Protected high-side power output of channel 0 Protected high-side power output of channel 1 Protected high-side power output of channel 2 Protected high-side power output of channel 3 Chip select of SPI interface (low active); Integrated pull up Serial clock of SPI interface Serial input of SPI interface (high active) Serial output of SPI interface PWM clock reference signal Current sense output signal Current sense synchronization signal Limp home activation signal (high active) External driver output for activation of external driver 0 External driver output for activation of external driver 1 External driver diagnosis enable signal of external driver 0 External driver diagnosis enable signal of external driver 1 Power Supply Pins 1, 2, 9, 28, 35, 36 1) 19 15, 22 16 17 18 Power Output Pins 3, 4, 5, 6 2) 31, 32, 33, 34 29, 30 7, 8 14 13 12 11 27 21 20 10 26 24 25 23 2) 2) Parallel Input Pins (integrated pull-down, leave unused pins unconnected) OUT1 OUT2 OUT3 CS SCLK SI SO PCLK IS ISSY LHI EDO0 EDO1 EDD0 EDD1 SPI, PWM & Diagnosis Pins Limp Home Pin (integrated pull-down, pull-down resistor recommended) External Driver Pins (integrated pull-down, leave unused external driver pins unconnected) 1) All VBB pins have to be connected. 2) All outputs pins of each channel have to be connected. Data Sheet 9 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Electrical Characteristics 4 4.1 Electrical Characteristics Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 to +150 °C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values min. Supply Voltage 4.1.1 4.1.2 4.1.3 4.1.4 Power supply voltage Logic supply voltage Reverse polarity voltage according Figure 30 max. 28 5.5 16 V V V – – Unit Conditions VBB VDD -Vbat(rev) -0.3 -0.3 – Supply voltage for short circuit protection (single VBB(SC) pulse) channel 0, 1 channel 2, 3 0 0 24 24 40 25 12 IL(LIM) 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 Supply voltage for load dump protection with connected loads Current through ground pin Current through VDD pin Load current Maximum energy dissipation single pulse channel 0, 1 channel 2, 3 VBB(LD) IGND IDD IL EAS – – -25 -IL(LIM) TjStart = 25 °C t ≤ 2 min. 2) V RECU = 20 mΩ l = 0 o r 5 m 3) RCable = 6 mΩ/m LCable = 1 µH/m RCable = 16 mΩ/m LCable = 1 µH/m V RI = 2 Ω 4) t = 400 ms mA t ≤ 2 min. mA t ≤ 2 min. A mJ 5) 6) Power Stages – – 180 45 8 5.5 0.75 2.0 Tj(0) = 150 °C IL(0) = 5 A IL(0) = 2 A mA t ≤ 2 min. V – Diagnosis Pin 4.1.10 Current through sense pin IS Input Pins 4.1.11 Voltage at input pins 4.1.12 Current through input pins SPI Pins 4.1.13 Voltage at chip select pin 4.1.14 Current through chip select pin 4.1.15 Voltage at serial input pin 4.1.16 Current through serial input pin 4.1.17 Voltage at serial clock pin 4.1.18 Current through serial clock pin 4.1.19 Voltage at serial out pin Data Sheet 10 IIS VIN IIN -8 -0.3 -0.75 -2.0 -0.3 -2.0 -0.3 -2.0 -0.3 -2.0 -0.3 mA – t ≤ 2 min. – – – – Rev. 1.0, 2010-04-12 VCS ICS VSI ISI VSCLK ISCLK VSO VDD + 0.3 V 2.0 2.0 2.0 mA t ≤ 2 min. mA t ≤ 2 min. mA t ≤ 2 min. VDD + 0.3 V VDD + 0.3 V VDD + 0.3 V SPOC - BTS6480SF Electrical Characteristics Absolute Maximum Ratings (cont’d)1) Tj = -40 to +150 °C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values min. 4.1.20 Current through serial output pin SO PWM Clock and Sense Synchronization Pin 4.1.21 Voltage at PWM clock input pin 4.1.22 Current through PWM clock input pin 4.1.23 Voltage at sense synchronization pin 4.1.24 Current through sense synchronization pin Limp Home Pin 4.1.25 Voltage at limp home input pin 4.1.26 Current through limp home input pin External Driver Pins max. 2.0 mA t ≤ 2 min. – -2.0 -0.3 -0.75 -2.0 -0.3 -2.0 -0.3 -0.75 -2.0 -0.3 -1.0 -0.3 -1.0 -40 – -55 Unit Conditions ISO VPCLK IPLCK VISSY IISSY VLHI ILHI VDD + 0.3 V 0.75 2.0 2.0 5.5 0.75 2.0 mA – t ≤ 2 min. – mA t ≤ 2 min. V – VDD + 0.3 V mA – t ≤ 2 min. – – VEDO 4.1.28 Current through external driver output IEDO 4.1.29 Voltage at external driver diagnosis enable VEDD 4.1.30 Current through external driver diagnosis enable IEDD 4.1.27 Voltage at external driver output Temperatures 4.1.31 Junction temperature 4.1.32 Dynamic temperature increase while switching 4.1.33 Storage temperature ESD Susceptibility 4.1.34 ESD susceptibility HBM OUT pins vs. VBB other pins incl. OUT vs. GND VDD + 0.3 V 1.0 1.0 150 60 150 mA t ≤ 2 min. mA t ≤ 2 min. °C K °C kV – – – HBM 7) – – VDD + 0.3 V Tj ∆Tj Tstg VESD -4 -2 4 2 1) Not subject to production test, specified by design. 2) Device is mounted on an FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. 3) In accordance to AEC Q100-012 and AEC Q101-006. 4) RI is the internal resistance of the load dump pulse generator. 5) Over current protection is a protection feature. Operation in over current protection is considered as “outside” normal operating range. Protection features are not designed for continuous repetitive operation. 6) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse 7) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5 kΩ, 100 pF) Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 11 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Electrical Characteristics 4.2 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. 4.2.1 4.2.2 Parameter Junction to Soldering Point Junction to Ambient 1) 1) Symbol Min. Limit Values Typ. – 35 Max. 20 – – – Unit K/W K/W Conditions measured to pin 1, 2, 9, 28, 35, 36 2) RthJSP RthJA 1) Not subject to production test, specified by design. 2) Specified RthJA values is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. Data Sheet 12 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Supply 5 Power Supply The SPOC - BTS6480SF is supplied by two supply voltages VBB and VDD. The VBB supply line is used by the power switches. The VDD supply line is used by the SPI related circuitry and for driving the SO line. A capacitor between pins VDD and GND is recommended as shown in Figure 30. There is a power-on reset function implemented for the VDD logic power supply. After start-up of the logic power supply, all SPI registers are reset to their default values. The SPI interface including daisy chain function is active as soon as VDD is provided in the specified range independent of VBB. First SPI data are the output register values with TER = 1. Specified parameters are valid for the supply voltage range according VBB(nor) or otherwise specified. For the extended supply voltage range according VBB(ext) device functionality (switching, diagnosis and protection functions) are still given, parameter deviations are possible. 5.1 Power Supply Modes The following table shows all possible power supply modes for VBB, VDD and the pin LHI. Power Supply Modes Off Off SPI on 0V 5V 0V – – ✓ – – – Reset Off On via Limp Home Normal operation INx mode without SPI 13.5 V 5V 0V ✓ – ✓ ✓5) ✓6) ✓ 0V 0V ✓ – reset ✓4) – – 2) Limp Home mode with SPI 1) 13.5 V 5V 5V ✓2) ✓ reset3) – – ✓7) VBB VDD LHI Power stage, protection Limp home SPI (logic) Stand-by current Idle current Diagnosis 1) 2) 3) 4) 5) 6) 7) 0V 0V 0V – – – – – – 0V 0V 5V – – – – – – 0V 5V 5V – – ✓ – – – 13.5 V 13.5 V 13.5 V 0V 0V – – reset ✓ – – 0V 5V ✓ ✓ reset – – – 2) SPI read only Channel 1, 2 and/or 3 activated according to the state of INx SPI reset only with applied VBB voltage When INx = low When DCR.MUX = 111b, INx = low and PCR.PST = 0b When all channels are in OFF-state and DCR.MUX ≠ 111b Current sense disabled in limp home mode 5.1.1 Stand-by Mode and Device Wake-up Mechanisms Stand-by mode is entered as soon as the current sense multiplexer (DCR.MUX) is in default (stand-by) position, the PWM start bit is reset (PCR.PST = 0b) and all input pins are not set. All error latches are cleared automatically in stand-by mode. As soon as stand-by mode is entered, register HWCR.STB is set. To wake-up the device, the current sense multiplexer (DCR.MUX) is programmed different to default (stand-by) position or the PWM start bit is set (PCR.PST = 1b). The power-on wake up time tWU(PO) has to be considered for both cases. Idle mode parameters are valid, when all channels are switched off, but the current sense multiplexer is not in default position, and VDD supply is available. Note: A transition from operation to stand-by mode does not reset the SPI registers. So, if VDD is present and SPI is programmed, a changing to MUX = 111b does not reset the SPI registers. An activation of the channels via the input pin INx will wake up the device with the former SPI register settings. Data Sheet 13 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Supply Activating one of the outputs via the input pins (INx = high) will wake-up the device out of stand-by mode. The power stages are working without VDD supply according to the table above. The output turn-on times will be extended by the stand-by channel wake up time tWU(STCH) as long as no other channel is active. If one channel is active already before channel turn-on times ton (6.6.12) can be considered. Note: In the operation with VDD = 0 V and INx = high a switching off of all input signals will turn the device in standby mode. In stand-by mode the error latches are cleared. Limp home (LHI = high) applied for a time longer than tLH(ac) will wake-up the device out of stand-by mode after the power-on wake up time tWU(PO) and it is working without VDD supply. Channels 1, 2 and 3 can be activated via the input pins INx. The error latches can be cleared by a low-high transition at the according input pin. 5.2 Reset There are several reset trigger implemented in the device. They reset the SPI registers including the over temperature latches to their default values. The power stages will switch off, if they are activated via the SPI register OUT.n. If the power stages are activated via the parallel input pins they are not affected by the reset signals. The ERR-flags are cleared by those reset triggers. The over temperature protection and latches are functional after a reset trigger. Note: During a reset only the channels 1, 2 and 3 can be activated via the according input pins. The input assigned mode is not available during a reset. The first SPI transmission after any kind of reset contains at pin SO the read information from the standard diagnosis, the transmission error bit TER is set. Power-On Reset The power-on reset is released, when VDD voltage level is higher than VDD(PO). The SPI interface can be accessed after wake up time tWU(PO). Reset Command There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As soon as HWCR.RST = 1b, a reset is triggered equivalent to power-on reset. The SPI interface can be accessed after transfer delay time tCS(td). Limp Home Mode The limp home mode will be activated as soon as the pin LHI is set to high for a time longer than tLH(ac). The SPI write-registers are reset with applied VBB voltage. The outputs OUTx can be activated via the input pins also during activated limp home mode. The error latches can be cleared by a low-high transition at the according input pin. For application example see Figure 30. The SPI interface is operating normally, so the limp home register bit LHI as well as the error flags can be read, but any write command will be ignored. Data Sheet 14 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Supply 5.3 Electrical Characteristics Electrical Characteristics Power Supply Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter 5.3.1 Supply voltage range for normal operation power switch Symbol Limit Values min. typ. – – max. 17 281) V V µA – – 5.3.4 Idle current for whole device with loads, all channels off 5.3.5 Logic supply voltage 5.3.6 Logic supply current – – 7 – 4.5 28 – 5.5 mA V µA – Parameter deviations possible 8 4.5 Unit Test Conditions VBB(nor) 5.3.2 Extended supply voltage range for operation VBB(ext) power switch 5.3.3 Stand-by current for whole device with loads IBB(STB) IBB(idle) VDD IDD – 3.0 VDD = 0 V VLHI = 0 V 1) Tj = 25 °C 1) Tj ≤ 85 °C VDD = 5 V DCR.MUX = 110 – – – 5.3.7 Logic idle current 140 280 25 – – – µA IDD(idle) – VCS = VLHI = 0 V RIS = 2.7 kΩ VIS = 0 V fSCLK = 0 Hz fSCLK = 5 MHz VCS = VDD fSCLK = 0 Hz Chip in Standby 5.3.8 Operating current for whole device active LHI Input Characteristics 5.3.9 L-input level at LHI pin 5.3.10 H-input level at LHI pin 5.3.11 L-input current through LHI pin 5.3.12 H-input current through LHI pin Reset 5.3.13 Power-On reset threshold voltage 5.3.14 Power-On wake up time 5.3.15 Stand-by channel wake up time 5.3.16 Limp home acknowledgement time 1) Not subject to production test, specified by design. IGND VLHI(L) VLHI(H) ILHI(L) ILHI(H) VDD(PO) tWU(PO) tWU(STCH) tLH(ac) – 0 1.8 3 10 – – – 5 10 – – 12 40 – – – – 25 0.8 5.5 80 80 2.4 200 200 200 mA V V µA µA V µs µs µs fSCLK = 0 Hz – – 1) VLHI = 0.4 V VLHI = 5 V – 1) 1) 1) Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Data Sheet 15 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Supply 5.4 Command Description HWCR Hardware Configuration Register 1) W/R 2) read write RB2) 1 1 0 0 ADDR2) 0 0 1 1 0 0 9 0 0 8 7 CLKTRIM CLKTRIM 6 5 CLK CLK 4 0 0 3 2 1 STB RST 0 CL CL LED3 LED2 LED3 LED2 1) Shaded cells not mentioned in this chapter. 2) W/R Write/Read, RB Register Bank, ADDR Address Field RST Bits 1 Type w Description Reset Command 0 1) Normal operation 1 Execute reset command Stand-by 0 Device is awake 1 Device is in stand-by mode STB 1 r 1) Bold letters indicate the default values. Data Sheet 16 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Stages 6 Power Stages The high-side power stages are built by N-channel vertical power MOSFETs (DMOS) with charge pumps. There are four channels implemented in the device. Channels can be switched on via an input pin (please refer to Section 6.2) or via SPI register OUT. 6.1 Output ON-State Resistance The on-state resistance RDS(ON) depends on the supply voltage VBB as well as on the junction temperature Tj. Figure 4 shows those dependencies. The behavior in reverse polarity mode is described in Section 8.5. VBB = 13.5 V 50 45 40 35 Tj = 25 °C 50 Channel 0,1 (bulb) Channel 2,3 (bulb) Channel 2,3 (LED) 45 40 35 RDS(ON) [mΩ ] 30 25 20 15 10 5 0 Channel 0, 1 (bulb) channel 2,3 (bulb) channel 2,3 (LED) RDS(ON) [mΩ ] 30 25 20 15 10 5 0 -50 0 50 T j [°C] 100 150 0 5 10 15 VBB [V] 20 25 30 Figure 4 Typical On-State Resistance 6.2 Input Circuit The outputs of the SPOC - BTS6480SF can be activated either via the SPI register OUT.OUTn or via the dedicated input pins. There are two different ways to use the input pins, the direct drive mode and the assigned drive mode. The default setting is the direct drive mode. To activate the assigned drive mode the register bit IECR.INCG needs to be set. Additionally, there are two ways of using the input pins in combination with the OUT register by programming the IECR.COL parameter. • • IECR.COL = 0b: A channel is switched on either by the according OUT register bit or the input pin. IECR.COL = 1b: A channel is switched on by the according OUT register bit only, when the input pin is high. In this configuration, a PWM signal can be applied to the input pin and the channel is activated by the SPI register OUT. Data Sheet 17 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Stages Figure 5 shows the complete input switch matrix. OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 PWM Generator OFF/ ON FREQ-values ch2 ch3 PWM signals ch0 ch1 ch2 ch3 ch4 ch5 ch0 ch1 ch4 ch5 & FREQ1 FREQ0 PST OR & channel 0 OR & Gate Driver 0 IN1 OR & Gate Driver 1 IN2 OR & Gate Driver 2 IN3 OR OR & Gate Driver 3 OR & External Driver Output 0 OR & External Driver Output 1 INCG COL & InputMatrix_PWM_EXT .emf Figure 5 Input Switch Matrix The current sink to ground ensures that the input signal is low in case of an open input pin. The zener diode protects the input circuit against ESD pulses. Data Sheet 18 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Stages 6.2.1 Input Direct Drive This mode is the default after the device’s wake up and reset. The input pins activate the channels during normal operation (with default setting of bit IECR.INCG), stand-by mode and limp home mode. Channel 0 and the external drivers can be activated only via the SPI-bit OUT.OUTn in direct drive mode. The inputs are linked directly to the channels according to: Table 1 Input Pin IN1 IN2 IN3 Direct Drive Mode Assigned channel, if IECR.INCG = 0b Channel 1 Channel 2 Channel 3 6.2.2 Input Assigned Drive To activate the assigned drive function the register bit IECR.INCG needs to be set. In this mode all output channels can be activated via the input pins. Channel 2, 3 and the two external drivers are assigned to only one input pin. The following mapping is used: Table 2 Input Pin IN1 IN2 IN3 Assigned Drive Mode Assigned channel, if IECR.INCG = 1b Channel 0 Channel 1 Channel 2, channel 3, external driver 0, external driver 1 6.3 Power Stage Output The power stages are built to be used in high side configuration (Figure 6). VBB VDS VBB OUT GND VOUT Outputemf . Figure 6 Power Stage Output The power DMOS switches with a dedicated slope, which is optimized in terms of EMC emission. Defined slew rates and edge shaping allow lowest EMC emissions during PWM operation at low switching losses. Data Sheet 19 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Stages 6.3.1 Bulb and LED mode Channel 2 and channel 3 can be configured in bulb and LED mode via the SPI registers HWCR.LEDn. During LED mode following parameters are changed for an optimized functionality with LED loads: On-state resistance RDS(ON), switching timings (tdelay(ON), tdelay(OFF), tON, tOFF), slew rates dV/dtON and dV/dtOFF, current protections IL(trip) and current sense ratio kILIS. 6.3.2 Switching Resistive Loads When switching resistive loads the following switching times and slew rates can be considered. IN / OUTx t ON V OUT 90% of V BB 70% of V BB 70% tOFF tON(rise) tdelay(OFF ) t OFF (f all) t t delay(ON ) dV / dtON 30% of V BB 10% of V BB dV / dt OFF 30% t SwitchOn.emf Figure 7 Switching a Load (resistive) 6.3.3 Switching Inductive Loads When switching off inductive loads with high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to high voltages, there is a voltage clamp mechanism implemented, which limits that negative output voltage to a certain level (VDS(CL) (6.6.2)). See Figure 6 for details. The device provides SmartClamp functionality. To increase the energy capability, the clamp voltage VDS(CL) increases with the junction temperature Tj and load current IL. Please refer also to Section 8.6. The maximum allowed load inductance is limited. 6.4 Inverse Current Behavior During inverse currents (VOUT > VBB) the affected channel stays in ON- or in OFF-state. Furthermore, during applied inverse currents no ERR-flag is set. The functionality of unaffected channels is not influenced by inverse currents applied to other channels (except effects due to junction temperature increase). Influences on the diagnostic function of unaffected channels are possible only for the current sense ratio, please refer to ∆kILIS(IC) (9.8.3). Note: No protection mechanism like temperature protection or current protection is active during applied inverse currents. Inverse currents cause power losses inside the DMOS, which increase the overall device temperature, which could lead to a switch off of the unaffected channels due to over temperature. Data Sheet 20 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Stages 6.5 External Driver Control Two external smart power drivers can be driven by the SPOC - BTS6480SF via the external driver control block. For each external driver there are two control outputs available: one output for controlling the input (EDOx) and one output for diagnosis enable input (EDDx). The current sense output of the external smart power drivers can be connected to the IS pin. For details please refer to Figure 30. The external driver outputs can be used only with applied VDD voltage. The external driver outputs are internally pulled down. The external drivers can be activated via SPI-bits OUT.OUT4 and OUT.OUT5 or via the input pin IN3 in assigned drive mode. They will be served as well by the integrated automatic PWM-generation. Therefore, the according PWM-frequency and duty cycle needs to be programmed. For performing diagnosis on the external drivers they can be selected via the SPI register DCR.MUX. For being compliant to PROFET+ diagnostic functions, it is possible to configure pin EDD0 as DEN and EDD1 as DSEL. Therefore, the bit IECR.PRO+ needs to be set. The DSEL will be set depending on the multiplexer setting DCR.MUX. Table 3 PROFET+ Compliancy EDD0 used as DEN 1 1 EDD1 used as DSEL 0 1 MUX Setting DCR.MUX 100b 101b Note: The usable duty cycle range and diagnostic timings for the external drivers depend on the external driver’s characteristics. Data Sheet 21 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Stages 6.6 Electrical Characteristics Electrical Characteristics Power Stages Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Output Characteristics 6.6.1 On-state resistance channel 0, 1 – – channel 2, 3 – – 11 22 – 28 3.5 7 – 9 Symbol Limit Values min. typ. max. Unit Test Conditions RDS(ON) mΩ IL = 7.5 A 1) Tj = 25 °C Tj = 150 °C HWCR.LEDn = 0 IL = 2.6 A 1) Tj = 25 °C Tj = 150 °C HWCR.LEDn = 1 – – 6.6.2 Output clamp channel 0, 1 39 78 – – – – – 100 V 54 55 54 55 µA IL = 0.6 A 1) Tj = 25 °C Tj = 150 °C Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 6 A Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 2 A OUT.OUTn = 0 DCR.MUX = 111 VDS(CL) 32 40 channel 2, 3 32 40 6.6.3 Output leakage current per channel in stand-by channel 0, 1 IL(OFFSTB) – – – – – – – – – – – – 2 10 50 1 4 20 channel 2, 3 Tj = 25 °C 1) Tj = 85 °C 1) Tj = 105 °C Tj = 25 °C 1) Tj = 85 °C 1) Tj = 105 °C µA OUT.OUTn = 0 DCR.MUX ≠ 111 1) 1) 6.6.4 Output leakage current per channel in idle IL(OFFidle) mode channel 0, 1 – – – – – – – – – – – – 60 80 530 45 50 230 channel 2, 3 Tj = 150 °C 1) Tj = 85 °C 1) Tj = 105 °C Tj = 150 °C Tj = 85 °C Tj = 105 °C Data Sheet 22 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Stages Electrical Characteristics Power Stages (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter 6.6.5 Inverse current capability per channel channel 0, 1 channel 2, 3 Input Characteristics 6.6.6 L-input level 6.6.7 H-input level 6.6.8 L-input current 6.6.9 H-input current Symbol Limit Values min. typ. max. Unit Test Conditions A 6 2 – – – – No influences on switching functionality of unaffected channels, kILIS influence according ∆kILIS(IC) (9.8.3) – – 1) 1) -IL(IC) VIN(L) VIN(H) IIN(L) IIN(H) 0 1.8 3 10 – – 12 40 0.8 5.5 80 80 V V µA µA VIN = 0.4 V VIN = 5 V Data Sheet 23 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Stages Electrical Characteristics Power Stages (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Timings 6.6.10 Turn-ON delay to 10% VBB channel 0, 1 channel 2, 3 6.6.11 Turn-OFF delay to 90% VBB channel 0, 1 channel 2, 3 6.6.12 Turn-ON time to 90% VBB including turn-ON delay channel 0, 1 channel 2, 3 Symbol Limit Values min. typ. max. Unit Test Conditions tdelay(ON) – – – 25 20 12 75 50 20 – – – µs 1) VBB = 13.5 V – HWCR.LEDn = 0 HWCR.LEDn = 1 µs 1) tdelay(OFF) – – – – – – VBB = 13.5 V – HWCR.LEDn = 0 HWCR.LEDn = 1 µs tON – – – – – – 100 100 50 VBB = 13.5 V RL = 2.2 Ω DCR.MUX ≠ 111 HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω µs 6.6.13 Turn-OFF time to 10% VBB including turn-OFF delay channel 0, 1 channel 2, 3 tOFF – – – – – – 150 110 50 VBB = 13.5 V RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω 6.6.14 Turn-ON rise time from 10% to 90% VBB channel 0, 1 channel 2, 3 tON(rise) – – – – – – 55 55 11 µs VBB = 13.5 V RL = 2.2 Ω DCR.MUX ≠ 111 HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω µs 6.6.15 Turn-OFF fall time from 90% to 10% VBB channel 0, 1 channel 2, 3 tOFF(fall) – – – – – – 55 55 11 VBB = 13.5 V RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω Data Sheet 24 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Stages Electrical Characteristics Power Stages (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter 6.6.16 Turn-ON/OFF matching channel 0, 1 channel 2, 3 Symbol |tON tOFF| Limit Values min. typ. max. Unit Test Conditions µs VBB = 13.5 V RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω – – – – – – 90 70 50 6.6.17 Turn-ON slew rate 30% to 70% VBB channel 0, 1 channel 2, 3 dV/ dtON 0.2 0.2 0.6 0.7 0.9 2.5 2.0 2.5 6.0 V/µs VBB = 13.5 V RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω V/µs VBB = 13.5 V 6.6.18 Turn-OFF slew rate 70% to 30% VBB channel 0, 1 channel 2, 3 -dV/ dtOFF 0.2 0.2 0.6 0.7 0.9 2.5 2.0 2.5 6.0 RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω V V µs µs V V µs µs External Driver Control 6.6.19 L level external driver output voltage 6.6.20 H level external driver output voltage 6.6.21 External driver output enable time 6.6.22 External driver output disable time 6.6.23 L level external driver diagnosis enable voltage 6.6.24 H level external driver diagnosis enable voltage 6.6.25 External driver diagnosis enable enable time 6.6.26 External driver diagnosis enable disable time 1) Not subject to production test, specified by design. VEDO(L) VEDO(H) tEDO(en) tEDO(dis) VEDD(L) VEDD(H) tEDD(en) tEDD(dis) 0 – 0.4 VDD VDD - – 0.4V – – 0 – – – 4 4 0.4 VDD IEDO = -0.5 mA IEDO = 0.5 mA VDD = 4.3 V 1) CL = 20 pF 1) CL = 20 pF IEDD = -0.5 mA IEDD = 0.5 mA VDD = 4.3 V 1) CL = 20 pF 1) VDD - – 0.4V – – – – 4 4 CL = 20 pF Data Sheet 25 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Power Stages 6.7 Command Description OUT Output Configuration Registers W/R r/w RB 0 0 0 ADDR 0 0 9 0 8 0 7 0 6 0 5 4 3 2 1 0 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 Field OUTn n = 5 to 0 Bits n Type rw Description Set Output Mode for Channel n 0 Channel n is switched off 1 Channel n is switched on 1) 1) Channel status depends on automatic PWM generator configuration. For more details, please refer to Section 7. HWCR Hardware Configuration Register W/R r/w RB 1 0 0 ADDR 1 0 9 0 8 7 CLKTRIM 6 5 CLK 4 0 3 2 1 STB 0 CL LED3 LED2 Field LEDn n = 3 to 2 Bits n Type rw Description Set LED Mode for Channel n 0 Channel n is in bulb mode 1 Channel n is in LED mode IECR Input, External Drive and Current Source Configuration Register W/R r/w RB 1 0 0 ADDR 0 1 9 0 8 0 7 0 6 0 5 0 4 0 3 COL 2 INCG 1 CSL 0 PRO+ Field PRO+ Bits 0 Type rw Description Configuration of EDD0 and EDD1 to be Compliant to PROFET+ 0 Normal mode 1 EDD0=DEN, EDD1=DSEL Input Drive Configuration 0 Direct drive mode 1 Assigned drive mode Input Combinatorial Logic Configuration 0 Input signal OR-combined with according OUT register bit 1 Input signal AND-combined with according OUT register bit INCG 2 rw COL 3 rw Data Sheet 26 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Automatic PWM Generator 7 Automatic PWM Generator The SPOC - BTS6480SF has an automatic PWM generator implemented, which allows to operate the channels in PWM mode with drastically reduced micro controller attention compared to a conventional PWM generation via SPI. After the initializing phase, where different settings are done, the PWM generator works autonomously. The only required information from the micro controller is the PWM duty cycle and the channel states (ON-state or OFF-state). For details about the current sense diagnosis please refer to Chapter 9. 7.1 PWM Setup The PWM operation mode is available for each output. The register CHCRn.FREQ is used to switch from normal mode to automatic PWM generation mode. With CHCRn.FREQ = 00b the output state is following the OUTn register value. For details please refer to Figure 5. To start the automatic PWM generation the bit PCR.PST has to be set. For details please refer to Figure 8. The device can be woken up also out of stand-by mode by setting the bit PCR.PST. Therefore, the power-on wake up time tWU(PO) (5.3.14) has to be considered as delay until the automatic PWM generation will start. 7.2 PWM Clock The output PWM frequency fPWM can be derived from an external clock fPCLK, which is applied at the pin PCLK, or from an internal clock fINT. The source for the PWM clock can be selected by the SPI register HWCR.CLK. Note: For avoiding skews it is recommended to change from external to internal clock source or vice versa only during deactivated PWM generator (PCR.PST = 0b). 7.2.1 External PWM Clock The output PWM frequency is generated from the PWM clock input signal fPCLK (applied at the pin PCLK), if HWCR.CLK is set to 0b. The resulting output PWM frequency clock fPWM is: f PCLK f PWM = ------------------------------------256 ⋅ prescaler The prescaler is set via the register CHCRn.FREQ according to: Table 4 Prescaler Setting Resulting Prescaler Normal mode without automatic PWM generation Prescaler 1: fPCLK (or fINT) / 256 Prescaler 2: fPCLK (or fINT) / 512 Prescaler 4: fPCLK (or fINT) / 1024 (1) Prescaler Setting CHCRn.FREQ 00b 01b 10b 11b For example: with fin =102,400 Hz • • • CHCRn.FREQ = 01b: fPWM = 400 Hz CHCRn.FREQ = 10b: fPWM = 200 Hz CHCRn.FREQ = 11b: fPWM = 100 Hz Note: For avoiding skews it is recommended to change the prescaler setting only during deactivated PWM generator (PCR.PST = 0b). Data Sheet 27 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Automatic PWM Generator The applied clock signal can be monitored via SPI in the standard diagnosis. The standard diagnosis bit CLE provides the information in device operation mode (not during stand-by), if the applied clock is above or below the threshold fPCLK(TH) according to the following table. The bit CLE will be reset after every successful standard diagnosis readout. The reset of the bit CLE is performed only, if the bit CLE is set. Table 5 External Clock Monitoring Clock Frequency External Clock Status CLE 0b 1b fPCLK > fPCLK(TH) fPCLK < fPCLK(TH) Note: A changing of the HWCR.CLKTRIM will also change the CLE thresholds. 7.2.2 Internal PWM Clock The SPOC - BTS6480SF provides also an internal clock signal fINT. The internal clock frequency is used by setting the register HWCR.CLK to 1b. For adjusting the clock signal, a trimming of fINT via the SPI register HWCR.CLK_TRIM can be done. fPWM can be decreased or increased in steps of kTRIM. f INT ± ( x ⋅ k TRIM ) f PWM = ------------------------------------256 ⋅ prescaler (2) 7.3 PWM Duty Cycle The PWM duty cycle of each output is defined by the SPI register DCCRn.DC register from 0 to 256. The ON-state duty cycle is (in %): ------------------------------------------------DC PWM = DCCRn.DC ⋅ 100 256 (3) The minimum duty cycle, which can be set (except from 0 %), is according to Equation (3) 0.39 %. The duty cycle of the output voltage depends on the switching times tON, tOFF and the connected load. Therefore, the observed output duty cycle can differ from the set duty cycle. 7.4 Channel Phase Shift For optimized EMC performances phase shifts between all channels can be programmed via the SPI register CHCRn.PHS. The phase shifts refer to one common start point. Please refer to Figure 8. Up to eight different phase shifts can be selected. Data Sheet 28 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Automatic PWM Generator VPCLK TPCLK PCR.PST t OUT.OUT0 t VOUT0 DCPWM0 TPWM0 OUT.OUT1 t VOUT1 tCh. phase shift1 t ChannelPhaseShift .emf t t Figure 8 Phase Shifts between Channels 7.5 Daisy Chain Operation with PWM Generator The SPI of SPOC - BTS6480SF provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. This allows the usage of only one PWM clock input signal fPCLK. To avoid a synchronous activation of channels of the different devices, device phase shift can be programmed at the register PCR.DPSH. 7.5.1 Activation of Several SPOC Devices with PWM Generation For the usage of several SPOC devices in daisy chain configuration with automatic PWM generation the following procedure is recommended: • • • • • Wake up the devices by setting the DCR.MUX ≠ 111b Set the PWM frequencies, duty cycles, phase shifts of all channels Set the device phase shift for each SPOC device differently Activate the automatic PWM generator of all devices by setting PCR.PST within one MCS-frame Activate the channels via the SPI registers OUT.OUTn With the next rising edge of the PWM clock signal fPWM the automatic PWM generation will start. Please see Figure 9 for details. Note: If the PWM generator is started during stand-by, the power-on wake up time tWU(PO) (5.3.14) has to be considered as delay until the automatic PWM generation will start. Data Sheet 29 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Automatic PWM Generator VPCLK t PCR.PST t OUT.OUT0 t VOUT0 t D evice 1 PCR.PST t OUT.OUT0 t VOUT0 tDev. phase shift1 DCPWM0 OUT.OUT1 t VOUT1 tDev. phase shift1 t Ch. phase shift1 DCPWM1 DevicePhaseShift.emf t Device 2 t Figure 9 Phase Shifts between Devices 7.5.2 • • • • • How to resynchronize a Reset SPOC In case of a reset SPOC device or a SPOC device in stand-by mode the synchronization can be done as follows: Set the PWM frequencies, duty cycles, phase shifts of the reset device Set the device phase shift for the reset SPOC device Deactivate the automatic PWM generation of all SPOC devices in this daisy chain With the next SPI transmission activate the automatic PWM generator of all SPOC devices by setting PCR.PST within one MCS-frame Activate the channels of the reset SPOC device via the SPI register OUT.OUTn With the next rising edge of the PWM clock signal fPWM the automatic PWM generation will start again synchronously. Data Sheet 30 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Automatic PWM Generator 7.6 Electrical Characteristics Electrical Characteristics Power Stages Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Automatic PWM Generator 7.6.1 External PWM clock threshold 7.6.2 External PWM clock 7.6.3 External PWM clock period 7.6.4 External PWM clock high time 7.6.5 External PWM clock low time 7.6.6 External PWM clock duty cycle range 7.6.7 Internal PWM clock 7.6.8 Internal PWM clock trimming step Symbol Limit Values min. typ. max. Unit Test Conditions fPCLK(TH) fPCLK tPCLK(P) tPCLK(H) tPCLK(L) DCPCLK fINT kTRIM 22 – 4 2 2 75 – – – – – – 105 5% 46 250 – – – 70 % 135 – kHz kHz µs µs µs kHz HWCR.CLKTRIM = 100 – 1) 1) 1) 1) 30 % – HWCR.CLKTRIM = 100 2) 1) Not subject to production test, specified by design. Functional test is performed at fPCLK = 250kHz. 2) Not subject to production test, specified by design. Data Sheet 31 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Automatic PWM Generator 7.7 Command Description HWCR Hardware Configuration Register W/R read write RB 1 1 0 0 0 0 ADDR 1 1 0 0 9 0 0 8 7 CLKTRIM CLKTRIM 6 5 CLK CLK 4 0 0 3 2 1 STB RST 0 CL CL LED3 LED2 LED3 LED2 Field CLK Bits 5 Type rw Description Clock Mode 1) 0 External clock input PCLK is used for PWM mode 1 Internal clock is used for PWM mode Internal Clock Trim 000 fINT - 4 kTRIM ... 011 fINT - 1 kTRIM 100 fINT without trimming 101 fINT + 1 kTRIM ... 111 fINT + 3 kTRIM CLKTRIM 8:6 rw 1) For avoiding skews it is recommended to change from external to internal clock source or vice versa only during deactivated PWM generator (PCR.PST = 0b). Standard Diagnosis CS TER 15 0 14 LHI 13 SBM 12 x 11 CLE 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 2 1 0 ERR3 ERR2 ERR1 ERR0 Field CLE Bits 11 Type r Description External Clock Status 1) 0 fPCLK > fPCLK(TH) 1 fPCLK < fPCLK(TH) 1) Invalid in stand-by mode Data Sheet 32 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Automatic PWM Generator CHCRn Channel Configuration Register W/R r/w RB 1 1 x ADDR x x 9 0 8 0 7 0 6 5 PHSn 4 3 2 1 0 SYDELn FREQn Field FREQn n = 0 to 5 Bits 1:0 Type rw Description PWM Frequency Prescaler Setting for Channel n 00 Normal mode without automatic PWM generation 01 Prescaler 1: fPCLK (or fINT) / 256 10 Prescaler 2: fPCLK (or fINT) / 512 11 Prescaler 4: fPCLK (or fINT) / 1024 Delay of Current Sense Synchronization Signal for Channel n 00 No synchronization signal delay 01 Synchronization signal delay 1: 8 / (fPCLK (or fINT)) 10 Synchronization signal delay 2: 16 / (fPCLK (or fINT)) 11 Synchronization signal delay 3: 24 / (fPCLK (or fINT)) Channel Phase Shift for Channel n 000 No phase shift 001 Phase shift 1: 32 / (fPCLK (or fINT)) 010 Phase shift 2: 64 / (fPCLK (or fINT)) ... 110 Phase shift 6: 192 / (fPCLK (or fINT)) 111 Phase shift 7: 224 / (fPCLK (or fINT)) SYDELn n = 0 to 5 3:2 rw PSHn n = 0 to 5 6:4 rw PCR PWM Configuration Register W/R r/w RB 0 0 1 ADDR 1 1 9 0 8 0 7 0 6 0 5 0 4 0 3 DCS 2 DPSH 1 0 PST Field PST Bits 0 Type rw Description Automatic PWM Generation 0 No automatic PWM generation 1 Automatic PWM generation Device Phase Shift 00 No phase shift 01 Phase shift 1: 8 / (fPCLK (or fINT)) 10 Phase shift 2: 16 / (fPCLK (or fINT)) 11 Phase shift 3: 24 / (fPCLK (or fINT)) Single Duty Cycle for all Channels 0 Duty cycle setting of channel 0 used for all channels 1 Individual duty cycle setting used for each channel DPSH 2:1 rw DCS 3 rw Data Sheet 33 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Automatic PWM Generator DCCRn Duty Cycle Configuration Register W/R r/w RB 0 1 x ADDR x x 9 0 8 7 6 5 4 DCn 3 2 1 0 Field DCn n = 0 to 5 Bits 8:0 Type rw Description Duty Cycle for Channel n during Automatic PWM Generation 000000000 DC value: 0 (channel off) 000000001 DC value: (1 / 256) * 100 000000010 DC value: (2 / 256) * 100 ... 011111111 DC value: (255 / 256) * 100 1xxxxxxxx DC value: 1 (channel 100% on) Data Sheet 34 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Protection Functions 8 Protection Functions The device provides embedded protective functions, which are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered as “outside” normal operating range. Protective functions are neither designed for continuous nor for repetitive operation. 8.1 Over Current Protection The maximum load current IL is switched off in case of exceeding the over current trip level IL(trip) by the device itself. Depending on the total short circuit impedance higher current over shoots may occur. A limited auto-restart function is implemented. The number of restarts is dependent of the VDS voltage. Please refer to following figures for details. normal operation t V DS V DS(Vtrip) over current IN / OUTx t IL I L(trip) Switch off by over current switch off T j(SC) Tj Latch OFF due maximum number of retries reached Restart by dynamic temperature sensor t T j(startn) + ∆T j(res) T j(start2) + ∆ T j(res) Tj(start1) + ∆ Tj(res) Tj(start1) IIS n=1 n = n retry t t ERR * * ERR-flag will be reset by standard diagnosis readout during restart t CL = 1 over load removed CurrentTrippingDeltaT_nretry.emf Figure 10 Over current protection with latch due to reaching maximum number of retries nretry Data Sheet 35 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Protection Functions over current IN / OUTx V DS V DS(Vtrip) normal operation t t IL I L(trip) Switch off by over current switch off T j(SC) T j(startn) + ∆T j(res) Tj Restart by dynamic temperature sensor Latch OFF due to over temperature t T j(start2) + ∆ T j(res) Tj(start1) + ∆ Tj(res) Tj(start1) IIS n=1 n < nretry t t ERR * * ERR-flag will be reset by standard diagnosis readout during restart CL = 1 over load removed t CurrentTrippingDeltaT_OT.emf Figure 11 Over current protection with latch due to reaching over temperature Tj(SC) The ERR-flag will be set during over current shut down. It can be reset by reading the ERR-flag. If the channel is still in over current shut down, the ERR-flag will be set again. During the automatic restart of the channel the ERRflag can be cleared by reading the ERR-flag. It will be set again as soon as the over current protection is activated again. The number of restarts nretry is depending on the VDS voltage according to the following figure and Chapter 8.2. IL(trip) IL(Vtrip) IL n = n retry(LV) n = nretry(MV) no retry 5 10 15 20 VDS CurrentTrippingVsVDS.emf Figure 12 Number of retries and trip levels dependent of VDS The retry latch or over temperature latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately (or according to the automatic PWM generator setting) after the command HWCR.CL = 1b. Data Sheet 36 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Protection Functions 8.2 Over Current Protection at high VDS The SPOC - BTS6480SF provides an over current protection for VDS > VDS(Vtrip) (8.9.5). For VDS > VDS(Vtrip) and IL > IL(Vtrip) during turn on the channel switches off and latches immediately. For details please refer to parameter IL(VTRIP) (8.9.4). The current trip level IL(Vtrip) is below the current trip level IL(trip) at VDS = 7V. The ratio between IL(trip) and IL(Vtrip) is defined by the parameter ∆kTR (8.9.6). The over current latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately (or according to the automatic PWM generator setting) after the command HWCR.CL = 1b. normal operation t VDS VDS(Vtrip) IN / OUTx high V DS over current t IL I L(Vtrip) t I IS t ERR over load removed CL = 1 t CurrentTrippingHighVDS.emf Figure 13 Over current protection in case of high VDS voltages 8.3 Over Current Protection for Short Circuit Type 2 Protection After activation of the channels without over temperature shutdown and after the delay time tdelay(trip) (8.9.2) the over current protection threshold IL(trip) is reduced to IL(Itrip). The delay time tdelay(trip) is reset by an dynamic temperature sensor or over current shutdown and any IN, OUTx or automatic PWM generator signal transition. In case of a short circuit to GND event with IL > IL(Itrip) (8.9.3), which occurs in the on state, the channel is switched off and latched immediately. For more details, please refer to the figure Figure 14. The current trip level IL(Itrip) is below the current trip level IL(trip) at VDS = 7V. The ratio between IL(trip) and IL(Itrip) is defined by the parameter ∆kTR (8.9.6). The over current latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately (or according to the automatic PWM generator setting) after the command HWCR.CL = 1b. Data Sheet 37 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Protection Functions IN / OUTx IL normal operation over current normal operation t IL(Itrip) t IIS t ERR t > tdelay(trip) over load removed CL = 1 t CurrentTrippingLowVDS .emf Figure 14 Shut Down by Over Current due to Short Circuit Type 2 8.4 Over Temperature Protection Each channel has its own temperature sensor. If the temperature at the channel exceeds the thermal shutdown temperature Tj(SC), the channel will switch off and latch to prevent destruction (also in case of VDD = 0V). In order to reactivate the channel, the temperature at the output must drop by at least the thermal hysteresis ∆Tj and the over temperature latch must be cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately (or according to the automatic PWM generator setting) after the command HWCR.CL = 1b. IN / OUTx t IL I L(trip) t Tj(start1) + ∆ Tj(SW) T j(SC) Tj Latch OFF due to over temperature Latch OFF due to over temperature Tj(start1) I IS t t ERR CL = 1 CL = 1 t OverLoad.emf Figure 15 Shut Down by Over Temperature 8.4.1 Dynamic Temperature Sensor Protection Additionally, each channel has its own dynamic temperature sensor. The dynamic temperature sensor improves short circuit robustness by limiting sudden increases in the junction temperature. The dynamic temperature sensor turns off the channel if its sudden temperature increase exceeds the dynamic temperature sensor threshold ∆Tj(SW). The number of automatic reactivations is limited by nretry (8.9.7). If this number of retries is exceeded the channel turns off and latches. The retry latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately (or according to the automatic PWM generator setting) after the command HWCR.CL = 1b. For the condition n < nretrythe counter of automatic reactivations will be reset by every low to high transition on the input pin or the bit in SPI register OUT. Data Sheet 38 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Protection Functions For automatic PWM generation the counter will be reset also in case of duty cycles < 100% during the off-state. Please refer to Figure 14 for details. normal operation t VDS VDS(Vtrip) over load IN / OUTx t IL IL(trip) T j(SC) Tj Switch off by dynamic temperature sensor Restart by dynamic temperature sensor Latch OFF due maximum number of retries reached t T j(startn) + ∆T j(res) Tj(start1) + ∆ Tj(SW) T j(start1) + ∆ T j(res) Tj(start1) I IS ∆ T jSW n=1 n = nretry t t ERR * * ERR-flag will be reset by standard diagnosis readout during restart t CL = 1 over load removed DeltaT_nretry.emf Figure 16 Dynamic Temperature Sensor Operations with latch due to reaching maximum number of retries nretry Data Sheet 39 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Protection Functions over load IN / OUTx VDS VDS(Vtrip) normal operation t t IL IL(trip) T j(SC) T j(startn) + ∆T j(res) Tj Switch off by dynamic temperature sensor Restart by dynamic temperature sensor Latch OFF due to over temperature t Tj(start1) + ∆ Tj(SW) T j(start1) + ∆ T j(res) Tj(start1) I IS ∆ T jSW n=1 n < nretry t t ERR * * ERR-flag will be reset by standard diagnosis readout during restart CL = 1 over load removed t DeltaT_OT.emf Figure 17 Dynamic Temperature Sensor Operations with latch due to reaching over temperature Tj(SC) The ERR-flag will be set during dynamic temperature sensor shut down. It can be reset by reading the ERR-flag. If the channel is still in dynamic temperature sensor shut down, the ERR-flag will be set again. During the automatic restart of the channel the ERR-flag can be cleared by reading the ERR-flag. It will be set again as soon as the dynamic temperature sensor is activated again. 8.5 Reverse Polarity Protection In reverse polarity mode, power dissipation is caused by the intrinsic body diode of each DMOS channel as well as each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected loads.The current through the ground pin, sense pin IS, current sense synchronization pin, the logic power supply pin VDD, the SPI pins, input pins, external driver pins, clock input pin and the limp home input pin has to be limited as well (please refer to the maximum ratings listed on Page 10). For reducing the power loss during reverse polarity ReversaveTM functionality is implemented for all channels. They are turned on to almost forward condition in reverse polarity condition, see parameter RDS(REV). Note: No protection mechanism like temperature protection or current protection is active during reverse polarity. 8.6 Over Voltage Protection In the case of supply voltages between VBB(SC) max and VBB(CL) the output transistors are still operational and follow the input or the OUT register. Parameters are not warranted and lifetime is reduced compared to normal mode. In addition to the output clamp for inductive loads as described in Section 6.3, there is a clamp mechanism available for over voltage protection for the logic and all channels. Data Sheet 40 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Protection Functions 8.7 Loss of Ground In case of complete loss of the device ground connections, but connected load ground, the SPOC - BTS6480SF securely changes to or stays in OFF-state. 8.8 Loss of VBB In case of loss of VBB connection in on-state, all inductances of the loads have to be demagnetized through the ground connection or through an additional path from VBB to ground. For example, a suppressor diode is recommended between VBB and GND. Data Sheet 41 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Protection Functions 8.9 Electrical Characteristics Electrical Characteristics Protection Functions Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Over Load Protection 8.9.1 Load current trip level channel 0, 1 Symbol Limit Values min. typ. max. A 71 – 67 29 – 23 7 – 5.5 Over Current Protection 8.9.2 Over current tripping activation time 8.9.3 Load current trip level after tdelay(trip) channel 0, 1 channel 2, 3 17 15.5 3.8 3.8 8.9.4 Load current trip level at high VDS channel 0, 1 channel 2, 3 17 15.5 3.8 3.8 8.9.5 Over current tripping at high VDS activation level – – – – – 1.5 35 30 9 8 – – V – – – – – – 35 30 9 8 A 40 35 78 70 – 90 – – 30 – – 8.5 – – – – 120 – 100 44 – 39 12 – 11 14 78 70 ms A Unit Test Conditions IL(trip) VDS < 7 V Tj = -40 °C 1) Tj = 25 °C Tj = 150 °C HWCR.LEDn = 0 channel 2, 3 Tj = -40 °C 1) Tj = 25 °C Tj = 150 °C HWCR.LEDn = 1 Tj = -40 °C 1) Tj = 25 °C Tj = 150 °C 1) tdelay(trip) 7 IL(Itrip) 40 35 Tj = -40 °C Tj = 150 °C HWCR.LEDn = 0 Tj = -40 °C Tj = 150 °C HWCR.LEDn = 1 Tj = -40 °C Tj = 150 °C 1) IL(Vtrip) Tj = -40 °C Tj = 150 °C HWCR.LEDn = 0 Tj = -40 °C Tj = 150 °C HWCR.LEDn = 1 Tj = -40 °C Tj = 150 °C 1) VDS(Vtrip) 15 1.2 8.9.6 Current trip at VDS = 7 V to current trip at ∆kTR VDS = 20 V ratio 1) Data Sheet 42 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Protection Functions Electrical Characteristics Protection Functions (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Over Temperature Protection 8.9.7 Number of automatic retries at over nretry(LV) current or dynamic temperature sensor shut down at low VDS – 32 – 1) Symbol Limit Values min. typ. max. Unit Test Conditions VDS = 9 V nretry(MV) – 8.9.8 Number of automatic retries at over current or dynamic temperature sensor shut down at medium VDS 8.9.9 Thermal shut down temperature 8 – 1) VDS = 13 V Tj(SC) 8.9.10 Thermal hysteresis of thermal shutdown ∆Tj 8.9.11 Dynamic temperature increase ∆Tj(SW) limitation while switching 8.9.12 Dynamic temperature sensor restart Reverse Battery 8.9.13 On-state resistance channel 0, 1 ∆Tj(res) 150 – – – 175 10 60 20 195 – – – °C K K K mΩ 1) 1) 1) 1) RDS(REV) – – channel 2, 3 – – 14.7 29.5 – – 4.7 9.5 – – 1) VBB = -13.5 V IL = -7.5 A Tj = 25 °C Tj = 150 °C IL = -2.6 A Tj = 25 °C Tj = 150 °C V Over Voltage 8.9.14 Over voltage protection VBB to GND channel 0, 1 VBB(CL) 40 32 40 channel 2, 3 32 40 55 – – – – 70 54 55 54 55 IGND = 5 mA Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 6 A Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 2 A 1) Not subject to production test, specified by design. Data Sheet 43 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Protection Functions 8.10 Command Description HWCR Hardware Configuration Register W/R read write RB 1 1 0 0 0 0 ADDR 1 1 0 0 9 0 0 8 7 CLKTRIM CLKTRIM 6 5 CLK CLK 4 0 0 3 2 1 STB RST 0 CL CL LED3 LED2 LED3 LED2 Field CL Bits 0 Type rw Description Clear Latch 0 Thermal and over current latches are untouched 1 Command: Clear all thermal and over current latches Standard Diagnosis CS TER 15 0 14 LHI 13 SBM 12 x 11 CLE 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 2 1 0 ERR3 ERR2 ERR1 ERR0 Field ERRn n = 0 to 3 Bits 3:0 Type r Description Error Flag for Channel n 0 No error 1 Error occurred Data Sheet 44 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis 9 Diagnosis For diagnosis purpose, the SPOC - BTS6480SF provides a current sense signal at pin IS and the diagnosis word via SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. In OFF-state a current source is able to be switched on for a selected channel with the DCR.CSOL bit. This allows open load / short circuit detection to VBB in OFF-state. The current value can be configured to a low or a high value by programming the bit IECR.CSL. Please refer to parameter IL(OL) (9.8.15). Note: Please note: All below stated parameters and functions are valid for the internal channels. The behavior of the current sense of the two external channel is restricted to the behavior of the external drivers. Please refer to Figure 18 for details on diagnosis function: VBB IIS0 latch gate control OR temperature sensor T CSOL IL(OL) over current protection load current sense latch ERR0 OUT3 OUT2 OUT1 OUT0 channel 0 DCR.MUX VBB V DS(SB) DCR. SBM current sense multiplexer IS RIS Diagnosis_STD .emf Figure 18 Block diagram: Diagnosis Data Sheet 45 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis For diagnosis feedback at different operation modes, please see following table. Table 6 Operation Modes 1) Input Level Output OUT.OUTn Level VOUT L/0 GND (OFF-state) GND Z VBB Operation Mode Normal Operation (OFF) Short Circuit to GND Thermal shut down Short Circuit to VBB Open Load Inverse Current Normal Operation (ON) Short Circuit to GND Dynamic Temperature Sensor shut down Over Current shut down Thermal shut down Short Circuit to VBB Open Load Inverse Current 1) 2) 3) 4) 5) 6) Current Sense IIS Z Z Z Z Z Z IL / kILIS Error Flag ERRn2) 0 0 0 0 0 0 0 1 1 1 1 5) 6) SBM DCR.SBM 1 1 x 0 03) 04) 0 1 x x x 0 0 0 Z > VBB H/1 (ON-state) ~ VBB ~ GND Z Z Z VBB VBB Z Z Z Z < IL / kILIS Z Z 0 0 0 > VBB L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit x = undefined The error flags are latched until they are transmitted in the standard diagnosis word via SPI If the current sense multiplexer is set to Channel 0 to 3 and DRC.CSOL bit set If the current sense multiplexer is set to Channel 0 to 3 The over current latch off flag is set latched and can be cleared by SPI command HWCR.CL The over temperature flag is set latched and can be cleared by SPI command HWCR.CL 9.1 Diagnosis Word at SPI The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard diagnosis bits ERRn. The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal. The over temperature flags, which cause an overheated channel to latch off, are latched directly at the gate control block. The over current flags, which cause an channel 0 or 1 driving a too high current to switch off, are latched like the over temperature flags. Those latches are cleared by SPI command HWCR.CL. Please note: The over temperature and over current information is latched twice. When transmitting a clear latch command (HWCR.CL), the error flag is cleared during command transmission of the next SPI frame and ready for latching after the third raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CL command will indicate a failure mode at the previously affected channels although the thermal latches have been cleared already. In case of continuous over load, the error flags are set again immediately because of the over load monitoring signal. 9.2 Load Current Sense Diagnosis There is a current sense signal available at pin IS which provides a current proportional to the load current of one selected channel. The selection is done by a multiplexer which is configured via SPI. Data Sheet 46 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis Current Sense Signal The current sense signal (ratio kILIS = IL / IS) is provided during on-state as long as no failure mode occurs.The ratio kILIS can be adjusted to the load type (LED or bulb) via SPI register HWCR for channel 2 and 3. The accuracy of the ratio kILIS depends on the load current.Usually a resistor RIS is connected to the current sense pin. It is recommended to use resistors 1.5 kΩ < RIS < 5 kΩ. A typical value is 2.7 kΩ. 60000 50000 kilis Tj = -40 °C kilis typ Tj = 25 °C kilis Tj = 25 °C, 150 °C 40000 k ilis v alue 30000 20000 10000 0 0 1 2 3 4 Load current IL [A] 5 6 7 8 Figure 19 Current Sense Ratio kILIS Channel 0, 1 1) 4000 kilis bulb Tj = 25 °C, 150 °C 3500 3000 2500 k ilis v alue 2000 1500 1000 500 0 0 0.5 1 1.5 2 2.5 3 kilis bulb typ Tj = 25 °C kilis bulb Tj = -40 °C kilis LED Tj = 25 °C, 150 °C kilis LED typ Tj = 25 °C kilis LED Tj = -40 °C 3.5 4 4.5 Load current IL [A] Figure 20 Current Sense Ratio kILIS Channel 2, 3 2) In case of off-state, over current, dynamic temperature sensor shut down (n < nretry), dynamic temperature sensor latch (n = nretry) as well as over temperature, the current sense signal of the affected channel is switched off. To distinguish between over temperature or over current and over load, the SPI diagnosis word can be used. Whereas the over load and dynamic temperature sensor shut down (n < nretry) flag is cleared every time the diagnosis is transmitted. The over temperature, dynamic temperature sensor latch (n = nretry) and over current flag is cleared by a dedicated SPI command (HWCR.CL). 1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in Section 9.8 (Position 9.8.1). 2) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in Section 9.8 (Position 9.8.1). Data Sheet 47 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL can be found in Figure 21. OUTx V OUT OFF ON tON OFF tOFF t t IL IIS tsIS(ON) tsIS(LC) tdIS(OFF) t t SenseTiming .emf Figure 21 Timing of Current Sense Signal Current Sense Multiplexer There is a current sense multiplexer implemented in the SPOC - BTS6480SF that routes the sense current of the selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current also can be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please refer to Figure 22. The current sense diagnosis enable signal for the external smart power drivers also can be selected via the SPI register DCR.MUX. For being compliant to PROFET+ diagnostic functions, it is possible to configure pin EDD0 as DEN and EDD1 as DSEL. Therefore, the bit IECR.PRO+ needs to be set. CS DCR.MUX 110 IIS 000 tsIS(EN) 010 tsIS(MUX) 110 tdIS(MUX) t t MuxTiming.emf Figure 22 Timing of Current Sense Multiplexer Data Sheet 48 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis 9.3 Sense Synchronization during Automatic PWM Generation For performing current sense measurements there is a current sense synchronization signal at the pin ISSY available. This signal indicates the possible start of VIS measurement. The synchronization signal will be activated after the time tMeasurement delay after channel’s activation. The delay time can be configured via SPI register CHCRn.SYDEL. The current sense synchronization signal is only available during the automatic PWM generation, i.e. the bit PCR.PST is set. Figure 23 shows the functionality of the current sense synchronization signal. VPCLK t PCR.PST t OUT.OUT0 t VOUT0 t OUT.OUT1 t VOUT1 tCh. phase shift1 DCR.MUX VISSY t Synch. delay1 VIS tsIS(ON) t SenseSynchronization.emf t 001 001 001 000 t tSynch. delay0 t Figure 23 Current Sense Synchronization Data Sheet 49 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis 9.4 Sense Measurement without Synchronization Signal The SPOC - BTS6480SF refers all the channel activations to the clock signal fPCLK or fINT. In case of using the external clock fPCLK the state (ON- or OFF-state) is known by the micro controller, which allows a time based processing. In case of micro controller’s loss of the PCLK synchrony the automatic PWM generation can be started again by resetting and setting of the bit PCR.PST. After that the micro controller is synchronous to the automatic PWM generation. 9.5 Automatic Current Sense Multiplexer Switching The device provides for current sense measurements a function, which changes the current sense multiplexer sequentially and automatically. The function starts after the PWM reference point has passed, which happens each 1024 clock cycles (fPCLK or fINT). For more details please refer to figure Figure 24. The current sense multiplexer is switched first to the channel 0. When the current sense synchronization signal at the pin ISSY is finished, the multiplexer is programmed automatically to channel 1 (one clock cycle after the high low transition of the ISSY signal) and so on. The current sense synchronization signal at the pin ISSY will be set for eight clock cycles, if the channel duty cycle is 0 % < DC tduty cycle (delay longer than on-state of channel) the sense synchronization signal will be set for nine clock cycles (fPCLK or fINT). Furthermore, to shorten the ISSY burst length for channels continuously in ON- or OFF-state, the ISSY signal will be started 11 clock cycles after the previous ISSY pulse. If the synchronization delay is programmed to 11b the following channel needs at minimum a synchronization delay ≥ = 01b, otherwise the next ISSY signal will be delayed by one period of the following channel. This multiplexer switching loop is done only once after the bit DCR.AMUX is set. After the completed loop the bit will be set to DCR.AMUX = 0b automatically. For more details please refer to Figure 24. The automatic multiplexer switching can be stopped manually by setting the bit DCR.AMUX = 0b. Note: The phase shifts between the channels have to be programmed in ascending order (channel 0 with minimum phase shift, channel 1 with a higher phase shift than channel 0, channel 2 with a higher phase shift than channel 1, ...) to get a short AMUX burst duration. Otherwise the duration for a complete automatic multiplexer cycle will increase until a new PWM reference point has passed and the channel is activated. During the activated AMUX bit any command, which should change the multiplexer, will be ignored. If a channel is switched continuously off, the current sense multiplexer will be switched to high impedance during the sense synchronization pulse. Data Sheet 50 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis VPCLK n * 1024 PCR.PST t DCR.AMUX VOUT0 t VOUT1 tCh. phase shift1 VOUT2 ... VOUT5 tCh. phase shift5 Ch0 VIS t sIS(ON) VISSY tSynch. delay0 tSynch. high A * tISSY delay ON/OFF tSynch. high B * tSynch. delay2 tSynch. high A * * tSynch. high A = 8 / (f PCLK or f INT) tISSY delay ON/OFF * tSynch. high B = 9 / (f PCLK or f INT) tSynch. high B * * tISSY delay ON/OFF = 11 / (f PCLK or fINT ) t t Ch1 Ch2 ... Ch5 t tCh. phase shift2 t t Set to 0 automatically t t AutoMUX_EXT .emf Figure 24 Automatic Current Sense Multiplexer Switching 9.6 Switch Bypass Diagnosis To detect short circuit to VBB, there is a switch bypass monitor implemented for all internal channels. In case of short circuit between the output pin OUT and VBB in ON-state, the current will flow through the power transistor as well as through the short circuit (bypass) with undefined ratio. As a result, the current sense signal will show lower values than expected by the load current. In OFF-state, the output voltage will stay close to VBB potential which means a small VDS. The switch bypass monitor compares the voltage VDS across the power transistor of that channel, which is selected by the current sense multiplexer (DCR.MUX) with threshold VDS(SB). The result of comparison can be read in SPI register DCR.SBM or in the standard diagnosis. Data Sheet 51 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis 9.7 Open Load in OFF-State For performing a dedicated open load in OFF-state detection a current source can be switched in parallel to the DMOS according to the Figure 18. The current source current can be programmed in two steps by the bit IECR.CSL. The following procedure is recommended to use: • • • • Select the dedicated channel with the multiplexer Enable the open load current with the DCR.CSOL bit Read the DCR.SBM or the standard diagnosis Disable the open load current with the DCR.CSOL bit Data Sheet 52 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis 9.8 Electrical Characteristics Electrical Characteristics Diagnosis Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Load Current Sense 9.8.1 Current sense ratio channel 0, 1: 0.600 A 1.3 A 2.6 A 4.0 A 7.5 A channel 2, 3 (bulb): 0.300 A 0.600 A 1.3 A 2.6 A 4.0 A channel 2, 3 (LED): 0.050 A 0.150 A 0.300 A 0.600 A 1.0 A 9.8.2 Current sense ratio channel 0, 1: 0.600 A 1.3 A 2.6 A 4.0 A 7.5 A channel 2, 3 (bulb): 0.300 A 0.600 A 1.3 A 2.6 A 4.0 A channel 2, 3 (LED): 0.050 A 0.150 A 0.300 A 0.600 A 1.0 A 165 300 350 385 400 400 440 450 460 500 805 640 580 555 555 990 1240 1400 1540 1540 1670 1750 1800 1830 1840 2690 2300 2100 2110 2110 3120 4420 5030 5130 5490 5840 6140 6350 6430 6480 10960 10010 8660 8240 7710 – – – – – HWCR.LEDn = 0 – – – – – HWCR.LEDn = 1 – – – – – 165 300 350 385 400 400 440 450 460 500 1305 675 580 555 555 990 1240 1400 1540 1540 1670 1750 1800 1830 1840 3710 2710 2210 2110 2110 2190 3990 4690 5130 5490 5840 6140 6350 6430 6480 50010 12510 9210 8510 7710 – – – – – HWCR.LEDn = 0 – – – – – HWCR.LEDn = 1 – – – – – Symbol Limit Values min. typ. max. Unit Test Conditions kILIS Tj = -40 °C kILIS Tj = 25 °C to 150 °C Data Sheet 53 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis Electrical Characteristics Diagnosis (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values min. 9.8.3 Current sense drift of unaffected channel ∆kILIS(IC) during inverse current of other channels channel 0, 1 -20 % – -20 % – channel 2, 3 (bulb) -20 % – -20 % – channel 2, 3 (LED) -20 % – -20 % – 9.8.4 Current sense voltage limitation 20 % 20 % 1.1 × V 20 % 20 % 20 % 20 % typ. max. 1) Unit Test Conditions DCR.MUX ≠ 111 IL0, 1 = 7.5 A IL1, 0 (IC) = 7.5 A IL2, 3 (IC) = 2.6 A HWCR.LEDn = 0 IL2, 3 = 2.6 A IL0, 1 (IC) = 7.5 A IL3, 2 (IC) = 2.6 A HWCR.LEDn = 1 IL2, 3 = 0.6 A IL0, 1 (IC) = 7.5 A IL3, 2 (IC) = 2.6 A DCR.MUX = 011 VIS(LIM) 0.9 × VDD 5.5 VDD VDD – mA µA 9.8.5 Maximum steady state current sense output current 9.8.6 Current sense leakage / offset current channel 0, 1 channel 2, 3 9.8.7 Current sense leakage, while diagnosis disabled IIS(MAX) IIS(en) – IL3 = 2 A RIS = 2.7 kΩ 1) VIS = 0 V IL = 0 A DCR.MUX ≠ 111 – – – – – 76 76 1 µA µs DCR.MUX = 110 IIS(dis) – 9.8.8 Current sense settling time after channel tsIS(ON) activation channel 0, 1 channel 2, 3 – – – – – – 150 150 100 µs VBB = 13.5 V RIS = 2.7 kΩ RL = 2.2 Ω HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 9.8.9 Current sense desettling time after channel deactivation tdIS(OFF) – – – – 25 25 RL = 33 Ω 1) VBB = 13.5 V RIS = 2.7 kΩ HWCR.LEDn = 0 HWCR.LEDn = 1 1) 9.8.10 Current sense settling time after change tsIS(LC) of load current channel 0, 1 channel 2, 3 µs – – – – – – 30 30 30 RIS = 2.7 kΩ IL = 7.5 A to 4.0 A HWCR.LEDn = 0 IL = 2.6 A to 1.3 A HWCR.LEDn = 1 IL = 0.6 A to 0.3 A VBB = 13.5 V Data Sheet 54 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis Electrical Characteristics Diagnosis (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter 9.8.11 Current sense settling time after current sense activation 9.8.12 Current sense settling time after multiplexer channel change Symbol Limit Values min. typ. – max. 25 µs – Unit Test Conditions tsIS(EN) RIS = 2.7 kΩ DCR.MUX: 110 -> 000 tsIS(MUX) – – 30 µs RIS = 2.7 kΩ RL0 = 2.2 Ω RL2 = 33 Ω DCR.MUX: 010 -> 000 1) 9.8.13 Current sense deactivation time tdIS(MUX) – – 25 µs RIS = 2.7 kΩ DCR.MUX: 000 -> 110 – IECR.CSL = 0 IECR.CSL = 1 Switch Bypass Monitor 9.8.14 Switch bypass monitor threshold Open load in off current source 9.8.15 Current source in OFF-state Current Sense Synchronization Signal 9.8.16 L level signal voltage 9.8.17 H level signal voltage 9.8.18 Signal enable time 9.8.19 Signal disable time 1) Not subject to production test, specified by design. VDS(SB) IL(OL) 1.5 100 3.0 0 – – – – – – – 4 450 7.5 0.4 V µA mA V V µs µs VISSY(L) VISSY(H) tISSY(en) tISSY(dis) VDD 0.4 V – – VDD 4 4 IISSY = -0.5 mA 1) IISSY = 0.5 mA VDD = 4.3 V 1) CL = 20 pF 1) CL = 20 pF Data Sheet 55 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis 9.9 Command Description DCR Diagnosis Control Register W/R read write RB 1 1 0 0 0 0 ADDR 1 1 1 1 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 3 2 1 MUX MUX 0 AMUX SBM AMUX CSOL Output state OUT.OUTn 0 (OFF-state) Field MUX Bits 2:0 Type r/w Description Set Current Sense Multiplexer Configuration 000 IS pin is high impedance 001 IS pin is high impedance 010 IS pin is high impedance 011 IS pin is high impedance 100 IECR.PRO+ = 0: Diagnosis enable of external driver 0 activated (EDD0 = 1) 101 IECR.PRO+ = 0: Diagnosis enable of external driver 1 activated (EDD1 = 1) 100 IECR.PRO+ = 1: EDD0 = 1, EDD1 = 0 101 IECR.PRO+ = 1: EDD0 = 1, EDD1 = 1 110 IS pin is high impedance 111 Stand-by mode (IS pin is high impedance) Switch Bypass Monitor 1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) Set Current Sense Multiplexer Configuration 000 Current sense of channel 0 is routed to IS pin 001 Current sense of channel 1 is routed to IS pin 010 Current sense of channel 2 is routed to IS pin 011 Current sense of channel 3 is routed to IS pin 100 IECR.PRO+ = 0: Diagnosis enable of external driver 0 activated (EDD0 = 1) 101 IECR.PRO+ = 0: Diagnosis enable of external driver 1 activated (EDD1 = 1) 100 IECR.PRO+ = 1: EDD0 = 1, EDD1 = 0 101 IECR.PRO+ = 1: EDD0 = 1, EDD1 = 1 110 IS pin is high impedance 111 Stand-by mode (IS pin is high impedance)) Switch Bypass Monitor 1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) SBM 3 r 1 (ON-state) MUX 2:0 r/w SBM 3 r 1) Invalid in stand-by mode Data Sheet 56 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis Field CSOL Bits 3 Type w Description Current Source Switch for Open Load Detection 0 OFF 1 ON Automatic Current Sense Multiplexer Switching during Automatic PWM Generation 0 OFF 1 ON AMUX 4 rw CHCRn Channel Configuration Register W/R r/w RB 1 1 1 ADDR x x 9 0 8 0 7 0 6 5 PHSn 4 3 2 1 0 SYDELn FREQn Field SYDELn n = 0 to 5 Bits 3:2 Type rw Description Delay of Current Sense Synchronization Signal for Channel n 00 No synchronization signal delay 01 Synchronization signal delay 1: 8 / (fPCLK (or fINT)) 10 Synchronization signal delay 2: 16 / (fPCLK (or fINT)) 11 Synchronization signal delay 3: 24 / (fPCLK (or fINT)) Standard Diagnosis CS TER 15 0 14 LHI 13 SBM 12 x 11 CLE 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 2 1 0 ERR3 ERR2 ERR1 ERR0 Field ERRn n = 3 to 0 SBM Bits n Type r Description Error flag Channel n 0 normal operation 1 failure mode occurred Switch Bypass Monitor 1) 0 VDS < VDS(SB) 1 VDS > VDS(SB) 13 r 1) Invalid in stand-by mode Data Sheet 57 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Diagnosis IECR Input, External Drive and Current Source Configuration Register W/R r/w RB 1 0 0 ADDR 0 1 9 0 8 0 7 0 6 0 5 0 4 0 3 COL 2 INCG 1 CSL 0 PRO+ Field PRO+ Bits 0 Type rw Description Configuration of EDD0 and EDD1 to be Compliant to PROFET+ 0 Normal mode 1 EDD0=DEN, EDD1=DSEL Level for Current Source for Open Load Detection 0 Low level 1 High level CSL 1 rw Data Sheet 58 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Serial Peripheral Interface (SPI) 10 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred, while the minimum of 16 bit is also taken into consideration. Therefore the interface provides daisy chain capability even with 8 bit SPI devices. SO SI CS SCLK time MSB MSB 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB SPI_16bit .emf Figure 25 Serial Peripheral Interface 10.1 SPI Signal Description CS - Chip Select: The system micro controller selects the SPOC - BTS6480SF by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: • • The requested information is transferred into the shift register. SO changes from high impedance state to high or low state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration, a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK. TER SI OR 1 0 SO SI CS SCLK S SPI SO S TER.emf Figure 26 Combinatorial Logic for TER Flag CS Low to High transition: • Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored. Data from shift register is transferred into the addressed register. • Data Sheet 59 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Serial Peripheral Interface (SPI) SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 10.5 for further information. SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 10.5 for further information. 10.2 Daisy Chain Capability The SPI of SPOC - BTS6480SF provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 27), in order to build a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain. device 1 SI SO SI device 2 SO SI device 3 SO MO SPI SPI SPI CS CS SCLK SCLK CS MI MCS MCLK Figure 27 Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out occurs at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in daisy chain, three times 16 (or e.g. 16 + 8 +16) bits have to be shifted through the devices. After that, the MCS line must turn high (see Figure 28). Data Sheet 60 Rev. 1.0, 2010-04-12 SCLK SPI_DaisyChain .emf SPOC - BTS6480SF Serial Peripheral Interface (SPI) MI MO MCS MCLK time SO device 1 SI device 1 SO device 2 SI device 2 SO device 3 SI device 3 SPI_DaisyChain2_16bitemf . Figure 28 Data Transfer in Daisy Chain Configuration 10.3 Timing Diagrams tCS(lead) tCS(lag) tSCLK(P) tSCLK(H) tSCLK(L) 0.7VDD tCS(td) 0.7VDD 0.2VDD CS SCLK tSI(su) tSI(h) 0.2VDD SI tSO(en) tSO(v) tSO(dis) 0.7VDD 0.2VDD SO 0.7VDD 0.2VDD SPI Timing.emf Figure 29 Timing Diagram SPI Access Data Sheet 61 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Serial Peripheral Interface (SPI) 10.4 Electrical Characteristics Electrical Characteristics Serial Peripheral Interface (SPI) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Input Characteristics (CS, SCLK, SI) 10.4.1 L level of pin CS VCS(L) SCLK VSCLK(L) SI VSI(L) 10.4.2 H level of pin CS VCS(H) SCLK VSCLK(H) SI VSI(H) 10.4.3 Pull-up resistor at CS pin 10.4.4 Pull-down resistor at pin SCLK RSCLK SI RSI Output Characteristics (SO) 10.4.5 L level output voltage 10.4.6 H level output voltage 10.4.7 Output tristate leakage current Timings 10.4.8 Serial clock frequency 10.4.9 Serial clock period 10.4.10 Serial clock high time 10.4.11 Serial clock low time 10.4.12 Enable lead time (falling CS to rising SCLK) 0.4* – 0 – 0.2* V Symbol Limit Values min. typ. max. Unit Test Conditions VDD VDD = 4.3 V VDD VDD V VDD = 4.3 V RCS 50 50 120 120 180 180 kΩ kΩ ICS = 100 µA – ISCLK = 100 µA ISI = 100 µA 0 0.4 V – 0.4 V V µA MHz ns ns ns ns ns ns ns ns VSO(L) VSO(H) ISO(OFF) fSCLK tSCLK(P) tSCLK(H) tSCLK(L) tCS(lead) VDD - – -10 0 0 200 333 100 166 100 166 200 333 200 333 200 333 20 33 20 33 – – – – – – – – – – – – – – – – – – – VDD 10 5 3 – – – – – – – – – – – – – – – – ISO = -0.5 mA ISO = 0.5 mA VDD = 4.3 V VCS = VDD 1) 2) 10.4.13 Enable lag time (falling SCLK to rising tCS(lag) CS) 10.4.14 Transfer delay time (rising CS to falling CS) 10.4.15 Data setup time (required time SI to falling SCLK) 10.4.16 Data hold time (falling SCLK to SI) tCS(td) tSI(su) tSI(h) VDD = 4.3 V VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V 1) VDD = 4.3 V 2) VDD = 3.0 V Data Sheet 62 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Serial Peripheral Interface (SPI) Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter 10.4.17 Output enable time (falling CS to SO valid) 10.4.18 Output disable time (rising CS to SO tri-state) Symbol Limit Values min. typ. – – – – – – max. ns – – 200 333 ns – – – – 200 333 ns 100 166 2) Unit Test Conditions tSO(en) tSO(dis) 10.4.19 Output data valid time with capacitive tSO(v) load VDD = 4.3 V VDD = 3.0 V 2) CL = 20 pF VDD = 4.3 V VDD = 3.0 V 2) CL = 20 pF VDD = 4.3 V VDD = 3.0 V CL = 20 pF 1) Not subject to production test, specified by design. SPI functional test is performed at fSCLK = 5 MHz. 2) Not subject to production test, specified by design. Data Sheet 63 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Serial Peripheral Interface (SPI) 10.5 CS1) SI SI SI SI SI SO TER SO TER SO TER SPI Protocol 16Bit 15 1 0 1 0 0 0 1 1 14 0 0 x x x x 13 0 0 12 0 0 11 0 0 10 0 0 9 0 x 8 0 x 7 0 x 6 0 x 5 4 3 2 1 0 Write OUT Register OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 x x x x x 0 Read OUT Register Write Configuration and Control Registers ADDR ADDR x x 0 x CLE 0 x x 0 x x x x x x x x x x x x x x x x DATA x x x x x x x x x x x x 0 1 Read Configuration and Control Registers Read Standard Diagnosis Standard Diagnosis LHI SBM 0 x 0 ERR3 ERR2 ERR1 ERR0 Second Frame of Read Command OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 DATA ADDR 1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition. Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame. The standard diagnosis can be accessed either by sending the standard diagnosis read command or it is transmitted after each write command. Field W/R RB Bits 15 14 Type w rw Description 0 1 Read Write Register Bank 0 Read / write to register bank 0 1 Read / write to register bank 1 Transmission Error 0 Previous transmission was successful (modulo 16 clocks received) 1 Previous transmission failed or first transmission after reset Output Control Register of Channel n 0 OFF 1 ON Address Pointer to register for read and write command Data Data written to or read from register selected by address ADDR Diagnosis of Channel n 1) 0 No failure 1 Over temperature, over load or short circuit TER CS r OUTn n = 5 to 0 ADDR DATA ERRn n = 3 to 0 n w 13:10 9:0 n rw rw r Data Sheet 64 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Serial Peripheral Interface (SPI) Field CLE Bits 11 Type r Description External Clock Status 2) 0 fPCLK > fPCLK(TH) 1 fPCLK < fPCLK(TH) Switch Bypass Monitor 2) 0 VDS < VDS(SB) 1 VDS > VDS(SB) Limp Home Enable 3) 0 H-input signal at pin LHI 1 L-input signal at pin LHI SBM 13 r LHI 14 r 1) No ERR-flags available for external drivers 2) Invalid in stand-by mode 3) Not latching information, read of LHI-status during falling CS Data Sheet 65 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Serial Peripheral Interface (SPI) 10.6 Register Overview Register Bank 0 Bit Name OUT PCR DCCR0 DCCR1 DCCR2 DCCR3 DCCR4 DCCR5 15 W/R W/R W/R W/R W/R W/R W/R W/R W/R 14 RB 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 13 12 0 1 0 0 0 0 1 1 11 0 1 0 0 1 1 0 0 10 0 1 0 1 0 1 0 1 9 0 0 0 0 0 0 0 0 8 0 0 7 0 0 6 0 0 5 4 3 2 1 0 ADDR DATA OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 0 0 DC0 DC1 DC2 DC3 DC4 DC5 DCS DPSH PST Note: A readout of an unused register will return the standard diagnosis. Field RB Bits 6 Type - Description Read Bit 0 Read / write to register bank 0 1 Read / write to register bank 1 Address Pointer to register for read and write command Data Data written to or read from register selected by address ADDR Set Output Mode for Channel n 0 Channel n is switched off 1 Channel n is switched on Automatic PWM Generation 0 No automatic PWM generation 1 Automatic PWM generation Device Phase Shift 00 No phase shift 01 Phase shift 1: 8 / (fPCLK (or fINT)) 10 Phase shift 2: 16 / (fPCLK (or fINT)) 11 Phase shift 3: 24 / (fPCLK (or fINT)) Single Duty Cycle for all Channels 0 Duty cycle setting of channel 0 used for all channels 1 Individual duty cycle setting used for each channel Duty Cycle for Channel n during Automatic PWM Generation 000000000 DC value: 0 (channel off) 000000001 DC value: (1 / 256) * 100 000000010 DC value: (2 / 256) * 100 ... 011111111 DC value: (255 / 256) * 100 1xxxxxxxx DC value: 1 (channel 100% on) ADDR DATA OUTn n = 5 to 0 PST 5:4 3:0 n w rw rw 0 rw DPSH 6:4 rw DCS 0 rw DCn n = 0 to 5 8:0 rw Data Sheet 66 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Serial Peripheral Interface (SPI) Register Bank 1 Bit Name IECR HWCR DCR CHCR0 CHCR1 CHCR2 CHCR3 CHCR4 CHCR5 15 W/R W/R R W R W W/R W/R W/R W/R W/R W/R 14 RB 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 13 12 0 0 0 0 0 0 0 0 0 1 1 11 0 1 1 1 1 0 0 1 1 0 0 10 1 0 0 1 1 0 1 0 1 0 1 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 7 0 CLKTRIM CLKTRIM 0 0 0 0 0 0 0 0 0 0 6 0 5 0 CLK CLK 0 0 PSH0 PSH1 PSH2 PSH3 PSH4 PSH5 4 0 0 0 3 2 1 0 ADDR DATA COL INCG CSL PRO+ LED3 LED2 STB LED3 LED2 RST MUX MUX FREQ0 FREQ1 FREQ2 FREQ3 FREQ4 FREQ5 CL CL AMUX SBM AMUX CSOL SYDEL0 SYDEL1 SYDEL2 SYDEL3 SYDEL4 SYDEL5 Note: A readout of an unused register will return the standard diagnosis. Field PRO+ Bits 0 Type rw Description Configuration of EDD0 and EDD1 to be Compliant to PROFET+ Concept 0 Normal mode 1 EDD0=DEN, EDD1=DSEL Level for Current Source for Open Load Detection 0 Low level 1 High level Input Drive Configuration 0 Direct drive mode 1 Assigned drive mode Input Combinatorial Logic Configuration 0 Input signal OR-combined with according OUT register bit 1 Input signal AND-combined with according OUT register bit Clear Latch 0 Thermal and over current latches are untouched 1 Command: Clear all thermal and over current latches Reset Command 0 Normal operation 1 Execute reset command Standby Mode 0 Device is awake 1 Device is in Standby mode Set LED Mode for Channel n 0 Channel n is in bulb mode 1 Channel n is in LED mode CSL 1 rw INCG 2 rw COL 3 rw CL 0 rw RST 1 w STB 1 r LEDn n = 3 to 2 n rw Data Sheet 67 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Serial Peripheral Interface (SPI) Field CLK Bits 5 Type rw Description Clock Mode 1) 0 External Clock input PCLK is used for PWM Mode 1 Internal Clock is used for PWM Mode Internal Clock Trim 000 fINT - 4 kTRIM ... 011 fINT - 1 kTRIM 100 fINT without trimming 101 fINT + 1 kTRIM ... 111 fINT + 3 kTRIM Set Current Sense Multiplexer Configuration in OFF-state 000 IS pin is high impedance 001 IS pin is high impedance 010 IS pin is high impedance 011 IS pin is high impedance 100 IECR.PRO+ = 0: Diagnosis enable of external driver 0 activated (EDD0 = 1) 101 IECR.PRO+ = 0: Diagnosis enable of external driver 1 activated (EDD1 = 1) 100 IECR.PRO+ = 1: EDD0 = 1, EDD1 = 0 101 IECR.PRO+ = 1: EDD0 = 1, EDD1 = 1 110 IS pin is high impedance 111 Stand-by mode (IS pin is high impedance) Set Multiplexer Configuration in ON-state 000 Current sense of channel 0 is routed to IS pin 001 Current sense of channel 1 is routed to IS pin 010 Current sense of channel 2 is routed to IS pin 011 Current sense of channel 3 is routed to IS pin 100 IECR.PRO+ = 0: Diagnosis enable of external driver 0 activated (EDD0 = 1) 101 IECR.PRO+ = 0: Diagnosis enable of external driver 1 activated (EDD1 = 1) 100 IECR.PRO+ = 1: EDD0 = 1, EDD1 = 0 101 IECR.PRO+ = 1: EDD0 = 1, EDD1 = 1 110 IS pin is high impedance 111 Stand-by mode (IS pin is high impedance)) Switch Bypass Monitor 2) 0 VDS < VDS(SB) 1 VDS > VDS(SB) Current Source Switch for Open Load Detection 0 OFF 1 ON Automatic Current Sense Multiplexer Switching (single loop) 0 Automatic current sense multiplexer switching not activated 1 Automatic current sense multiplexer switching activated and proceeding CLKTRIM 8:6 rw MUX 2:0 rw SBM 3 r CSOL 3 w AMUX 5:4 w Data Sheet 68 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Serial Peripheral Interface (SPI) Field FREQn n = 0 to 5 Bits 1:0 Type rw Description PWM Frequency Prescaler Setting for Channel n 00 Normal mode without automatic PWM generation 01 Prescaler 1: fPCLK (or fINT) / 256 10 Prescaler 2: fPCLK (or fINT) / 512 11 Prescaler 4: fPCLK (or fINT) / 1024 Delay of Current Sense Synchronization Signal for Channel n 00 No synchronization signal delay 01 Synchronization signal delay 1: 8 / (fPCLK (or fINT)) 10 Synchronization signal delay 2: 16 / (fPCLK (or fINT)) 11 Synchronization signal delay 3: 24 / (fPCLK (or fINT)) Channel Phase Shift for Channel n 000 No phase shift 001 Phase shift 1: 32/ (fPCLK (or fINT)) 010 Phase shift 2: 64 / (fPCLK (or fINT)) ... 110 Phase shift 6: 192 / (fPCLK (or fINT)) 111 Phase shift 7: 224 / (fPCLK (or fINT)) SYDELn n = 0 to 5 3:2 rw PSHn n = 0 to 5 6:4 rw 1) For avoiding skews it is recommended to change from external to internal clock source or vice versa only during deactivated PWM generator (PCR.PST = 0b). 2) Invalid in stand-by mode Data Sheet 69 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Application Description 11 Application Description V bat 1 5V W D-OUT 500 Ω 100nF 68nF VDD VBB VCC GPIO GPIO 8kΩ 8kΩ IN1 IN2 IN3 OUT0 OUT1 OUT2 OUT3 GND VDD SPI LHI 8k Ω 1 0kΩ W D- OUT 65W 65W 27W 10W GPIO 1kΩ 3.9k Ω ISSY IS µC AD e . g. X C2 2 6 7 2.7k Ω 1nF 3.9k Ω CS SCLK SO SI PWM generator PCLK SPI 3 .9k Ω 3.9k Ω 3.9k Ω IN 1 VBB P RO FE T O UT1 Ch1 GPIO VSS 3.9k Ω E DO0 IN2 DE N ext. driver cont. GND E DD0 E DO1 E DD1 DS E L IS P RO FE T O UT2 Ch2 G ND 10 Ω 2 1 2 For filtering and protec tion purpos es For inc reas ed ISO-puls e robus tnes s Circ uit_PW M_EXT.emf Figure 30 Application Circuit Example Data Sheet 70 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Package Outlines SPOC - BTS6480SF 12 Package Outlines SPOC - BTS6480SF 2.65 MAX. 0.35 x 45˚ 7.6 -0.2 2.45 -0.2 0.23 +0.09 0.7 ±0.2 10.3 ±0.3 0.2 -0.1 1) 0.65 0.33 ±0.08 2) 0.1 C 0.17 M C A-B D 36x D A 36 19 Bottom View 19 36 Ejector Mark 1 18 18 1 B 1) 12.8 -0.2 Index Marking Dimensions in mm Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side GPS01089 Figure 31 PG-DSO-36-43 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 71 8˚ MAX. Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Revision History 13 Revision 1.0 Revision History Date 2010-04-12 Changes Initial Data Sheet Data Sheet 72 Rev. 1.0, 2010-04-12 Edition 2010-04-12 Published by Infineon Technologies AG 81726 Munich, Germany © 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. 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