C161U

Addendum DS1, 2002-07-31 C161U Embedded C166 with USB, USART and SSC SAF C161U-LF, Version 1.3 Please, replace the erroneous description in the C161U Data Sheet, 2001-04-19, by the following correct text: 1 Fast External Interrupts Page 127, second paragraph: The pins of Port 2 (P2.1...P2.0) can individually be programmed to this fast interrupt mode, where also the trigger transition (rising, falling or both) can be selected. The External Interrupt Control register EXICON controls this feature for all 2 pins. EXICON (F1C0H / E0H) 15 00 rw 14 13 00 rw 12 11 00 rw 10 9 00 rw ESFR 8 7 00 rw 6 5 00 rw 4 Reset Value: 0000H 3 2 1 0 EXI1ES rw EXI0ES rw Bit EXIxES Function External Interrupt x Edge Selection Field (x = 1:0) 0 0 Fast external interrupts disabled: standard mode 0 1 Interrupt on positive edge (rising) 1 0 Interrupt on negative edge (falling) 1 1 Interrupt on any edge (rising or falling) Revision History: Previous Version: Major Changes: Addendum 1/6 2002-07-31 C161U SAF C161U-LF External Interrupt Source Control 2 Page 128. External Interrupt Source Control EXISEL register is defined as follows: EXISEL (F1DAH / EDH) 15 14 13 00 rw 12 11 10 9 EXI7SS rw EXI5SS rw ESFR-b 8 7 6 5 4 Reset Value: 0000H 3 00 rw 2 1 00 rw 0 EXI2SS rw EXI4SS rw EXI3SS rw Bit EXI0SS Function 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Must be set to ’00’. Not allowed. Not allowed. Not allowed. Must be set to ’00’. Not allowed. Not allowed. Not allowed. Not applicable. Input from source ASC_RxD @ P3.11. Not allowed. Not allowed. Not applicable. Input from source SSC_RxD @ P3.9. Not allowed. Not allowed. Not applicable. Input from source SSC_SCLK @ P3.13. Not allowed. Not allowed. Not applicable. Input from source USB_suspend interrupt. Not allowed. Not allowed. EXI1SS EXI2SS EXI3SS EXI4SS EXI5SS Addendum 2/6 2002-07-31 C161U SAF C161U-LF Interrupt Subnode Control Bit EXI6SS Function 00 01 10 11 00 01 10 11 Must be set to ’00’. Not allowed. Not allowed. Not allowed. Not applicable. Input from source RTC_INT. Not allowed. Not allowed. EXI7SS 3 Page 130. Interrupt Subnode Control The ISNC register is defined as follows: ISNC (F1DEH / EFH) 15 14 13 12 11 10 9 ESFR-b 8 7 6 5 4 Reset Value: 0000H 3 PLL IE 2 PLL IR 1 RTC T14 IE 0 RTC T14 IR Bit T14IR Function T14 Overflow Interrupt Request Flag ‘0’ No request pending ‘1’ This source has raised an interrupt request T14 Overflow Interrupt Enable Control Bit ‘0’ Interrupt request is disabled ‘1’ Interrupt request is enabled PLL Interrupt Request Flag (OWD Interrupt) ‘0’ No request pending ‘1’ This source has raised an interrupt request PLL Interrupt Enable Control Bit ‘0’ Interrupt request is disabled ‘1’ Interrupt request is enabled T14IE PLLIR PLLIE Note: See Data Sheet, Chapter 3.3 for Clock Generation Concept. Addendum 3/6 2002-07-31 C161U SAF C161U-LF System Startup Configuration 4 Page 369. Table 91 System Startup Configuration C161U’s Supported Modes and Related Reset Configurations P0L.1 (ADP) 0 1 1 1 1 Selected Mode Adapt Mode Normal Mode Internal Boot-ROM Read-Out Not applicable Bootstrap-Loader Mode Selftest Not applicable P0L.5: P0L.2 (SMOD) xxxx 1111 0001 1011 1101 5 Page 109. Note: Interrupt System Structure 1. The X-Bus interrupts xb(0), xb(1) and xb(2), known from other C16x device’s, are connected to the main interrupt node of the respective X-Bus peripheral: UTXRINT (xb(0) and irq(22)), EPECINT (xb(1) and irq(40)) and IOMIOINT (xb(2) and irq(42)). 2. Each entry of the interrupt vector table provides space for two word instructions or one doubleword instruction. The respective vector location results from multiplying the trap number by 4 (4 bytes per entry). 3. One interrupt control register is provided for each interrupt node. All IC registers of the C161U can be found in the SFR list. 4. ISNC register controls the interrupt xb(3). See Data Sheet, Chapter 7.8.3 for further description. Addendum 4/6 2002-07-31 C161U SAF C161U-LF Defining the RTC Time Base 6 Page 296. Defining the RTC Time Base Correct values are indicated blue. Table 67 Oscillator Frequency 32 kHz 1 MHz 4 MHz 5 MHz 8 MHz 10 MHz 12 MHz 16 MHz 20 MHz 24 MHz 25 MHz 32 MHz 50 MHz : RTC Interrupt Periods Divider Factor 1 32 32 32 32 32 32 32 32 32 32 32 32 RTC Input Frequency 32 kHz 31.25 kHz 125 kHz 156.25 kHz 250 kHz 312.5 kHz 375 kHz 500 kHz 625 kHz 750 kHz 781.25 kHz 1 MHz 1.56 MHz 8 8 8 8 8 8 8 8 8 8 8 8 Prescaler Factor RTC_T14INT Period Minimum 31.25 µs 256.0 µs 64.0 µs 51.2 µs 32.0 µs 25.6 µs 21.3 µs 16.0 µs 12.8 µs 10.67 µs 10.24 µs 8.0 µs 5.12 µs Maximum 2.048 s 16.77 s 4.194 s 3.355 s 2.097 s 1.678 s 1.398 s 1.049 s 0.839 s 0.699 s 0.671 s 0.524 s 0.336 s Table 68 RTC Input Frequency 32 kHz 31.25 kHz 125 kHz 156.25 kHz 250 kHz 312.5 kHz 375 kHz 500 kHz RTC Reload Values Reload Value A T14REL 8300H F0BEH C2F7H B3B5H 85EEH 6769H 48E5H 0BDCH Base 1.000 s 0.999 s 1.000 s 0.999 s 1.000 s 1.000 s 1.000 s 1.000 s Reload Value B T14REL F380H FE79H F9E5H F85FH F3CBH F0BEH EDB0H E796H Base 100.0 ms 100.1 ms 100.0 ms 99.9 ms 100.0 ms 99.9 ms 100.0 ms 100.0 ms Reload Value C T14REL FFE0H FFFCH FFF0H FFECH FFE1H FFD9H FFD1H FFC1H Base 1.000 ms 1.024 ms 1.024 ms 1.024 ms 0.992 ms 0.998 ms 1.003 ms 1.008 ms Addendum 5/6 2002-07-31 C161U SAF C161U-LF Defining the RTC Time Base Table 68 RTC Input Frequency 625 kHz 750 kHz 781.25 kHz 1 MHz 1.56 MHz RTC Reload Values (cont’d) Reload Value A T14REL Base Reload Value B T14REL E17BH DB61H D9DAH CF2CH B3B5H Base 100.0 ms 100.0 ms 100.0 ms 100.0 ms 99.9 ms Reload Value C T14REL FFB2H FFA2H FF9EH FF83H FF3DH Base 0.998 ms 1.003 ms 1.004 ms 1.000 ms 0.998 ms Addendum 6/6 2002-07-31