C501

Microcomputer Components 8-Bit CMOS Microcontroller C501 Data Sheet 04.97 C501 Data Sheet Revision History : Previous Releases : Page (previous version) general 4 5 5-7 11 8, 9, 10 13 14 15-18 17 41 4 5 5-7 11 8, 9, 10 13 14 15 16-18 17 25-28 31 41 43, 44 Page (new version) 1997-04-01 11.92, 11.93, 08.94, 08.95, 10.96 Subjects (changes since last revision) C501G-1E OTP version included Ordering information resorted and C501G-1E types added Table with literature hints added Pin configuration logic symbol for pins EA/Vpp and ALE/PROG updated Pin description for ALE/PROG and EA/Vpp completed Port 1, 3, 2 pin description: “bidirectional” replaced by “quasibidirectional” Block diagram updated for C501G-1E New design of register (PSW) description “Memory organization” added Actualized design of the SFR tables Reset value of T2CON corrected Description for the C501-1E OTP version added DC characteristics for C501-1E added Timing “External Clock Drive” now behind “Data Memory Cycle” AC characteristics for C501-1E added Edition 1997-04-01 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. 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If they fail, it is reasonable to assume that the health of the user may be endangered. 8-Bit CMOS Microcontroller C501 Preliminary • • • • • • • • • • • • • Fully compatible to standard 8051 microcontroller Versions for 12/24/40 MHz operating frequency Program memory : completely external (C501-L) 8K × 8 ROM (C501-1R) 8K × 8 OTP memory (C501-1E) 256 × 8 RAM Four 8-bit ports Three 16-bit timers / counters (timer 2 with up/down counter feature) USART Six interrupt sources, two priority levels Power saving modes Quick Pulse programming algorithm (C501-1E only) 2-Level program memory lock (C501-1E only) P-DIP-40, P-LCC-44, and P-MQFP-44 package Temperature ranges : SAB-C501 TA : 0 ˚C to 70 ˚C SAF-C501 TA : – 40 ˚C to 85 ˚C Power Saving Modes T0 T2 T1 RAM 256 x 8 Port 0 Ι /O Port 1 CPU USART Port 2 Ι /O Ι /O 8K x 8 ROM (C501-1R) 8K x 8 OTP (C501-1E) Port 3 Ι /O MCA03238 Figure 1 C501G Functional Units Semiconductor Group 3 1997-04-01 C501 The C501-1R contains a non-volatile 8K × 8 read-only program memory, a volatile 256 × 8 read/ write data memory, four ports, three 16-bit timers counters, a seven source, two priority level interrupt structure and a serial port. The C501-L is identical, except that it lacks the program memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip. The term C501 refers to all versions within this specification unless otherwise noted. Further, the term C501 refers to all versions which are available in the different temperature ranges, marked with SAB-C501... or SAF-C501.... . Ordering Information Type SAB-C501G-LN SAB-C501G-LP SAB-C501G-LM SAB-C501G-L24N SAB-C501G-L24P SAB-C501G-L24M SAB-C501G-L40N SAB-C501G-L40P SAB-C501G-L40M SAF-C501G-L24N SAF-C501G-L24P SAB-C501G-1RN SAB-C501G-1RP SAB-C501G-1RM Ordering Code Package Q67120-C969 Q67120-C968 Q67127-C970 Q67120-C1001 Q67120-C999 Q67127-C1014 Q67120-C1002 Q67120-C1000 Q67127-C1009 Q67120-C1011 Q67120-C1010 Q67120-DXXX Q67120-DXXX Q67127-DXXX Description (8-Bit CMOS microcontroller) P-LCC-44 for external memory (12 MHz) P-DIP-40 P-MQFP-44 P-LCC-44 for external memory (24 MHz) P-DIP-40 P-MQFP-44 P-LCC-44 for external memory (40 MHz) P-DIP-40 P-MQFP-44 P-LCC-44 for external memory (24 MHz) P-MQFP-44 ext. temp. – 40 ˚C to 85 ˚C P-LCC-44 with mask-programmable ROM (12 MHz) P-DIP-40 P-MQFP-44 P-LCC-44 with mask-programmable ROM (24 MHz) P-DIP-40 P-MQFP-44 P-LCC-44 with mask-programmable ROM (40 MHz) P-DIP-40 P-MQFP-44 P-LCC-44 P-DIP-40 P-LCC-44 P-DIP-40 P-LCC-44 P-DIP-40 P-LCC-44 P-DIP-40 P-LCC-44 P-DIP-40 with mask-programmable ROM (24 MHz) ext. temp. – 40 ˚C to 85 ˚C with OTP memory (12 MHz) with OTP memory (12 MHz)) ext. temp. – 40 ˚C to 85 ˚C with OTP memory (24 MHz) with OTP memory (24 MHz)) ext. temp. – 40 ˚C to 85 ˚C SAB-C501G-1R24N Q67120-DXXX SAB-C501G-1R24P Q67120-DXXX SAB-C501G-1R24M Q67127-DXXX SAB-C501G-1R40N Q67120-DXXX SAB-C501G-1R40P Q67120-DXXX SAB-C501G-1R40M Q67127-DXXX SAF-C501G-1R24N SAF-C501G-1R24P SAB-C501G-1EN SAB-C501G-1EP SAF-C501G-1EN SAF-C501G-1EP SAB-C501G-1E24N SAB-C501G-1E24P SAF-C501G-1E24N SAF-C501G-1E24P Q67120-DXXX Q67120-DXXX Q67120-C1054 Q67120-C1056 Q67120-C2002 Q67120-C2003 Q67120-C2005 Q67120-C2006 Q67120-C2008 Q67120-C2009 Semiconductor Group 4 1997-04-01 C501 Note: Versions for extended temperature range – 40 ˚C to 110 ˚C (SAH-C501G) on request. The ordering number of ROM types (DXXX extensions) is defined after program release (verification) of the customer. Additional Literature For further information about the C501 the following literature is available : Title C501 8-Bit CMOS Microcontroller User’s Manual C500 Microcontroller Family Architecture and Instruction Set User’s Manual C500 Microcontroller Family - Pocket Guide Ordering Number B158-H6723-X-X-7600 B158-H6987-X-X-7600 B158-H6986-X-X-7600 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 N.C VCC 6 P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP N.C. ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 C501 18 19 20 21 22 23 24 25 26 27 28 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS N.C. P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 MCP03214 Figure 2 Pin Configuration P-LCC-44 Package (Top view) Semiconductor Group 5 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 1997-04-01 C501 T2/P1.0 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 C501 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 MCP03215 VSS Figure 3 Pin Configuration P-DIP-40 Package (top view) Semiconductor Group 6 1997-04-01 C501 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC N.C. P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 C501 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP N.C. ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 N.C. VSS XTAL1 XTAL2 RD/P3.7 WR/P3.6 P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 MCP03216 Figure 4 Pin Configuration P-MQFP-44 Package (top view) VCC VSS XTAL1 XTAL2 Port 0 8-Bit Digital Ι /O Port 1 8-Bit Digital Ι /O RESET EA /VPP ALE/PROG PSEN C501 Port 2 8-Bit Digital Ι /O Port 3 8-Bit Digital Ι /O MCL03217 Figure 5 Logic Symbol Semiconductor Group 7 1997-04-01 C501 Table 1 Pin Definitions and Functions Symbol P1.0 – P1.7 2–9 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 1–8 40–44, 1–3, I/O Port 1 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 1 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 1 also contains the timer 2 pins as secondary function. The output latch corresponding to a secondary function must be pro-grammed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 1, as follows: P1.0 T2 Input to counter 2 P1.1 T2EX Capture - Reload trigger of timer 2 / Up-Down count I/O*) Function 2 3 *) I = Input O = Output 1 2 40 41 Semiconductor Group 8 1997-04-01 C501 Table 1 Pin Definitions and Functions (cont’d) Symbol P3.0 – P3.7 11, 13–19 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 10–17 5, 7–13 I/O Port 3 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 3 also contains the interrupt, timer, serial port 0 and external memory strobe pins which are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 R×D receiver data input (asynchronous) or data input output (synchronous) of serial interface 0 P3.1 T×D transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 P3.2 INT0 interrupt 0 input/timer 0 gate control P3.3 INT1 interrupt 1 input/timer 1 gate control P3.4 T0 counter 0 input P3.5 T1 counter 1 input P3.6 WR the write control signal latches the data byte from port 0 into the external data memory P3.7 RD the read control signal enables the external data memory to port 0 I/O*) Function 11 10 5 13 11 7 14 15 16 17 18 12 13 14 15 16 8 9 10 11 12 19 17 13 *) I = Input O = Output Semiconductor Group 9 1997-04-01 C501 Table 1 Pin Definitions and Functions (cont’d) Symbol XTAL2 20 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 18 14 – XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed. Port 2 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-up resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. I/O*) Function XTAL1 21 19 15 – P2.0 – P2.7 24–31 21–28 18–25 I/O *) I = Input O = Output Semiconductor Group 10 1997-04-01 C501 Table 1 Pin Definitions and Functions (cont’d) Symbol PSEN 32 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 29 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. Remains high during internal program execution. RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC. The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. For the C501-1E this pin is also the program pulse input (PROG) during OTP memory programming. External Access Enable When held at high level, instructions are fetched from the internal ROM (C501-1R and C501-1E) when the PC is less than 2000H. When held at low level, the C501 fetches all instructions from external program memory. For the C501-L this pin must be tied low. This pin also receives the programming supply voltage VPP during OTP memory programming (C501-1E) only). I/O*) Function RESET 10 9 4 I ALE/PROG 33 30 27 I/O EA/VPP 35 31 29 I *) I = Input O = Output Semiconductor Group 11 1997-04-01 C501 Table 1 Pin Definitions and Functions (cont’d) Symbol P0.0 – P0.7 43–36 Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 39–32 37–30 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-up resistors when issuing 1s. Port 0 also outputs the code bytes during program verification in the C501-1R and C501-1E. External pull-up resistors are required during program verification. Circuit ground potential Supply terminal for all operating modes No connection I/O*) Function VSS VCC N.C. 22 44 1, 12, 23, 34 20 40 – 16 38 6, 17, 28, 39 – – – *) I = Input O = Output Semiconductor Group 12 1997-04-01 C501 Functional Description The C501 is fully compatible to the standard 8051 microcontroller family. It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational characteristics of the 8051microcontroller family, the C501 incorporates some enhancements in the timer 2 unit. Figure 6 shows a block diagram of the C501. V CC V SS XTAL1 XTAL2 C501 RAM C501-1R : ROM C501-1E : OTP 8K x 8 OSC & Timing 256 x 8 RESET ALE/PROG PSEN EA/VPP CPU Timer 0 Timer 1 Port 1 Timer 2 Port 2 Interrupt Unit Serial Channel (USART) Port 3 Port 3 8-Bit Digit. Ι /O Port 2 8-Bit Digit. Ι /O Port 0 8-Bit Digit. Ι /O Port 0 Port 1 8-Bit Digit. Ι /O MCB03219 Figure 6 Block Diagram of the C501 Semiconductor Group 13 1997-04-01 C501 CPU The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 µs 24 MHz: 500 ns, 40 MHz : 300 ns). Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. Semiconductor Group 14 1997-04-01 C501 Memory Organization The C501 CPU manipulates data and operands in the following four address spaces: – – – – up to 64 Kbyte of internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area Figure 7 illustrates the memory address spaces of the C501. FFFF H FFFF H External External Indirect Address FF H Internal RAM 2000 H 1FFF H Internal (EA = 1) External (EA = 0) 0000 H "Code Space" 0000 H "Data Space" Internal RAM 80 H Direct Address Special Function Register 7F H 00 H FF H 80 H "Internal Data Space" MCD03224 Figure 7 C501 Memory Map Semiconductor Group 15 1997-04-01 C501 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 27 special function registers (SFRs) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The SFRs of the C501 are listed in table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C501. Table 3 illustrates the contents of the SFRs in numeric order of their addresses. Semiconductor Group 16 1997-04-01 C501 Table 2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP IE IP P0 P1 P2 P3 PCON 2) SBUF SCON TCON TH0 TH1 TL0 TL1 TMOD T2CON T2MOD RC2H RC2L TH2 TL2 Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Interrupt Enable Register Interrupt Priority Register Port 0 Port 1 Port 2 Port 3 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture Register, High Byte Timer 2 Reload/Capture Register, Low Byt Timer 2 High Byte Timer 2 Low Byte Power Control Register Address Contents after Reset E0H 1) F0H 1) 83H 82H D0H 1) 81H A8H1) B8H 1) 80H 1) 90H 1) A0H 1) B0H 1) 87H 99H 98H 1) 88H 1) 8CH 8DH 8AH 8BH 89H C8H 1) C9H CBH CAH CDH CCH 87H 00H 00H 00H 00H 00H 07H 0X000000B 3) XX000000B 3) FFH FFH FFH FFH 0XXX0000B 3) XXH 3) 00H 00H 00H 00H 00H 00H 00H 00H XXXXXXX0B 3) 00H 00H 00H 00H 0XXX0000B 3) Interrupt System Ports Serial Channel Timer 0 / Timer 1 Timer 2 Pow. Sav. PCON 2) Modes 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved Semiconductor Group 17 1997-04-01 C501 Table 3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) 80H2) P0 81H 82H 83H 87H SP DPL DPH PCON FFH 07H 00H 00H 0XXX0000B 00H 00H 00H 00H 00H 00H FFH 00H XXH FFH 0X000000B FFH XX00. 0000B 00H XXXXXXX0B 00H 00H 00H 00H 00H 00H 00H .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 .6 .6 .6 .6 .5 .5 .5 .5 – TF0 M1 .5 .5 .5 .5 .5 SM2 .5 .5 ET2 T1 PT2 RCLK – .5 .5 .5 .5 F0 .5 .5 .4 .4 .4 .4 – TR0 M0 .4 .4 .4 .4 .4 REN .4 .4 ES T0 PS TCLK – .4 .4 .4 .4 RS1 .4 .4 .3 .3 .3 .3 GF1 IE1 GATE .3 .3 .3 .3 .3 TB8 .3 .3 ET1 INT1 PT1 .2 .2 .2 .2 GF0 IT1 C/T .2 .2 .2 .2 .2 RB8 .2 .2 EX1 INT0 PX1 .1 .1 .1 .1 PDE IE0 M1 .1 .1 .1 .1 .1 TI .1 .1 ET0 TxD PT0 C/T2 – .1 .1 .1 .1 F1 .1 .1 .0 .0 .0 .0 IDLE IT0 M0 .0 .0 .0 .0 .0 RI .0 .0 EX0 RxD PX0 CP/RL2 DCEN .0 .0 .0 .0 P .0 .0 SMOD – TF1 GATE .7 .7 .7 .7 .7 SM0 .7 .7 EA RD – TF2 – .7 .7 .7 .7 CY .7 .7 TR1 C/T .6 .6 .6 .6 .6 SM1 .6 .6 – WR – EXF2 – .6 .6 .6 .6 AC .6 .6 88H 2) TCON 89H 8AH 8BH 8CH 8DH TMOD TL0 TL1 TH0 TH1 90H2) P1 98H2) SCON 99H A8H 2) SBUF IE A0H2) P2 B0H2) P3 B8H2) IP C8H2) T2CON C9H T2MOD CAH RC2L CBH RC2H CCH TL2 CDH TH2 D0H2) PSW E0H2) ACC F0H2) B EXEN2 TR2 – .3 .3 .3 .3 RS0 .3 .3 – .2 .2 .2 .2 OV .2 .2 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group 18 1997-04-01 C501 Timer / Counter 0 and 1 Timer/counter 0 and 1 can be used in four operating modes as listed in table 4. Table 4 Timer/Counter 0 and 1 Operating Modes Mode 0 1 2 3 Description Gate 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit autoreload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops X X X X TMOD C/T X X X X M1 0 1 0 1 M0 0 1 0 1 Input Clock internal external (max) fOSC/12 × 32 fOSC/12 fOSC/12 fOSC/12 fOSC/24 × 32 fOSC/24 fOSC/24 fOSC/24 In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count rate is fOSC/12. In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INTO and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 8 illustrates the input clock logic. f OSC ÷ 12 C/T TMOD 0 f OSC/12 P3.4/T0 P3.5/T1 max f OSC/24 TR 0/1 TCON Gate TMOD P3.2/INT0 P3.3/INT1 =1 _