C505L

U se r’ s M an ual , No v . 1 99 9 C505L 8-Bit CMOS Microcontroller Microcontrollers Never stop thinking. Edition 10.99 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 1999. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. U se r’ s M an ual , No v . 1 99 9 C505L 8-Bit CMOS Microcontroller Microcontrollers Never stop thinking. C505L User’s Manual Revision History: Previous Version: Page several Table 3-3 Table 3-5 Figure 5-3, Figure 5-4, Figure 5-5 Figure 7-1 Page 8-1 Page 8-6 10.99 04.99 Subjects (major changes since last revision) Minor changes on title pages VCC is replaced by VDD. Note 6 added. Note 2 added. Figures changed. Figure 6-40 New version of Figure imported. New version of Figure imported. New variable time-out period for programmable watchdog timer. 3rd indent text title in bold: external is removed. Chapter 10 Throughout this chapter the term C505l-4E is replaced by C505L. Chapter 10 Pages 10-7 to 10-14 were missing, now included. Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation licensed to Infineon. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com General Information C505L Contents 1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.1.1 6.1.2 6.1.2.1 6.1.2.2 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 CPU Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Program Memory, “Code Space” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Data Memory, “Data Space” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 General Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 XRAM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 XRAM/LCD Controller/RTC Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Accesses to XRAM using the DPTR (16-bit Addressing Mode) . . . . . . . . . . . . . . . . . .3-5 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode) . . . . . . . . . . .3-5 Reset Operation of the XRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9 Behavior of Port 0 and Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 PSEN, Program Store Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . . . . . . . . . .4-3 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 Eight Datapointers for Faster External Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 The Importance of Additional Datapointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 How the eight Datapointers of the C505L are Implemented . . . . . . . . . . . . . . . . . . . . .4-6 Advantages of Multiple Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7 Application Example and Performance Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7 System Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6 System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Standard I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4 Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6 Port 1 and Port 3 Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7 User’s Manual I-1 10.99 General Information C505L Contents 6.1.2.3 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 6.1.3.4 6.1.4 6.1.5 6.1.6 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5 6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.2.2.4 6.2.2.5 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.3.3.2 6.3.3.3 6.3.4 6.3.5 6.3.6 6.4 6.4.1 6.4.1.1 6.4.2 6.4.2.1 6.4.2.2 6.4.3 6.4.3.1 6.4.4 6.4.5 6.4.6 6.4.6.1 6.4.7 Page Port 2 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8 Detailed Output Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10 Type B Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10 Type C Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12 Type D Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13 Type E and F Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-14 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-16 Read-Modify-Write Feature of Ports 0 to 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-17 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-18 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-18 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25 Timer/Counter 2 with Additional Compare/Capture/Reload . . . . . . . . . . . . . . . . . . . .6-26 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28 Timer 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-33 Compare Function of Registers CRC, CC1 to CC3 . . . . . . . . . . . . . . . . . . . . . . . . . .6-35 Using Interrupts in Combination with the Compare Function . . . . . . . . . . . . . . . . . . .6-41 Capture Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-43 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-45 Multiprocessor Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-46 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-46 Baudrate Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-48 Baudrate in Mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-49 Baudrate in Mode 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-49 Baudrate in Mode 1 and 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-50 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-56 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-59 LCD Controller Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-62 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-62 Display Module Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-62 LCD Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-63 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-63 Digit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-64 LCD Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-65 LCD Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-66 Row Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-67 Column Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-68 Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-72 D/A Converter (Reference Voltage Generator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-72 Power Saving Mode Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-72 User’s Manual I-2 10.99 General Information C505L Contents 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.2.1 8.2.2 9 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.5 10 10.1 10.2 10.3 Page Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-73 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-73 Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-74 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-77 Real-Time Clock Wake-up Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-78 Power-saving Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-79 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-80 A/D Converter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-80 A/D Converter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-82 A/D Converter Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-86 A/D Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87 A/D Converter Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-91 A/D Converter Analog Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-92 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-12 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-13 How Interrupts Are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16 Interrupt Response Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Programmable WatchDog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2 Watchdog Timer Control / Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 Oscillator Watchdog Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6 Detailed Description of the Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . .8-7 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 Power-saving Mode Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 Slow-down Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6 Software Power-down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7 Invoking Software Power-down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8 Exit from Software Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9 State of Pins in Software-initiated Power-saving Mode . . . . . . . . . . . . . . . . . . . . . . .9-12 OTP Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 User’s Manual I-3 10.99 General Information C505L Contents 10.4 10.4.1 10.4.2 10.5 10.6 10.6.1 10.7 11 Page Programming Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5 Basic Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6 Program/Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7 Programming and Reading Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-9 Access of Version Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11 OTP Verification Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-12 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 User’s Manual I-4 10.99 Introduction C505L 1 Introduction The C505L microcontroller is a member of the Infineon Technologies C500 family of 8-bit microcontrollers. The C505 is fully compatible to the standard 8051 microcontroller. Additionally the C505L provides a 128-segment Liquid-Crystal Display (LCD) controller, real-rime clock, a 10-bit A/D Converter, on-chip RAM, and 32 Kbytes of on-chip OTP memory, extended power save provisions and RFI related improvements. With a maximum external clock rate of 20 MHz it achieves a 300 ns instruction cycle time. The C505L contains a 32k × 8 one time programmable (OTP) program memory. This device operates with internal program memory only. On-Chip Emulation Support Module Oscillator Watchdog 10-Bit ADC Timer 2 4-Channel PWM Watchdog Timer Real-Time Clock XRAM 256 x 8 T0 T1 CPU RAM 256 x 8 Port 0 Port 1 8 Digit. I / O 8 Analog Inputs / 8 Digit. I / O 8 Digit. I / O 2 LCD Outputs / 8 Digit. I / O 8 LCD Outputs / 8 Digit. I / O 6 LCD Outputs / 6 Digit. I / O MCB03832 8-Bit USART 8 Datapointers Port 2 Port 3 OTP 32k x 8 128-Segment LCD Control Port 4 Port 5 20 LCD Outputs Figure 1-1 C505L Functional Units User’s Manual 1-1 10.99 Introduction C505L Listed below is a summary of the main features of the C505L family: • Fully compatible with the standard 8051 microcontroller • Superset of the 8051 architecture with 8 datapointers • Up to 20 MHz operating frequency – 375 ns instruction cycle time @ 16 MHz – 300 ns instruction cycle time @ 20 MHz (50% duty cycle) • Program Memory – 32K bytes of on-chip OTP memory – Externally expandable up to 64 Kbytes • 256-byte on-chip RAM • 256-byte on-chip XRAM • Five 8-bit and one 6-bit digital I/O ports (Port 5 with 6 bits only) – Port 1 with mixed analog/digital I/O capability – Port 3 with 2 LCD output lines as secondary functions – Port 4 and 5 with 8 and 6 LCD output lines respectively as secondary functions • Three 16-bit timers/counters – Timer 0 / 1 (C501 compatible) – Timer 2 with 4 channels for 16-bit capture/compare operation • 128-segment LCD Controller – 1/4 duty cycle drive – 4 row and 32 column outputs – On-chip programmable reference voltage generation – 20 dedicated LCD output lines (4 rows + 16 columns) • Real-Time Clock – 47-bit digital clock counter – Input frequency of 32.768 kHz required – Operates in a special power down mode • Full duplex serial interface with programmable baudrate generator (USART) • 10-bit A/D Converter with 8 multiplexed inputs • Twelve interrupt sources with four priority levels • On-chip emulation support logic (Enhanced HooksTM 1)) • Programmable 15-bit Watchdog Timer • Oscillator Watchdog • Fast power-on reset • Power-saving modes – Slow-down mode – Idle mode (can be combined with slow-down mode) – 3 special power down modes – Software power-down mode with wake up capability through INT0 pin or Real-Time Clock • P-MQFP-80 package TA = 0 to 70 °C • Temperature ranges: SAB-C505L SAF-C505L TA = – 40 to 85 °C TA = – 40 to 110 °C (max. operating frequency: 12 MHz) SAH-C505L TA = – 40 to 125 °C (max. operating frequency: 12 MHz) SAK-C505L 1 “Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. User’s Manual 1-2 10.99 Introduction C505L V DD V SS V AREF V AGND XTAL1 XTAL2 RESET EA ALE PSEN XTAL3 XTAL4 R0 R3 C0 C31 Port 4 8-Bit Digital I / O Port 5 6-Bit Digital I / O MCL03833 Port 0 8-Bit Digital I / O Port 1 8-Bit Digital I / O / 8-Bit Analog Inputs C505L Port 2 8-Bit Digital I / O Port 3 8-Bit Digital I / O Figure 1-2 Logic Symbol User’s Manual 1-3 10.99 Introduction C505L 1.1 Pin Configuration This section shows the pin configuration of the C505L in the P-MQFP-80 package. P0.7 / AD7 P0.6 / AD6 P0.5 / AD5 P0.4 / AD4 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V DD V SS P1.0 / AN0 / INT3 / CC0 P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3 P1.4 / AN4 P1.5 / AN5 / T2EX P1.6 / AN6 / CLKOUT P1.7 / AN7 / T2 V AREF V AGND 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 39 62 38 63 37 64 36 65 35 66 34 67 33 68 32 69 31 70 C505L 30 71 29 72 28 73 27 74 26 75 25 76 24 77 23 78 22 79 80 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P2.0 / AD8 P2.1 / AD9 P2.2 / AD10 P2.3 / AD11 P2.4 / AD12 P2.5 / AD13 P2.6 / AD14 P2.7 / AD15 XTAL3 XTAL4 V DD V SS XTAL1 XTAL2 EA ALE PSEN RESET P3.0 / RxD P3.1 / TxD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 / C31 P3.5 / T1 / C30 P3.6 / WR P3.7 / RD P5.5 / C29 P5.4 / C28 P5.3 / C27 P5.2 / C26 P5.1 / C25 P5.0 / C24 P4.7 / C23 P4.6 / C22 P4.5 / C21 P4.4 / C20 P4.3 / C19 P4.2 / C18 P4.1 / C17 P4.0 / C16 R0 R1 R2 R3 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 MCP03834 Figure 1-3 Pin Configuration, P-MQFP-80-1 Package (top view) User’s Manual 1-4 10.99 Introduction C505L 1.2 Pin Definitions and Functions This section describes all external signals and functions of the C505L. Table 1-1 Pin Definitions and Functions Symbol R0-R3 Pin Number 1-4 I/O*) O Function LCD Row Outputs Output of LCD controller row lines. These pins are driven by the LCD controller and drive the row input lines of the external LCD display. Enabling the LCD Controller makes these pins available for LCD output levels. R0 LCD row output 0 R1 LCD row output 1 R2 LCD row output 2 R3 LCD row output 3 These pins should not be used for input. LCD Column Outputs Output of LCD controller column lines 0 to 15. These pins are driven by the LCD controller and drive the column input lines of the external LCD display. Enabling the LCD controller makes these pins available for LCD output levels. C0 LCD column output 0 C1 LCD column output 1 C2 LCD column output 2 C3 LCD column output 3 C4 LCD column output 4 C5 LCD column output 5 C6 LCD column output 6 C7 LCD column output 7 C8 LCD column output 8 C9 LCD column output 9 C10 LCD column output 10 C11 LCD column output 11 C12 LCD column output 12 C13 LCD column output 13 C14 LCD column output 14 C15 LCD column output 15 These pins should not be used for input. 1 2 3 4 C0-C15 5-20 O 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 *) I = Input O = Output User’s Manual 1-5 10.99 Introduction C505L Table 1-1 Pin Definitions and Functions (cont’d) Symbol P4.0-P4.7 Pin Number 21-28 I/O*) I/O Function Port 4 is a 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 4 pins that have a 1 written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup transistors. Port 4 pins can also be configured as LCD column outputs. The secondary functions are assigned to the pins of port 4 as follows: P4.0 / C16 LCD column output 16 P4.1 / C17 LCD column output 17 P4.2 / C18 LCD column output 18 P4.3 / C19 LCD column output 19 P4.4 / C20 LCD column output 20 P4.5 / C21 LCD column output 21 P4.6 / C22 LCD column output 22 P4.7 / C23 LCD column output 23 These pins should not be used for input when configured as LCD output pins. Port 5 is a 6-bit quasi-bidirectional port with internal pull-up arrangement. Port 5 pins that have a 1 written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup transistors. Port 5 pins can also be configured as LCD column outputs. The secondary functions are assigned to the pins of port 5 as follows: P5.0 / C24 LCD column output 24 P5.1 / C25 LCD column output 25 P5.2 / C26 LCD column output 26 P5.3 / C27 LCD column output 27 P5.4 / C28 LCD column output 28 P5.5 / C29 LCD column output 29 These pins should not be used for input when configured as LCD output pins. 21 22 23 24 25 26 27 28 P5.0-P5.5 29-34 I/O 29 30 31 32 33 34 *) I = Input O = Output User’s Manual 1-6 10.99 Introduction C505L Table 1-1 Pin Definitions and Functions (cont’d) Symbol P3.7-P3.0 Pin Number 35-42 I/O*) I/O Function Port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 3 pins that have a 1 written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup transistors. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR). P3.4 and P3.5 can also be configured as LCD column outputs C31 and C30 respectively. These pins should not be used for input when configured as LCD output pins. The secondary functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface External interrupt 0 input / timer 0 gate P3.2 / INT0 control input External interrupt 1 input / timer 1 gate P3.3 / INT1 control input P3.4 / T0 / C31 Timer 0 counter input / LCD column 31 output P3.5 / T1 / C30 Timer 1 counter input / LCD column 30 output WR control output; latches the data P3.6 / WR byte from port 0 into the external data memory RD control output; enables the external P3.7 / RD data memory 42 41 40 39 38 37 36 35 *) I = Input O = Output User’s Manual 1-7 10.99 Introduction C505L Table 1-1 Pin Definitions and Functions (cont’d) Symbol RESET Pin Number 43 I/O*) I Function RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VDD. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation. The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every three oscillator periods except during an external data memory access. When instructions are executed from internal program memory (EA = 1), the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. External Access Enable This pin must be held at high level. Instructions are fetched from the internal OTP memory when the PC is less than 8000H. Instructions are fetched from external program memory, when the PC is greater than 7FFFH. This pin must not be held at low level. PSEN 44 O ALE 45 O EA 46 I *) I = Input O = Output User’s Manual 1-8 10.99 Introduction C505L Table 1-1 Pin Definitions and Functions (cont’d) Symbol XTAL2 XTAL1 Pin Number 47 48 I/O*) O I Function XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics (refer to Data Sheet) must be observed. XTAL4 Output of the inverting real-time clock oscillator amplifier. XTAL3 Input to the inverting real-time clock oscillator amplifier. To drive the real-time clock from an external clock source, XTAL3 should be driven, while XTAL4 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics (refer to Data Sheet) must be observed. XTAL4 XTAL3 51 52 O I *) I = Input O = Output User’s Manual 1-9 10.99 Introduction C505L Table 1-1 Pin Definitions and Functions (cont’d) Symbol P2.7-P2.0 Pin Number 53-60 I/O*) I/O Function Port 2 is a an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have a 1 written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing 1 s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register and uses only the internal pullup resistors. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have a 1 written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing 1 s. P0.7-P0.0 61-68 I/O *) I = Input O = Output User’s Manual 1-10 10.99 Introduction C505L Table 1-1 Pin Definitions and Functions (cont’d) Symbol P1.0-P1.7 Pin Number 71-78 I/O*) I/O Function Port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 1 pins can be used for digital input/output or as analog inputs to the A/D converter. Port 1 pins that have a 1 written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. As inputs, port 1 pins being pulled low externally will source current ( I IL , in the DC characteristics) because of the internal pullup transistors. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. As secondary digital functions, port 1 contains the interrupt, timer, clock, capture and compare pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). The secondary functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / INT3 / CC0 Analog input channel 0 interrupt 3 input / capture/compare channel 0 I/O P1.1 / AN1 / INT4 / CC1 Analog input channel 1/ interrupt 4 input / capture/compare channel 1 I/O P1.2 / AN2 / INT5 / CC2 Analog input channel 2 / interrupt 5 input / capture/compare channel 2 I/O P1.3 / AN3 / INT6 / CC3 Analog input channel 3 interrupt 6 input / capture/compare channel 3 I/O P1.4 / AN4 Analog input channel 4 P1.5 / AN5 / T2EX Analog input channel 5 / timer 2 external reload / trigger input P1.6 / AN6 / CLKOUT Analog input channel 6 / system clock output P1.7 / AN7 / T2 Analog input channel 7 / timer/counter 2 input 71 72 73 74 75 76 77 78 *) I = Input O = Output User’s Manual 1-11 10.99 Introduction C505L Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number 79 80 49, 70 50, 69 I/O*) – – – – Function Reference voltage for the A/D converter. Reference ground for the A/D converter. Ground (0 V) Power Supply (+ 5 V) VAREF VAGND VSS VDD *) I = Input O = Output User’s Manual 1-12 10.99 Fundamental Structure C505L 2 Fundamental Structure The C505L is fully compatible with the architecture of the standard 8051/C501 microcontroller family. While maintaining all architectural and operational characteristics of the C501, the C505L incorporates a Central Processing Unit (CPU) with 8 datapointers, an 10-bit A/D converter, a 4-channel capture/compare unit, a 128-segment LCD controller unit, a real-time clock unit, an XRAM data memory as well as some enhancements in the Fail Save Mechanism Unit. Figure 2-1 shows a block diagram of the C505L. User’s Manual 2-1 10.99 Fundamental Structure C505L V DD V SS C505L Oscillator Watchdog XRAM 256 x 8 RAM 256 x 8 OTP 32k x 8 XTAL1 OSC & Timing XTAL2 CPU 8 Datapointers Port 0 8-Bit Digit. I / O Port 1 8-Bit Digit. I / O / 8-Bit Analog In Port 2 8-Bit Digit. I / O Port 3 8-Bit Digit. I / O / 2 LCD Outputs Port 4 8-Bit Digit. I / O / 8 LCD Outputs Port 5 6-Bit Digit. I / O / 6 LCD Outputs RESET ALE PSEN EA Port 0 Programmable Watchdog Timer Timer 0 Timer 1 Timer 2 Port 1 Port 2 Port 3 Port 4 USART Baudrate Generator Port 5 XTAL3 XTAL4 Real-Time Clock 128-Segment LCD Controller 20 LCD Outputs Interrupt Unit V AREF V AGND A / D Converter 10-Bit Emulation Support Logic MCB03835 S&H MUX Figure 2-1 Block Diagram of the C505L User’s Manual 2-2 10.99 Fundamental Structure C505L 2.1 CPU The C505L is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 16-MHz external clock, 58% of the instructions execute in 375 ns (20 MHz: 300 ns). The CPU of the C505L consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU which have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the Arithmetic/Logic unit (ALU), an A register, B register and a Program Status Word (PSW) register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, subtract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit Program Counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. The C505L, additionally, contains 8 datapointers compared to a standard 8051 microcontroller which has only one. For complex applications with peripherals (e.g. LCD controller) located in the external data memory space or extended data storage capacity this turned out to be a “bottle neck” for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. Accumulator ACC is the acronym for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The PSW register contains several status bits that reflect the current state of the CPU. User’s Manual 2-3 10.99 Fundamental Structure C505L Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 LSB D0H P Reset Value: 00H PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instructions. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instructions. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of “one” bits in the accumulator, i.e. even parity. B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The Stack Pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the SP is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. User’s Manual 2-4 10.99 Fundamental Structure C505L 2.2 CPU Timing The C505L has no clock prescaler. Therefore, a machine cycle of the C505L consists of 6 states (6 oscillator periods). Each state is divided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 6 oscillator periods, numbered S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts one oscillator period. Typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in Figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL1 oscillator signals and the ALE (Address Latch Enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Execution of a one-cycle instruction begins at S1P2, when the opcode is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next opcode) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and a 2-byte, 1-cycle instruction. Most C505L instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a 1-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-2 (c) and (d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction. User’s Manual 2-5 10.99 Fundamental Structure C505L S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 OSC (XTAL2) ALE Read Opcode S1 S2 S3 S4 Read Next Opcode (Discard) S5 S6 Read Next Opcode Again (a) 1-Byte, 1-Cycle Instruction, e. g. INC A Read Opcode S1 S2 S3 S4 Read 2nd Byte S5 S6 Read Next Opcode (b) 2-Byte, 1-Cycle Instruction, e. g. ADD A #DATA Read Opcode S1 S2 S3 S4 Read Next Opcode (Discard) Read Next Opcode Again S4 S5 S6 S5 S6 S1 S2 S3 (c) 1-Byte, 2-Cycle Instruction, e. g. INC DPTR Read Opcode (MOVX) S1 S2 S3 S4 Read Next Opcode (Discard) S5 ADDR S6 S1 Read Next Opcode Again No Fetch No Fetch No ALE S2 DATA MCD03287 S3 S4 S5 S6 (d) MOVX (1-Byte, 2-Cycle) Access of External Memory Figure 2-2 Fetch Execute Sequence User’s Manual 2-6 10.99 Memory Organization C505L 3 Memory Organization The C505L CPU manipulates operands in the following address spaces: – – – – – – – up to 64 Kbytes of program memory (32K on-chip OTP memory) up to 64 Kbytes of external data memory 256 bytes of internal data memory 256 bytes of internal XRAM data memory 20 bytes of LCD Controller registers 16 bytes of Real-Time Clock (RTC) registers A 128-byte Special Function Register (SFR) area Figure 3-1 illustrates the memory address spaces of the C505L. Alternatively FFFF H Internal XRAM (256 Byte) Not used Internal LCD & RTC (36 Byte) F3DB H 8000 H 7FFF H External Data Memory Indirect Address FF H Internal RAM 80 H 7F H Internal RAM 0000 H "Code Space" "Data Space" 0000 H 00 H "Internal Data Space" MCD03996 FFFF H External Data Memory External FF00 H F3FF H F3DC H Direct Address FF H Special Function Register 80 H Internal (EA = 1) Figure 3-1 C505L Memory Map User’s Manual 3-1 10.99 Memory Organization C505L 3.1 Program Memory, “Code Space” The C505L has 32 Kbytes of on-chip OTP memory which can be externally expanded up to 64 Kbytes. The C505L executes program code out of the internal OTP memory until the program counter address exceeds 7FFFH. Address locations 8000H through FFFFH are then fetched from the external program memory. The EA pin is always held high. It is recommended to not set the EA pin at low level as this may cause the device to function in a manner that is not defined. 3.2 Data Memory, “Data Space” The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks: The lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128-byte SFR area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit general-purpose registers, occupy locations 0 through 1F H in the lower RAM area. The next 16 bytes, locations 20H t hrough 2F H, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal RAM area, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbytes, and can be accessed by instructions that use a 16-bit or an 8-bit address. The internal LCD controller, the RTC, both peripherals, and the internal XRAM are located in the external memory address area at addresses F3DCH to F3EFH, F3F0H to F3FFH and FF00H to FFFFH respectively. The LCD controller registers, the RTC registers and internal XRAM can therefore be accessed using MOVX instructions with addresses pointing to the respective address areas. 3.3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks of eight General Purpose Registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the Program Status Word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in C hapter 2 ). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The eight general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction opcode indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM that is not used for data storage. User’s Manual 3-2 10.99 Memory Organization C505L 3.4 XRAM Operation The XRAM in the C505L is a memory area that is logically located at the upper end of the external data memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory, the same instruction types (MOVX), must be used for accessing the XRAM. 3.4.1 XRAM/LCD Controller/RTC Access Control Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to XRAM, the LCD Controller and the RTC. XMAP0 is a general access enable/disable control bit, and XMAP1 controls the external signal generation during XRAM/LCD controller/RTC accesses. Special Function Register SYSCON (Address B1H) Bit No. B1H MSB 7 _ Reset Value: XX10XX01B LSB 0 6 _ 5 EALE 4 RMAP 3 _ 2 _ 1 XMAP1 XMAP0 SYSCON The shaded bits are not described in this section. Bit XMAP1 Function XRAM/LCD Controller/RTC visible access control Control bit for RD/WR signals during XRAM/LCD Controller/RTC accesses. If addresses are outside the XRAM/LCD Controller/RTC address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0: The signals RD and WR are not activated during accesses to the XRAM/LCD Controller/RTC. XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated during accesses to XRAM/LCD Controller/RTC. In this mode, address and data information during XRAM/LCD Controller/RTC accesses are visible externally. Global XRAM/LCD Controller/RTC access enable/disable control XMAP0 = 0: The access to XRAM, LCD Controller and RTC are enabled. XMAP0 = 1: The access to XRAM, LCD Controller and RTC are disabled (default after reset!). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected. Reserved bits for future use. Read by CPU returns undefined values. XMAP0 – When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM, LCD Controller and RTC RD and WR become active and port 0 and 2 drive the actual address/data information which is read/ written from/to XRAM/LCD Controller/RTC. This feature allows to check the internal data transfers to XRAM, LCD Controller and the RTC. When port 0 and 2 are used for I/O purposes, the XMAP1 bit should not be set. Otherwise the I/O function of the port 0 and port 2 lines is interrupted. User’s Manual 3-3 10.99 Memory Organization C505L After a reset operation, bit XMAP0 is set. This means that accesses to LCD Controller, RTC and the internal XRAM are generally disabled. In this case, all accesses using MOVX instructions within the address range of F3DCH to F3EFH, F3F0H to F3FFH and FF00H to FFFFH generate external data memory bus cycles. When XMAP0 is cleared, accesses to LCD Controller, the RTC and the internal XRAM are enabled and all accesses using MOVX instructions with an address in the range as above will access the LCD Controller, RTC and the internal XRAM respectively. Internal accesses (XMAP0 = 0) in the address range gap from F400H to FEFFH (as shown in Figure 3-1) will have undefined data. Bit XMAP0 is hardware-protected. If it is cleared once, it cannot be set by software. Only a reset operation will set the XMAP0 bit again. This hardware protection mechanism is done by an asymmetric latch at XMAP0 bit. An unintentional disabling of LCD Controller, the RTC and the internal XRAM could be dangerous since indeterminate values could be read from the external bus. To avoid this the XMAP0 bit is forced to ‘1’ only by a reset operation. Additionally, an internal capacitor is charged during reset. Therefore, the reset state is a disabled LCD Controller, disabled RTC and disabled internal XRAM. Because of the charge time of the capacitor, once the XMAP0 bit is written to ‘0’ (that is, discharging the capacitor) the bit cannot be set to ‘1’ again by software. On the other hand any distortion (software hang-up, noise, …) is not able to charge this capacitor, either. That is, the stable status is with the LCD Controller, the RTC and internal XRAM are enabled. The “clear” instruction for the XMAP0 bit should be integrated in the program initialization routine before XRAM/LCD Controller/RTC is used. In extremely noisy systems the user may have redundant “clear” instructions. User’s Manual 3-4 10.99 Memory Organization C505L 3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode) The XRAM, LCD Controller and RTC can be accessed by two read/write instructions that use the 16-bit DPTR for indirect addressing. These instructions are: – MOVX – MOVX A, @DPTR @DPTR, A (Read) (Write) For accessing the XRAM, the effective address stored in DPTR must be in the range of FF00H to FFFFH. For accessing the LCD Controller, the effective address stored in DPTR must be in the range of F3DCH to F3EFH. For accessing the RTC, the effective address stored in DPTR must be in the range of F3F0H to F3FFH. 3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode) The 8051 architecture also provides instructions for accesses to external data memory range that use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are: MOVX MOVX A, @Ri @Ri, A (Read) (Write) A special page register is implemented in the C505L to make it possible to access the XRAM/LCD Controller/RTC also with the MOVX @Ri instructions. XPAGE serves the same function for the XRAM, LCD Controller and RTC as Port 2 for external data memory. Special Function Register XPAGE (Address 91H) Bit No. MSB 7 91H .7 LSB 0 .0 Reset Value: 00H 6 .6 5 .5 4 .4 3 .3 2 .2 1 .1 XPAGE Bit XPAGE.7-0 Function XRAM/LCD Controller/RTC high address XPAGE.7-0 is the address part A15-A8 when 8-bit MOVX instructions are used to access internal XRAM/LCD Controller/RTC. Figures 3-2 to 3-4 show the dependencies of XPAGE- and Port 2 - addressing in order to explain the differences in accessing XRAM/LCD Controller/RTC, external RAM and to show what to do when Port 2 is used as an I/O-port. User’s Manual 3-5 10.99 Memory Organization C505L Port 0 XRAM/ LCD Controller/ Real-Time Clock Address/Data XPAGE Write to Port 2 Port 2 Page Address MCS03837 Figure 3-2 Write Page Address to Port 2 “MOV P2, pageaddress” will write the page address to port 2 and the XPAGE-Register. When external RAM is to be accessed in the XRAM/LCD Controller/RTC address range, these modules should remain disabled after reset. When additional external RAM is to be addressed in an address range < F3DCH, the XRAM/LCD Controller/RTC may remain enabled and there is no need to overwrite XPAGE by a second move. User’s Manual 3-6 10.99 Memory Organization C505L Port 0 XRAM/ LCD Controller/ Real-Time Clock Address/Data XPAGE Write to XPAGE Port 2 Address/ I/O-Data MCS03838 Figure 3-3 Write Page Address to XPAGE “MOV XPAGE, pageaddress” will write the page address only to the XPAGE register. Port 2 is available for addresses or I/O data. User’s Manual 3-7 10.99 Memory Organization C505L Port 0 XRAM/ LCD Controller/ Real-Time Clock Address/Data XPAGE Write I/O Data to Port 2 Port 2 I/O-Data MCS03839 Figure 3-4 Use of Port 2 as I/O Port On a write to port 2, the XRAM/LCD Controller/RTC address in XPAGE register will be overwritten because of the concurrent write to port 2 and XPAGE register. Therefore, whenever XRAM is used and the XRAM address differs from the byte written to port 2 latch it is absolutely necessary to rewrite XPAGE with the page address. Example: I/O data at port 2 shall be AAH. A byte shall be fetched from XRAM at address FF30H. MOV MOV MOV MOVX R0, #30H P2, #0AAH XPAGE, #0FFH A, @R0 ; ; P2 shows AAH and XPAGE contains AAH ; P2 still shows AAH but XRAM is addressed ; the contents of XRAM at FF30H is moved to accumulator User’s Manual 3-8 10.99 Memory Organization C505L The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed by XPAGE and Ri points outside the XRAM/LCD Controller/RTC address range, an external access is performed. For the C505L the content of XPAGE must be F7H - FFH in order to use the XRAM/LCD Controller/RTC. The software has to distinguish two cases, if the MOVX @Ri instructions with paging shall be used: a) Access to XRAM/LCD Contr./RTC: The upper address byte must be written to XPAGE or P2; both writes select the XRAM/LCD Controller/RTC address range. b) Access to external memory: The upper address byte must be written to P2; XPAGE will be automatically loaded with the same address in order to deselect the XRAM. 3.4.4 Reset Operation of the XRAM The contents of the XRAM are not affected by a reset. After power-up the contents are undefined, although they remain unchanged during and after a reset as long as the power supply is not turned off. If a reset occurs during a write operation to XRAM, the content of a XRAM memory location depends on the cycle in which the active reset signal is detected (MOVX is a 2-cycle instruction): Reset during 1st cycle: The new value will not be written to XRAM. The old value is not affected. Reset during 2nd cycle: The old value in XRAM is overwritten by the new value. 3.4.5 Behavior of Port 0 and Port 2 The behavior of port 0 and port 2 during a MOVX access depends on the control bits in register SYSCON. Table 3-1 lists the various operating conditions. It shows the following characteristics: a) Use of P0 and P2 pins during the MOVX access. Bus: The pins work as external address/data bus. If (internal) XRAM/LCD Controller/RTC are accessed, the data written to the XRAM/LCD Controller/RTC can be seen on the bus in debug mode. I/0: The pins work as Input/Output lines under control of their latch. b) Activation of the RD and WR pin during the access. c) Use of internal (XRAM/LCD Controller/RTC) or external XDATA memory. The shaded areas in the table describe how each C5xx device without on-chip XRAM/LCD Controller/RTC behaves. For simplicity, the references in this table to the on-chip XRAM also cover the LCD Controller and the RTC accesses. User’s Manual 3-9 10.99 Memory Organization C505L Table 3-2 Behavior of P0/P2 and RD/WR During MOVX Accesses XMAP1, XMAP0 00 MOVX @DPTR DPTR < XRAM address range DPTR ≥ XRAM address range MOVX @Ri XPAGE < XRAM addr. page range XPAGE ≥ XRAM addr.page range a) P0/P2→Bus b) RD/WR active c) ext. memory is used a) P0/P2→Ι/Ο b) RD/WR inactive c) XRAM is used 10 a) P0/P2→Bus b) RD/WR active c) ext. memory is used a) P0/P2→Bus (RD/WR-Data) b) RD/WR active c) XRAM is used a) P0→Bus P2→I/O b) RD/WR active c) ext. memory is used a) P0/P2→I/O a) P0→Bus P2→I/O b) RD/WR active c) ext. memory is used a) P0→Bus (RD/WR-Data) P2→I/O b) RD/WR active c) XRAM is used X1 a) P0/P2→Bus b) RD/WR active c) ext. memory is used a) P0/P2→Bus b) RD/WR active c) ext. memory is used a) P0→Bus P2→I/O b) RD/WR active c) ext. memory is used a) P0→Bus P2→I/O b) RD/WR active c) ext. memory is used b) RD/WR inactive c) XRAM is used modes compatible to 8051/C501 family. User’s Manual 3-10 10.99 Memory Organization C505L 3.5 Special Function Registers All registers, except for the program counter and the four GPR banks reside in the SFR area. The SFR area consists of two portions: the standard SFR area and the mapped SFR area. Some of the C505L’s SFRs (PCON1, VR0, VR1 and VR2) are located in the mapped SFR area. For accessing the mapped SFR area, bit RMAP in SFR SYSCON must be set. All other SFRs are located in the standard SFR area which is accessed when RMAP is cleared (“0”). The registers and data locations of the LCD Controller (LCD-SFRs) and the RTC (RTC-SFRs) are located in the external data memory area at addresses F3DDH to F3EFH and F3F0H to F3FFH respectively. Details about the access of these registers is described in Section 3.4.1 of this chapter. Special Function Register SYSCON (Address B1H) Bit No. B1H MSB 7 _ Reset Value: XX100X01B LSB 0 6 _ 5 EALE 4 RMAP 3 _ 2 _ 1 XMAP1 XMAP0 SYSCON The shaded bits are not described in this section. Bit RMAP Function SFR map bit RMAP = 0: Access to the non-mapped (standard) SFR area is enabled. RMAP = 1: Access to the mapped SFR area is enabled. Reserved bits for future use. Read by CPU returns undefined values. – As long as bit RMAP is set, mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, …, F8H, FFH) are bit-addressable. The 51 SFRs in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C505L are listed in Table 3-3 and Table 3-4. In Table 3-3 they are organized in groups which refer to the functional blocks of the C505L. The LCD and RTC-SFRs are also included in Table 3-3. Table 3-4 illustrates the contents of the SFRs in numeric order of their addresses. Table 3-5 lists the LCD and the RTC-SFRs in numeric order of their addresses. User’s Manual 3-11 10.99 Memory Organization C505L Table 3-3 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL DPSEL PSW SP SYSCON2) VR04) VR14) VR24) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 1 Version Register 2 A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte Port 1 Analog Input Selection Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register Address E0H1) F0H1) 83H 82H 92H D0H1) 81H B1H FCH FDH FEH D8H1) DCH D9H DAH 90H4) A8H1) B8H1) A9H B9H 88H1) C8H1) 98H1) C0H1) Contents after Reset 00H 00H 00H 00H XXXXX000B3) 00H 07H XX10XX01B3) C5H 85H 5) A/DADCON02) Converter ADCON1 ADDATH ADDATL P1ANA2) Interrupt System IEN02) IEN12) IP02) IP1 TCON2) T2CON2) SCON2) IRCON XPAGE SYSCON2) Ports P0 P1 P1ANA2) P2 P3 P4 P5 00X00000B3) 01XXX000B3) 00H 00XXXXXXB3) FFH 00H 00H 00H XX000000B3) 00H 00X00000B 00H 00H 00H XX10XX01B3) FFH FFH FFH FFH FFH 00B XX111111B XRAM Page Address Register for Extended on-chip 91H XRAM, LCD Controller and RTC B1H System Control Register Port 0 Port 1 Port 1 Analog Input Selection Register Port 2 Port 3 Port 4 Port 5 80H1) 90H1) 90H1) 4) A0H1) B0H1) E8H1) F8H1) 1) Bit-addressable SFRs 2) This SFR is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved. 4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The content of this SFR varies with the actual step of the C505L (e.g. 01H for the first step). User’s Manual 3-12 10.99 Memory Organization C505L Table 3-3 Special Function Registers - Functional Blocks (cont’d) Block Serial Channel Symbol ADCON0 2) PCON 2) SBUF SCON SRELL SRELH TCON TH0 TH1 TL0 TL1 TMOD CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON IEN02) IEN12) Name A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Reload Register High Byte Reload Register Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Power Control Register Power Control Register 1 Address D8H1) 87H 99H 98H1) AAH BAH 88H1) 8CH 8DH 8AH 8BH 89H C1H C3H C5H C7H C2H C4H C6H CBH CAH CDH CCH C8H1) A8H1) B8H1) 86H A8H1) B8H1) A9H 87H 88H1) Contents after Reset 00X00000B3) 00H XXH3) 00H D9H XXXXXX11B3) 00H 00H 00H 00H 00H 00H 00H3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00X00000B3) 00H 00H 00H 00H 00H 00H 00H 0XX0XXXXB3) Timer 0/ Timer 1 Compare/ Capture Unit / Timer 2 Watchdog WDTREL IEN02) IEN12) IP02) Power Save Modes PCON 2) PCON14) 1) Bit-addressable SFRs 2) This SFR is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. User’s Manual 3-13 10.99 Memory Organization C505L Table 3-3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name D/A Conversion Register LCD Control Register LCD Timer Reload Low Register LCD Timer Reload High Register LCD Digit Register ‘n’ 5) Real-Time Clock Control Register Real-Time Clock Initialization Register 0 Real-Time Clock Initialization Register 1 Real-Time Clock Initialization Register 2 Real-Time Clock Initialization Register 3 Real-Time Clock Initialization Register 4 Clock Count Register 0 Clock Count Register 1 Clock Count Register 2 Clock Count Register 3 Clock Count Register 4 Real-Time Clock Interrupt Register 0 Real-Time Clock Interrupt Register 1 Real-Time Clock Interrupt Register 2 Real-Time Clock Interrupt Register 3 Real-Time Clock Interrupt Register 4 Address F3DCH F3DDH F3DEH F3DFH F3EnH F3F0H F3F1H F3F2H F3F3H F3F4H F3F5H F3F6H F3F7H F3F8H F3F9H F3FAH F3FBH F3FCH F3FDH F3FEH F3FFH Contents after Reset 00H 00H 00H 00H 00H5) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H LCD DAC06) Controller LCON6) LCRL6) LCRH6) DIGn5), 6) Real-Time RTCON6) RTCR06) Clock RTCR16) RTCR26) RTCR36) RTCR46) CLREG06) CLREG16) CLREG26) CLREG36) CLREG46) RTINT06) RTINT16) RTINT26) RTINT36) RTINT46) 1) Bit-addressable SFRs 2) This SFR is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved. 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The notation “n” (n = 0 to F) in the LCD Digit Register address definition defines the number of the related LCD digit. 6) This register is located in the on-chip external data memory area. User’s Manual 3-14 10.99 Memory Organization C505L Table 3-4 Contents of the SFRs, SFRs in Numeric Order of Their Addresses Addr Register Content Bit 7 after Reset1) P0 SP DPL DPH FFH 07H 00H 00H .7 .7 .7 .7 WDT PSEL TF1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H2) 81H 82H 83H 86H 87H 88H2) 88H3) 89H 8AH 8BH 8CH 8DH 90H2) 90H3) 91H 92H 98H2) 99H A0H2) A8H2) A9H AAH .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 IDLS TF0 – M1 .5 .5 .5 .5 .4 .4 .4 .4 .4 SD TR0 WS M0 .4 .4 .4 .4 .4 EAN4 .4 – REN .4 .4 ES .4 .4 .3 .3 .3 .3 .3 GF1 IE1 – GATE .3 .3 .3 .3 .3 EAN3 .3 – TB8 .3 .3 ET1 .3 .3 .2 .2 .2 .2 .2 GF0 IT1 – C/T .2 .2 .2 .2 INT5 EAN2 .2 .2 RB8 .2 .2 EX1 .2 .2 .1 .1 .1 .1 .1 PDE IE0 – M1 .1 .1 .1 .1 INT4 EAN1 .1 .1 TI .1 .1 ET0 .1 .1 .0 .0 .0 .0 .0 IDLE IT0 – M0 .0 .0 .0 .0 .0 EAN0 .0 .0 RI .0 .0 EX0 .0 .0 WDTREL 00H PCON TCON PCON1 TMOD TL0 TL1 TH0 TH1 P1 P1ANA XPAGE DPSEL SCON SBUF P2 IEN0 IP0 SRELL 00H 00H SMOD PDS TR1 0XX0-X EWPD – XXXB 00H 00H 00H 00H 00H FFH FFH 00H GATE .7 .7 .7 .7 T2 EAN7 .7 C/T .6 .6 .6 .6 CLK-O T2EX UT EAN6 .6 – SM1 .6 .6 WDT .6 EAN5 .5 – SM2 .5 .5 ET2 .5 XXXX-X – 000B 00H XXH FFH 00H 00H D9H SM0 .7 .7 EA .7 OWDS WDTS .5 1) “X” means that the value is undefined and the location is reserved 2) Bit-addressable SFRs 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. User’s Manual 3-15 10.99 Memory Organization C505L Table 3-4 Contents of the SFRs, SFRs in Numeric Order of Their Addresses (cont’d) Addr Register Content Bit 7 after Reset1) P3 FFH RD SYSCON XX10-X – X01B IEN1 IP1 SRELH IRCON CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 T2CON CRCL CRCH TL2 TH2 PSW 00H XX00-00 – 00B XXXX-X – X11B 00H 00H 00H 00H 00H 00H 00H 00H EXF2 COCA H3 .7 .7 .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B0H2) B1H B8H2) B9H BAH C0H2) C1H C2H C3H C4H C5H C6H C7H C8H2) CAH CBH CCH CDH D0H2) D8H2) D9H DAH WR – T1 EALE T0 RMAP EX5 .4 – IEX5 INT1 – EX4 .3 – IEX4 INT0 – EX3 .2 – IEX3 TxD RxD XMAP1 XMAP0 ESWI .1 .1 SWI EADC .0 .0 IADC COCAL 0 .0 .0 .0 .0 .0 .0 T2I0 .0 .0 .0 .0 P MX0 .2 – EXEN2 SWDT EX6 – – TF2 .5 – IEX6 COCAL COCA COCAL COCA COCAL COCA 3 H2 2 H1 1 H0 .6 .6 .6 .6 .6 .6 I3FR .6 .6 .6 .6 AC CLK .8 .0 .5 .5 .5 .5 .5 .5 – .5 .5 .5 .5 F0 – .7 – .4 .4 .4 .4 .4 .4 T2R1 .4 .4 .4 .4 RS1 BSY .6 – .3 .3 .3 .3 .3 .3 T2R0 .3 .3 .3 .3 RS0 ADM .5 – .2 .2 .2 .2 .2 .2 T2CM .2 .2 .2 .2 OV MX2 .4 – .1 .1 .1 .1 .1 .1 T2I1 .1 .1 .1 .1 F1 MX1 .3 – 00X0-00 T2PS 00B 00H 00H 00H 00H 00H .7 .7 .7 .7 CY ADCON0 00X0-00 BD 00B ADDATH 00H .9 ADDATL 00XX-X .1 XXXB 1) “X” means that the value is undefined and the location is reserved 2) Bit-addressable SFRs User’s Manual 3-16 10.99 Memory Organization C505L Table 3-4 Contents of the SFRs, SFRs in Numeric Order of Their Addresses (cont’d) Addr Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DCH E0H2) E8H2) F0H2) F8H2) ADCON1 01XX-X ADCL1 ADCL0 – 000B ACC P4 B P5 00H 00H 00H .7 .7 .7 .6 .6 .6 – 1 0 .6 .5 .5 .5 .5 0 0 .5 – .4 .4 .4 .4 0 0 .4 – .3 .3 .3 .3 0 0 .3 MX2 .2 .2 .2 .2 1 1 .2 MX1 .1 .1 .1 .1 0 0 .1 MX0 .0 .0 .0 .0 1 1 .0 XX00-00 – 00H C5H 85H 5) FCH3)4) VR0 FDH3)4) VR1 FEH 3)4) 1 0 .7 VR2 1) “X” means that the value is undefined and the location is reserved. 2) Bit-addressable SFRs. 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers. 5) The content of this SFR varies with the actual of the step C505L (e.g. 01H for the first step). User’s Manual 3-17 10.99 Memory Organization C505L Table 3-5 Contents of the LCD and the RTC Registers in Numeric Order of Their Addresses Addr. Register Content Bit 7 after Reset 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H S7 DSB1 .7 SLT 0 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F3DCH F3DDH F3DEH F3DFH F3EnH F3F0H F3F1H F3F2H F3F3H F3F4H F3F5H F3F6H F3F7H F3F8H F3F9H F3FAH F3FBH F3FCH F3FDH F3FEH F3FFH DAC02) LCON2) LCRL2) LCRH2) DIGn1), 2) RTCON2) RTCR02) RTCR12) RTCR22) RTCR32) RTCR4 2) S6 DSB0 .6 .14 0 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 S5 0 .5 .13 0 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 S4 0 .4 .12 0 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 S3 0 .3 .11 S2 0 .2 .10 S1 CSEL .1 .9 ERTC .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 S0 LCEN .0 .8 RTCS .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 SEGF SEGA SEGG SEGB SEGE SEGC SEGH SEGD RTPD IRTC .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 CLREG02) 00H CLREG12) 00H CLREG22) 00H CLREG3 2) 00H 00H 00H 00H 00H 00H CLREG42) 00H RTINT02) RTINT12) RTINT2 2) RTINT32) RTINT42) 1) The notation “n” (n = 0 to F) in the LCD Digit Register address definition defines the number of the related LCD digit. 2) This register is located in the on-chip external data memory area. User’s Manual 3-18 10.99 External Bus Interface C505L 4 External Bus Interface The C505L allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture with one exception: If the C505L is used in systems with no external memory the generation of the ALE signal can be suppressed. Resetting bit EALE in SFR SYSCON register, the ALE signal will be gated off. This feature reduces RFI emissions of the system. 4.1 Accessing External Memory It is possible to distinguish between accesses to external program memory, external data memory or to other peripheral components respectively. This distinction is made by hardware: Accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). 4.1.1 Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FFH to the port 0 latch (the Special Function Register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the SFR). Thus the port 2 latch does not have to contain 1 s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods. User’s Manual 4-1 10.99 External Bus Interface C505L a) S1 ALE One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN RD PCH OUT INST IN PCL OUT PCL OUT valid b) S1 ALE PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN (A) without MOVX P2 P0 One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN (B) with MOVX PCH OUT INST IN PCL OUT PCL OUT valid PCH OUT INST IN DPL or Ri valid DPH OUT OR P2 OUT DATA IN PCL OUT PCL OUT valid PCH OUT INST IN RD P2 P0 MCD02575 Figure 4-1 External Program Memory Execution User’s Manual 4-2 10.99 External Bus Interface C505L 4.1.2 Timing The timing of the external bus interface and the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2 are illustrated in Figures 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. 4.1.3 External Program Memory Access The external program memory is accessed whenever the program counter (PC) content is greater than 7FFFH, provided the EA pin is held at high level at reset. When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and must not be used for general-purpose I/O. The content of the port 2 SFR, however, is not affected. During external program memory fetches, port 2 lines output the high byte of the PC; during accesses to external data memory, they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). 4.2 PSEN, Program Store Enable The read strobe for external program memory fetches is PSEN. It is not activated for internal program memory fetches. When the CPU is accessing external program memory, PSEN is activated twice every instruction cycle (except during a MOVX instruction) whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN, takes 3 oscillator periods. The execution sequence for these two types of read cycles is shown in Figures 4-1 a) and b). 4.3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C505L, the external program and data memory spaces can be combined by the logical-AND of PSEN and RD. A positive result from this AND operation produces a low-active read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle. User’s Manual 4-3 10.99 External Bus Interface C505L 4.4 ALE, Address Latch Enable The C505L allows to switch off the ALE output signal. If the internal OTP is used (EA = 1 and PC ≤ 7FFFH) and ALE is switched off by EALE = 0, then, ALE will only go active during external data memory accesses (MOVX instructions). After a hardware reset, ALE generation is enabled. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – Reset Value: XX10XX01B LSB 0 SYSCON 6 – 5 EALE 4 RMAP 3 – 2 – 1 XMAP1 XMAP0 The shaded bits are not described in this section. Bit EALE Function Enable ALE output EALE = 0: ALE generation is disabled; disables ALE signal generation during internal code memory accesses; ALE is automatically generated during MOVX instructions EALE = 1: ALE generation is enabled (default after reset) Reserved bits for future use. Read by CPU returns undefined values. – User’s Manual 4-4 10.99 External Bus Interface C505L 4.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs, and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM-based programs is possible, too. Each C500 production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation, ensuring that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500, allows the C500 together with an EH-IC to function in a similar way as a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover, and ROMless modes of operation. It is also able to operate in single-step mode, and to read the SFRs after a break. ICE-System Interface to Emulation Hardware SYSCON PCON TCON RESET EA ALE PSEN RSYSCON RPCON RTCON EH-IC C500 MCU Optional I/O Ports Port 0 Port 2 Enhanced Hooks Interface Circuit Port 3 Port 1 RPort 2 RPort 0 TEA TALE TPSEN Target System Interface MCS02647 Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500-based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation; and to transfer information about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1) “Enhanced Hooks Technology” is a trademark and patent of MetaLink Corporation licensed to Infineon Technologies. User’s Manual 4-5 10.99 External Bus Interface C505L 4.6 Eight Datapointers for Faster External Bus Access 4.6.1 The Importance of Additional Datapointers The standard 8051 architecture provides just one 16-bit pointer for indirect addressing of external devices (memories, peripherals, latches, etc.). Except for a 16-bit “ move immediate ” to this datapointer and an increment instruction, any other pointer handling is bytewise. For complex applications with peripherals (e.g. LCD Controller or Real-Time Clock) located in the external data memory space, or extended data storage capacity, bytewise pointer handling turned out to be a “bottle neck” for the 8051’s communication to the external world. In particular, programming in highlevel languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. 4.6.2 How the eight Datapointers of the C505L are Implemented Simply adding more datapointers is not suitable because of the need to keep up 100% compatibility with the 8051 instruction set. That instruction set allows the handling of only one single 16-bit datapointer (DPTR, consisting of the two 8-bit SFRs DPH and DPL). To meet both of the above requirements (speed up external accesses, 100% compatibility with 8051 architecture), the C505L contains a set of eight 16-bit registers from which the actual datapointer can be selected. This means that the user’s program may keep up to eight 16-bit addresses resident in these registers, but only one register at a time is selected to be the datapointer. Thus the desired datapointer in turn is accessed (or selected) via indirect addressing. This indirect addressing is done through a special function register called DPSEL (data pointer select register). All instructions of the C505L that handle the datapointer therefore affect only pointer addressed by DPSEL at that very moment, rather than the other 7 pointers. Figure 4-3 illustrates the addressing mechanism: A 3-bit field in register DPSEL points to the currently used DPTRx. Any standard 8051 instruction (e.g. MOVX @DPTR, A - transfer a byte from accumulator to an external location addressed by DPTR) now uses this activated DPTRx. Special Function Register DPSEL (Address 92H) Bit No. MSB 7 92H – Reset Value: XXXXX000B LSB 0 .0 DPSEL 6 – 5 – 4 – 3 – 2 .2 1 .1 Bit DPSEL.2-0 Function Data pointer select bits DPSEL.2-0 defines the number of the actual active data pointer.DPTR0-7. User’s Manual 4-6 10.99 External Bus Interface C505L ----DPSEL(92 H) DPSEL .2 0 0 0 0 1 1 1 1 .1 0 0 1 1 0 0 1 1 .0 0 1 0 1 0 1 0 1 .2 .1 .0 DPTR7 Selected Datapointer DPTR 0 DPTR 1 DPTR 2 DPTR 3 DPTR 4 DPTR 5 DPTR 6 DPTR 7 External Data Memory MCD00779 DPTR0 DPH(83 H ) DPL(82 H) Figure 4-3 Accessing of External Data Memory via Multiple Datapointers 4.6.3 Advantages of Multiple Datapointers Using the addressing mechanism described above for external data memory results in less code and faster execution of external accesses. Whenever the contents of the datapointer must be altered between two or more 16-bit addresses, one instruction that selects a new datapointer does this job. lf the program uses just one datapointer, then it has to save the old value (with two 8-bit instructions) and load the new address, byte-by-byte. This takes more time and requires additional space in the internal RAM. 4.6.4 Application Example and Performance Analysis The following example demonstrates the use of multiple data pointers in a table transfer from the code memory to external data memory. Start address of ROM source table: Start address of table in external RAM: 1FFFH 2FA0H User’s Manual 4-7 10.99 External Bus Interface C505L Example 1: Using Only One Datapointer (Code for a C501) Initialization Routine MOV MOV MOV MOV LOW(SRC_PTR), #0FFH; HIGH(SRC_PTR), #1FH LOW(DES_PTR), #0A0H; HIGH(DES_PTR), #2FH Initialize shadow_variables with source_pointer Initialize shadow_variables with destination_pointer Table Look-up Routine under Real Time Conditions PUSH PUSH MOV MOV ;INC ;CJNE MOVC MOV MOV MOV MOV INC MOVX MOV MOV POP POP ; DPL DPH DPL, LOW(SRC_PTR) DPH, HIGH(SRC_PTR) DPTR … A,@DPTR LOW(SRC_PTR), DPL HIGH(SRC_PTR), DPH DPL, LOW(DES_PTR) DPH, HIGH(DES_PTR) DPTR @DPTR, A LOW(DES_PTR), DPL HIGH(DES_PTR),DPH DPH DPL ; Number of cycles ;Save old datapointer 2 ; 2 ;Load Source Pointer 2 ; 2 Increment and check for end of table (execution time not relevant for this consideration) – ;Fetch source data byte from ROM table 2 ;Save source_pointer and 2 ;load destination_pointer 2 ; 2 ; 2 ;Increment destination_pointer ;(ex. time not relevant) – ;Transfer byte to destination address 2 ;Save destination_pointer 2 ; 2 ;Restore old datapointer 2 ; 2 Total execution time (machine cycles): 28 User’s Manual 4-8 10.99 External Bus Interface C505L Example 2: Using Two Datapointers (Code for a C505L) Initialization Routine MOV MOV MOV MOV DPSEL, #06H DPTR, #1FFFH DPSEL, #07H DPTR, #2FA0H ;Initialize DPTR6 with source pointer ;Initialize DPTR7 with destination pointer Table Look-up Routine under Real-time Conditions PUSH MOV ;INC ;CJNE MOVC MOV MOVX POP DPSEL DPSEL, #06H DPTR … A,@DPTR DPSEL, #07H @DPTR, A DPSEL ; Number of cycles ;Save old source pointer 2 ;Load source pointer 2 Increment and check for end of table (execution time not relevant for this consideration) – ;Fetch source data byte from ROM table 2 ;Save source_pointer and ;load destination_pointer 2 ;Transfer byte to destination address 2 ;Save destination pointer and ;restore old datapointer 2 Total execution time (machine cycles): 12 ; The example above shows that utilization of the C505L’s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative. Here, four data variables in the internal RAM and two additional stack bytes were spared, too. For some applications where all eight datapointers are employed, a C505L program has up to 24 byte (16 variables and 8 stack bytes) of the internal RAM free for other use. User’s Manual 4-9 10.99 System Reset C505L 5 5.1 System Reset Hardware Reset Operation The hardware reset function incorporated in the C505L allows for an easy automatic start-up with a minimum of additional hardware, and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is commonly done when the power-down mode is to be terminated. In addition to the hardware reset, which is applied externally to the C505L, there are two internal reset sources: The watchdog timer, and the oscillator watchdog. This chapter deals only with the external hardware reset. The reset input is an active-high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. With the oscillator running, the internal reset is executed during the second machine cycle, and is repeated every cycle until RESET goes low again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. An external stimulation at these lines during reset activates several test modes that are reserved for test purposes. This may, in turn, cause unpredictable output operations at several port pins. At the reset pin, a pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. When VDD is applied, an automatic power-up reset can be caused by connecting the reset pin to VDD via a capacitor. After VDD has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time in order to effect a complete reset. User’s Manual 5-1 10.99 System Reset C505L The time required for a power-up reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is generated externally (Figure 5-1 b ). In each case it must be assured that the oscillator has started up properly and, after that, at least two machine cycles have passed before the reset signal goes inactive. VDD + a) C505L RESET & b) C505L RESET VDD c) C505L RESET + MCS03840 Figure 5-1 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is accomplished internally, the port latches of ports 0 to 4 default in FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/ O port lines (ports 1, 3 and 4) output a one (1). Port 2 lines output a one after reset. The internal SFRs are set to their initial states as defined in Table 3-2. The contents of the internal RAM and XRAM of the C505L are not affected by a reset. After power-up the contents are undefined, and they remain unchanged during a reset if the power supply is not turned off. User’s Manual 5-2 10.99 System Reset C505L 5.2 Fast Internal Reset after Power-On The C505L uses the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 5-1 shows the power-on sequence under control of the oscillator watchdog. Normally, the devices of the 8051 family do not enter their default reset states before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. If a crystal is used, the start up time of the oscillator is relatively long (typ. 10 ms). During this time period, the pins are in an undefined state which could have severe effects, especially to actuators connected to port pins. In the C505L, the oscillator watchdog unit avoids this situation. In this case, after power-on the oscillator watchdog’s RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). If the watchdog circuitry detects a failure condition for the on-chip oscillator because the latter has not yet started (a failure is always recognized if the watchdog’s RC oscillator runs faster than the on-chip oscillator), the watchdog uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator’s output. This allows correct resetting of the part and brings also all ports to the defined state (see Figure 5-2). Under worst-case conditions (fast VDD rise time - e.g. 1 µs, measured from VDD = 4.25 V up to stable port condition), the delay between power-on and the correct port reset state is: – Typ.: – Max.: 18 µs 34 µs The RC oscillator will already run at a VDD below 4.25 V (lower specification limit). Therefore, at slower VDD rise times the delay time will be less than the two values given above. After the on-chip oscillator has finally started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for up to 768 cycles of the RC oscillator clock in order to allow the oscillation of the on-chip oscillator to stabilize (Figure 5-2, II). Subsequently, the clock is supplied by the on-chip oscillator, and the oscillator watchdog’s reset request is released (Figure 5-2, III). However, an externally applied reset still remains active (Figure 5-2, IV) and the device does not start program execution (Figure 5-2, V) until the external reset is also released. Although the oscillator watchdog provides a fast internal reset, it is also necessary to apply an external reset signal when powering up. The reasons are: – – Termination of Software Power-Down Mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence. When using a crystal or ceramic resonator for clock generation, the external reset signal must be held active at least until the on-chip oscillator has started and the internal watchdog reset phase is completed (after phase III in Figure 5-2). When an external clock generator is used, phase II is very short. Therefore, an external reset time of 1 ms is usually sufficient for most applications. Generally, for reset time generation at power-on, an external capacitor can be applied to the RESET pin. User’s Manual 5-3 10.99 User’s Manual RESET II III IV V Clock from RC-Oscillator; RESET at Ports Port remains in RESET because of active ext. RESET Signal Start of Program Execution MCD02627 Ports Undef. Figure 5-2 Power-On Reset of the C505L On-Chip Osc. RC Osc. 5-4 On-Chip Osc. starts; Final RESET Sequence by Osc.-WD; (max. 768 RC Clock Cycles) VDD RESET I Power On; undef.Ports typ. 18 µ s max. 34 µ s System Reset C505L 10.99 System Reset C505L 5.3 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized with the internal CPU timing. When the reset is found active (high level), the internal reset procedure is started. It takes two complete machine cycles to put the complete device into its correct reset state, i.e. all Special Function Registers (SFRs) containing their default values, the port latches containing ‘1’ s etc. Note that this reset procedure may also be performed by the oscillator watchdog if there is no clock available at the device. The oscillator watchdog provides an auxiliary clock at the XTAL1 and XTAL2 pins for performing a complete reset without another. The RESET signal must be active for at least one machine cycle; after this time the C505L remains in its reset state as long as the signal is active. When the signal goes inactive, this transition is recognized in the subsequent state 5 phase 2 of the machine cycle. Then the processor starts program execution in the subsequent state 5 phase 1. One phase later (state 5 phase 2), the first falling edge at pin ALE occurs. User’s Manual 5-5 10.99 System Reset C505L 5.4 Oscillator and Clock Circuit XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter that can be configured with off-chip components such as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states, and machine cycles. Figure 5-3 shows the recommended oscillator circuit. C XTAL1 2 - 20 MHz C XTAL2 C = 20 pF 10 pF for crystal operation MCS04291 C505L Figure 5-3 Recommended Oscillator Circuit In this application, the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator. A more detailed schematic is given in Figure 5-4. The oscillator is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit, 20 pF can be used as single capacitance at any frequency together with a good-quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors normally have different values depending on the oscillator frequency. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors. User’s Manual 5-6 10.99 System Reset C505L To internal timing circuitry XTAL2 *) XTAL1 C505L C1 C2 *) Crystal or ceramic resonator MCS04292 Figure 5-4 On-Chip Oscillator Circuitry To drive the C505L with an external clock source, the external clock signal has to be applied to XTAL1, as shown in Figure 5-5. XTAL2 has to be left unconnected. A pullup resistor is recommended to increase the noise margin, but is optional if VOH of the driving gate corresponds to the VIH1 specification of XTAL1 (refer to Data Sheet). C505L N.C. XTAL2 VDD External Clock Signal XTAL1 MCS04037 Figure 5-5 External Clock Source User’s Manual 5-7 10.99 System Reset C505L 5.5 System Clock Output For peripheral devices requiring a system clock, the C505L provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. If bit CLK is set (bit 6 of SFR ADCON0), a clock signal with 1/6 of the oscillator frequency is gated to pin P1.6/ CLKOUT. To use this function, the port pin must be programmed to a 1, which is also the default after reset. Special Function Register ADCON0 (Address D8H) Bit No. D8H MSB DFH BD DEH CLK DDH – DCH BSY DBH ADM DAH MX2 D9H MX1 Reset Value: 00X00000B LSB D8H MX0 ADCON0 The shaded bits are not used for clock output control. Bit CLK Function Clockout enable bit When set, pin P1.6/CLKOUT outputs the system clock which is 1/6 of the oscillator frequency. Reserved bits for future use. Read by CPU returns undefined values. – The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states. Thus, the duty cycle of the clock signal is 1:6. Associated with a MOVX instruction, the system clock coincides with the last state (S3) in which a RD or WR signal is active. A timing diagram of the system clock output is shown in Figure 5-6. Note: During slow-down operation, the frequency of the CLKOUT signal is divided by 32. User’s Manual 5-8 10.99 System Reset C505L S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 ALE PSEN RD,WR CLKOUT MCT01858 Figure 5-6 Timing Diagram - System Clock Output User’s Manual 5-9 10.99 On-Chip Peripheral Components C505L 6 On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the C505L except for the integrated interrupt controller, which is described separately in Chapter 7. 6.1 Parallel I/O The C505L has five 8-bit and one 6-bit (port 5) digital I/O ports. Port 0 is an open-drain bidirectional I/O port, while ports 1 through 5 are quasi-bidirectional I/O ports with internal pull-up resistors. When configured as inputs, ports 1-5 will be pulled high, and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 Special Function register (SFR) contents. In this function, port 0 is not an open-drain port, but uses a strong internal pull-up FET. The C505L has 36 output lines (4 rows and 32 columns) for LCD voltage output. Of these, 20 are dedicated output lines: R0-R3 and C0-C15. Fourteen LCD output lines are used as alternate functions of the bits of port 4 (C16-C23) and port 5 (C24-C29). Two LCD output lines C30 and C31 are used as alternate functions of P3.5 / T1 and P3.4 / T0 respectively. 6.1.1 Port Structures The C505L generally allows digital I/O on 46 lines, grouped into five 8-bit digital and one 6-bit digital I/O ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0-P5 are performed via their corresponding SFRs. Depending on the specific ports, multiple functions are assigned to the port pins. Therefore, the parallel I/O ports of the C505L can be grouped into six different types which are listed in Table 6-1. Table 6-1 C505L Port Structure Types Type A B C D E F Description Standard digital I/O ports which can also be used for external address/data bus Standard multifunctional digital I/O port lines Mixed digital/analog I/O port lines with programmable analog input function LCD Output Lines Standard digital I/O or LCD output lines Standard multifunctional digital I/O or LCD output lines Type A and B port pins are standard C501-compatible I/O port lines, which can be used for digital I/O. The type A ports (port 0 and port 2) are also designed for accessing external data or program memory. Type B port lines are located at port 3 (except P3.4 and P3.5), and are used for digital I/O or for other alternate functions as described in the pin description. Type D port lines provide the LCD controller outputs R0-R3 and C0-C15 as primary functions. Type E port lines are located at port 4 and port 5 and provide the LCD controller output lines as alternate functions. Type F port lines User’s Manual 6-1 10.99 On-Chip Peripheral Components C505L are at P3.4 / T0 and P3.5 / T1 and have a digital alternate input each, apart from LCD output functions. The C505L provides eight analog input lines that are implemented as mixed digital/analog inputs (type C). The 8 analog inputs, AN0-AN7, are located at the port 1 pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are configured as digital inputs. The analog function of the specific port 1 pins are enabled by bits in the SFRs P1ANA. Writing a 0 to a bit position of P1ANA assigns the corresponding pin to operate as analog input. Note: P1ANA is a mapped SFR and can only be accessed if bit RMAP in SFR SYSCON is set. As already mentioned, ports 1, 3, 4 and 5 are provided for multiple alternate functions. These functions are listed in Table 6-2. User’s Manual 6-2 10.99 On-Chip Peripheral Components C505L Table 6-2 Alternate Functions of Port 1, 3, 4 and 5 Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 Second / third Port Function Function Type AN0 / INT3 / CC0 AN1 / INT4 /CC1 AN2 / INT5 /CC2 AN3 / INT6 / CC3 AN4 AN5 / T2EX AN6 / CLKOUT AN7 / T2 RxD TxD INT0 INT1 T0 / C31 T1 / C30 WR RD C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C C C C C C C C B B B B F F B B E E E E E E E E E E E E E E Analog input channel 0 / External Interrupt 3 / Compare/Capture channel 0 input/output Analog input channel 1 / External Interrupt 4 input / Compare/Capture channel 1 input/output Analog input channel 2 / External Interrupt 5 input / Compare/Capture channel 2 input/output Analog input channel 3 / External Interrupt 6 input / Compare/Capture channel 3 input/output Analog input channel 4 Analog input channel 5 / Timer 2 external reload / trigger input Analog input channel 6 / System clock output Analog input channel 7 / Timer 2 external count input Serial port’s receiver data input (asynchronous) or data input/output (synchronous) Serial port’s transmitter data output (asynchronous) or data clock output (synchronous) External interrupt 0 input, timer 0 gate control External interrupt 1 input, timer 1 gate control Timer 0 external counter input / LCD column 31 output Timer 1 external counter input / LCD column 30 output External data memory write strobe External data memory read strobe LCD column 16 output LCD column 17 output LCD column 18 output LCD column 19 output LCD column 20 output LCD column 21 output LCD column 22 output LCD column 23 output LCD column 24 output LCD column 25 output LCD column 26 output LCD column 27 output LCD column 28 output LCD column 29 output User’s Manual 6-3 10.99 On-Chip Peripheral Components C505L 6.1.2 Standard I/O Port Circuitry Figure 6-1 is a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the five I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop that will clock-in a value from the internal bus in response to a “write-to-latch” signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a “read-latch” signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a “read-pin” signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to P5) activate the “read-latch” signal, while others activate the “read-pin” signal. Read Latch Int. Bus Write to Latch D Port Latch CLK Q Port Driver Circuit Port Pin Q MCS01822 Read Pin Figure 6-1 Basic Structure of a Port Circuit User’s Manual 6-4 10.99 On-Chip Peripheral Components C505L The output drivers of Port 1 to 5 have internal pull-up FETs (see Figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain 1 (that means for Figure 6-2: Q = 0), which turns off the output driver FET n1. Then, for ports 1 to 5, the pin is pulled high by the internal pull-ups, but can be pulled low by an external source. When externally pulled low, the port pins source current (IIL or ITL). For this reason, these ports are called “quasi-bidirectional”. Read Latch VDD Internal Pull Up Arrangement Port Pin Int. Bus Write to Latch D Bit Latch CLK Q Q n1 MCS03844 Read Pin Figure 6-2 Basic Output Driver Circuit of Ports 1 to 5 User’s Manual 6-5 10.99 On-Chip Peripheral Components C505L 6.1.2.1 Port 0 Circuitry Port 0, in contrast to ports 1 to 5, is considered to be a “true” bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pull-ups. The pull-up FET in the P0 output driver (see Figure 6-3) is used only when the port is emitting 1s during external memory accesses. Otherwise, the pull-up is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a 1 to the port latch leaves both output FETs off and the pin floats. In that condition, the pin can be used as high-impedance input. If port 0 is configured as general I/O port and has to emit logic high-level (1), external pull-ups are required. Addr./Data Read Latch Control & VDD =1 Port Pin Int. Bus Write to Latch D Bit Latch CLK Q Q MUX Read Pin MCS03845 Figure 6-3 Port 0 Circuit User’s Manual 6-6 10.99 On-Chip Peripheral Components C505L 6.1.2.2 Port 1 and Port 3 Circuitry The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to implement the special features as listed in Table 6-2. Figure 6-4 is a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a 1 or the pulldown FET will be on and the port pin will be stuck at 0. After reset, all port latches contain 1 s. Read Latch Alternate Output Function VDD Internal Pull Up Arrangement Port Pin Int. Bus Write to Latch D Bit Latch CLK Q & Q MCS03846 Read Pin Alternate Input Function Figure 6-4 Ports 1 and 3 The LCD output functions of Port 3.4/T0 and P3.5/T1 pins are of type F. User’s Manual 6-7 10.99 On-Chip Peripheral Components C505L 6.1.2.3 Port 2 Circuitry As shown in Figure 6-3 and Figure 6-5, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application these ports cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P0/P2 SFR remains unchanged. Since it is an address/data bus, port 0 uses a pull-up FET as shown in Figure 6-3. When a 16-bit address is used, port 2 uses the additional strong pull-up p1 (Figure 6-5a) to emit 1s for the entire external memory cycle instead of the weak 1s (p2 and p3) used during normal port activity. Read Latch Address Control V DD Internal Pull UP Arrangement MUX Q =1 Port Pin Int. Bus Write to Latch D Latch CLK Q Read Pin MCS03847 Figure 6-5 Port 2 Circuit If no external bus cycles are generated using data or code memory accesses, port 0 can be used for I/O functions. User’s Manual 6-8 10.99 On-Chip Peripheral Components C505L Addr. Control VDD Q _ 1 V SS Enable Analog Input (Bits of SFR P1ANA) Input Data (Read Pin) =1 =1 to A / D Converter MCT03850 Figure 6-7 Driver Circuit of Type C Port Pins User’s Manual 6-12 10.99 On-Chip Peripheral Components C505L 6.1.3.3 Type D Port Driver Circuitry Figure 6-8 shows the C505L’s port driver circuit of the type D. These pins are used for the dedicated LCD Outputs, R0-R3 and C0-C15. The p-channel transistor p2 is a weak pull-up transistor similar to the p2 transistor in other digital I/O ports. After a reset operation, the LCD Controller remains disabled. At this point, the weak pull-up is enabled. When, the LCD controller is enabled by bit LCEN in SFR SYSCON, this transistor is switched off, making the LCD output available at the port pin. LCD levels are in the range mentioned in the DC Specifications (refer to Data Sheet). VDD LCEN p2 LCD Output ( from LCD Controller ) Port Pin MCS03851 Figure 6-8 Driver Circuit of Type D Port Pins User’s Manual 6-13 10.99 On-Chip Peripheral Components C505L 6.1.3.4 Type E and F Port Driver Circuitry Figure 6-9 describes the output structure of Type E port 4 and 5 pins. Such pins have both digital I/O and LCD output functions. Ports 4 and 5 have no digital alternate function possible. When the LCD output is enabled, all digital output drivers are switched off; the respective output signals from the LCD controller are selected; and LCD voltage levels are available at the pins shown in Table 6-2. After reset, the LCD output functions remain disabled due the LCEN bit having been cleared in the register LCON. When the LCD Controller is enabled with bit LCEN, the bits DSB0 and DSB1 in the register LCON will enable/disable the LCD output lines C16-C23 and C24-C31, respectively. Delay = 1 State =1 >1 p1 >1 p2 VDD p3 Port Pin Q & n1 >1 V SS LCEN DSB0 or DSB1 >1 Input Data (Read Pin) =1 =1 C16 - C31 (LCD Column outputs) MCT03852 Figure 6-9 Driver Circuit of Type E and Type F Port Pins The digital I/O function of the Type F pins is similar to that of Type E digital I/O pins, with one difference. The digital alternate function is available for P3.4/T0/C31 and P3.5/T1/C30 only (see Section 6.1.2.2). User’s Manual 6-14 10.99 On-Chip Peripheral Components C505L 6.1.4 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period. During phase 2, the output buffer holds the value it noticed during the previous phase 1. Consequently, the new value in the port latch will not appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle. When an instruction reads a value from a port pin (e.g., MOV A, P1), the port pin is actually sampled in state 5 phase 1 or phase 2, depending on port and alternate functions. Figure 6-10 illustrates this port timing. It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an “edge”, e.g., when used as counter input. In this case an edge is detected when the sampled value differs from the value that was sampled the cycle before. Therefore, certain requirements must be met with regards to the pulse length of signals, in order to ensure that signal edges are detected. The minimum time period of high and low level is one machine cycle, which guarantees that this logic level is noticed by the port at least once. S4 P1 XTAL2 P2 P1 S5 P2 P1 S6 P2 P1 S1 P2 P1 S2 P2 P1 S3 P2 Input sampled: e.g. MOV A, P1 P1 active for 1 State (driver transistor) Port Old Data New Data MCT03231 Figure 6-10 Port Timing User’s Manual 6-15 10.99 On-Chip Peripheral Components C505L 6.1.5 Port Loading and Interfacing The output buffers of ports 1 to 5 can drive TTL inputs directly. The maximum port load that guarantees correct logic output levels is specified in the DC characteristics in the Data Sheet of the C505L. The corresponding parameters are VOL and VOH. The same condition applies to port 0 output buffers. They do, however, require external pull-ups to drive floating inputs, except when being used as the address/data bus. When used as inputs, ports 1 to 5 are not floating but have internal pull-up transistors. The driving devices must be capable of sinking a sufficient current if a logic low level shall is applied to the port pin. Parameters ITL and IIL in the DC characteristics of the Data Sheet specify these currents. Port 1 may be programmed to analog input function, but has floating inputs in these cases. User’s Manual 6-16 10.99 On-Chip Peripheral Components C505L 6.1.6 Read-Modify-Write Feature of Ports 0 to 5 Some port-reading instructions read the latch and others read the pin. Instructions that read the latch rather than the pin do read a value, possibly change it, and then rewrite it to the latch. These “read-modify-write” instructions are listed in Table 6-3. If the destination is a port or a port pin, these instructions read the latch rather than the pin. Note that all other instructions that can be used to read a port just read the port pin. Reading from either the latch or the pin is performed by reading the SFR P0, P2 and P3; for example, “MOV A, P3” reads the value from port 3 pins, while “ANL P3, #0AAH” reads from the latch, modifies the value and writes it back to the latch. It is not obvious that the last three instructions in Table 6-3 are read-modify-write instructions, but they are because they read the port byte - all 8 bits - and modify the addressed bit, then write the complete byte back to the latch. Table 6-3 “Read-Modify-Write” Instructions Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV Px.y,C CLR Px.y SETB Px.y Function Logic AND; e.g. ANL P1, A Logic OR; e.g. ORL P2, A Logic exclusive OR; e.g. XRL P3, A Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL Complement bit; e.g. CPL P3.0 Increment byte; e.g. INC P4 Decrement byte; e.g. DEC P5 Decrement and jump if not zero; e.g. DJNZ P3, LABEL Move carry bit to bit y of port x Clear bit y of port x Set bit y of port x Read-modify-write instructions are directed to the latch rather than the pin in order to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a 1 is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor (approx. 0.7 V, i.e. a logic low level!) and interpret it as 0. For example, when modifying a port bit by a SETB or CLR instruction, another bit in this port with the configuration mentioned above might be changed if the value read from the pin were written back to the latch. However, reading the latch rather than the pin will return the correct value of 1. User’s Manual 6-17 10.99 On-Chip Peripheral Components C505L 6.2 Timers/Counters The C505L contains three 16-bit timers/counters (timer 0, 1, and 2) which are useful in many applications for timing and counting. In “timer” function, the timer register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 6 oscillator periods, the counter rate is 1/6 of the oscillator frequency. In “counter” function, the timer register is incremented in response to a 1-to-0 transition (falling edge) at the corresponding external input pin (T0, T1, or T2, which provide alternate functions of P3.4, P3.5 and P1.7, respectively). In the counter function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but it must be held for at least one full machine cycle to ensure that a given level is sampled at least once before it changes. 6.2.1 Timer/Counter 0 and 1 Timer/counter 0 and 1 of the C505L are fully compatible with timer/counter 0 and 1 of the C501 and can be used in the same four operating modes: Mode 0: 8-bit timer/counter with a divide-by-32 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; Timer/counter 1 in this mode holds its count. The effect is the same as setting TR1 = 0. External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. Each timer consists of two 8-bit registers (TH0 and TL0 for timer/counter 0, TH1 and TL1 for timer/counter 1) that may be combined to one timer configuration depending on the mode that is established. The functions of the timers are controlled by two Special Function Registers (SFRs), TCON and TMOD. In the following descriptions, TH0 and TL0 are used to specify the high byte and the low byte of timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for timer 0. If not explicity noted otherwise, this applies also to timer 1. User’s Manual 6-18 10.99 On-Chip Peripheral Components C505L 6.2.1.1 Timer/Counter 0 and 1 Registers Six SFRs control the timer/counter 0 and 1 operation: – TL0/TH0 and TL1/TH1 - counter registers, low and high part – TCON and TMOD - control and mode select registers Special Function Register TL0 (Address 8AH) Special Function Register TH0 (Address 8CH) Special Function Register TL1 (Address 8BH) Special Function Register TH1 (Address 8DH) Bit No. MSB 7 .7 Reset Value: 00H Reset Value: 00H Reset Value: 00H Reset Value: 00H LSB 0 .0 TL0 6 .6 5 .5 4 .4 3 .3 2 .2 1 .1 8AH 8CH .7 .6 .5 .4 .3 .2 .1 .0 TH0 8BH .7 .6 .5 .4 .3 .2 .1 .0 TL1 8DH .7 .6 .5 .4 .3 .2 .1 .0 TH1 Bit Function TLx.7-0 Timer/counter 0/1 low register x = 0-1 Operating Mode Description 0 1 2 3 “TLx” holds the 5-bit prescaler value. “TLx” holds the lower 8-bit part of the 16-bit timer/counter value. “TLx” holds the 8-bit timer/counter value. TL0 holds the 8-bit timer/counter value; TL1 is not used. THx.7-0 Timer/counter 0/1 high register x = 0-1 Operating Mode Description 0 1 2 3 “THx” holds the 8-bit timer/counter value. “THx” holds the higher 8-bit part of the 16-bit timer/counter value “THx” holds the 8-bit reload value. TH0 holds the 8-bit timer value; TH1 is not used. User’s Manual 6-19 10.99 On-Chip Peripheral Components C505L Special Function Register TCON (Address 88H) Bit No. MSB 7 8FH 88H TF1 6 8EH TR1 5 8DH TF0 4 8CH TR0 3 8BH IE1 2 8AH IT1 1 89H IE0 Reset Value: 00H LSB 0 88H IT0 TCON The shaded bits are not used for controlling timer/counter 0 and 1. Bit TR0 TF0 Function Timer 0 run control bit Set/cleared by software to turn timer/counter 0 ON/OFF. Timer 0 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit Set/cleared by software to turn timer/counter 1 ON/OFF. Timer 1 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR1 TF1 User’s Manual 6-20 10.99 On-Chip Peripheral Components C505L Special Function Register TMOD (Address 89H) Bit No. 89H MSB 7 Gate Reset Value: 00H LSB 0 M0 TMOD 6 C/T 5 M1 4 M0 3 Gate 2 C/T 1 M1 Timer 1 Control Timer 0 Control Bit GATE Function Gating control When set, timer/counter “x” is enabled only while “INT x” pin is high and “TRx” control bit is set. When cleared, timer “x” is enabled whenever “TRx” control bit is set. Counter or timer select bit Set for counter operation (input from “Tx” input pin). Cleared for timer operation (input from internal system clock). Mode select bits M1 0 M0 0 Function 8-bit timer/counter: “THx” operates as 8-bit timer/counter “TLx” serves as 5-bit prescaler 16-bit timer/counter. “THx” and “TLx” are cascaded; there is no prescaler 8-bit auto-reload timer/counter. “THx” holds a value which is to be reloaded into “TLx” each time it overflows Timer 0: TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only controlled by timer 1 control bits. Timer 1: Timer/counter 1 stops C/T M1 M0 0 1 1 0 1 1 User’s Manual 6-21 10.99 On-Chip Peripheral Components C505L 6.2.1.2 Mode 0 Putting either timer/counter 0 or timer/counter 1 into mode 0 configures it as an 8-bit timer/counter with a divide-by-32 prescaler. Figure 6-11 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0 s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer to be controlled by external input INT0, in order to facilitate pulse width measurements. TR0 is a control bit in the SFR TCON; Gate is in TMOD. The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag TR0 does not clear the registers. Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR0, TF0, TH0, TL0 and INT0 for the corresponding timer 1 signals in Figure 6-11. There are two different gate bits, one for timer 1 (TMOD.7) and one for timer 0 (TMOD.3). OSC ÷6 C/T = 0 TL0 (5 Bits) C/T = 1 TH0 (8 Bits) TF0 Interrupt P3.4/T0 Control Gate =1 _ 1 OWDS WDTS RESET Clear External HW Reset Request Synchro- Internal Reset nization Internal Bus MCT03307 Figure 8-2 Watchdog Timer Status Flags and Reset Requests User’s Manual 8-5 10.99 Fail Safe Mechanisms C505L 8.2 Oscillator Watchdog Unit The oscillator watchdog serves three functions: – Monitoring the on-chip oscillator’s function The watchdog supervises the on-chip oscillator’s frequency. If it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset. If the failure condition disappears (i.e., the on-chip oscillator has a higher frequency than the RC oscillator), the device executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize. Then the oscillator watchdog reset is released and the device starts program execution from address 0000H again. – Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit and the monitoring function also work identically. – Control of wake-up from software power-down mode When the power-down mode is left by a low level signal at the P3.2/INT0 pin or an active Real Time Clock Interrupt Request flag IRTC, the oscillator watchdog unit ensures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode, the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts program execution by processing a power down interrupt after a final delay (typ. 1 ms) in order to allow the on-chip oscillator to stabilize. Note: The oscillator watchdog unit is always enabled. Special Function Register IP0 (Address A9H) MSB 7 Reset Value: 00H LSB 0 IP0.0 IP0 Bit No. A9H 6 5 IP0.5 4 IP0.4 3 IP0.3 2 IP0.2 1 IP0.1 OWDS WDTS The shaded bits are not used for fail-safe control. Bit OWDS Function Oscillator WatchDog Status Flag. Set by hardware when an oscillator watchdog reset occurred. Can be set and cleared by software. User’s Manual 8-6 10.99 Fail Safe Mechanisms C505L 8.2.1 Detailed Description of the Oscillator Watchdog Unit Figure 8-2 is a block diagram of the oscillator watchdog unit. The oscillator watchdog consists of an internal RC oscillator that provides the reference frequency for the comparison with the frequency of the on-chip oscillator. Figure 8-3 also shows the additional provisions for integration of the wake-up from power-down mode. EWPD IRTC (RTCON.2) P3.2 / INT0 Control Logic WS Power - Down Mode Activated (PCON1.0) Power - Down Mode Wake - Up Interrupt Control Logic Internal Reset Start / Stop RC Oscillator f RC 3 MHz XTAL2 XTAL1 On-Chip Oscillator OWDS 10 f1 Frequency Comparator f 2 1 Start / Stop f2 IP0 (A9 H ) Int. Clock MCB03870 Figure 8-3 Functional Block Diagram of the Oscillator Watchdog The frequency of the RC oscillator is divided by 10 and compared with the on-chip oscillator’s frequency. If the frequency of the on-chip oscillator is lower than the frequency derived from the RC oscillator the watchdog detects a failure condition. For example, the oscillation at the on-chip oscillator could stop because of crystal damage, etc. In this case, it switches the input of the internal clock system to the output of the RC oscillator. This means that the device is being clocked even if the on-chip oscillator has stopped or has not yet started. At the same time, the watchdog activates the internal reset in order to bring the device to its defined reset state. The reset is performed because a clock signal is available from the RC oscillator. This internal watchdog reset has the same effects as an externally-applied reset signal with the following exceptions: The Watchdog Timer Status flag WDTS is not reset (the watchdog timer is, however, stopped); and bit OWDS is set. This allows the software to examine error conditions detected by the watchdog unit even if meanwhile an oscillator failure occurred. User’s Manual 8-7 10.99 Fail Safe Mechanisms C505L The oscillator watchdog is able to detect a recovery of the on-chip oscillator after a failure. If the frequency derived from the on-chip oscillator is again higher than the reference, the watchdog starts a final reset sequence which takes 1 ms. Within that time, the clock is still supplied by the RC oscillator and the device is held in reset. This allows a reliable stabilization of the on-chip oscillator. After that, the watchdog switches the clock supply back to the on-chip oscillator and releases the oscillator watchdog reset. If no other reset is applied at this time, the device will start program execution. If an external reset or a watchdog timer reset is active, however, the device will retain the reset state until the other reset request disappears. Furthermore, the status flag OWDS is set if the oscillator watchdog was active. The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog. The flag OWDS can be set or cleared by software. An external reset request, however, also resets OWDS (and WDTS). If software power-down mode is activated, the RC oscillator and the on-chip oscillator are stopped. Both oscillators are again started in power-down mode when a low level signal is detected at either the P3.2/INT0 input pin or the real-time clock interrupt flag (IRTC), when bit EWPD in SFR PCON1 is set (wake-up from power-down mode enabled). The wake-up source is chosen from one of P3.2/ INT0 and IRTC (RTCON.3) by bit WS in SFR PCON1. In this case, the oscillator watchdog does not execute an internal reset during start-up of the on-chip oscillator. After the start-up phase of the on-chip oscillator, the watchdog generates a power-down mode wake-up interrupt. Detailed description of the wake-up from software power-down mode is given in Section 9.4.2. 8.2.2 Fast Internal Reset after Power-On The C505L can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Normally, the members of the 8051 family (e. g. SAB 80C52) do not enter their default reset state before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. In particular, the start up time of the oscillator is relatively long (typ. 1 ms) if a crystal is used. During this time period, the pins are in an undefined state that could have severe effects, e.g., on actuators connected to port pins. In the C505L, the oscillator watchdog unit avoids this situation. After power-on, the oscillator watchdog's RC oscillator starts working within a very short start-up time (typically less than 2 µs). Then the watchdog circuitry detects a failure condition for the on-chip oscillator because it has not yet started. A failure is always recognized if the watchdog’s RC oscillator runs faster than the on-chip oscillator. As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip. This allows correct resetting of the device and brings all ports to the defined state (see also Chapter 5 of this manual). User’s Manual 8-8 10.99 Power Saving Modes C505L 9 Power Saving Modes The C505L provides three basic power-saving modes, the idle mode, the slow-down mode and the power-down mode. 9.1 Power-saving Mode Control Registers The functions of the power-saving modes are controlled by bits in the Special Function Registers (SFRs) PCON and PCON1. The SFR PCON is located at SFR address 87H. PCON1 is located in the mapped SFR area (RMAP = 1) at SFR address 88H. Bit RMAP, which controls the access to the mapped SFR area, is located in SFR SYSCON (B1H). The bits PDE, PDS and IDLE, IDLS located in SFR PCON select the power-down mode or the idle mode, respectively. If the power-down mode and the idle mode are set at the same time, power-down takes precedence. The slow-down mode is controlled by the bit SD located in SFR PCON. Furthermore, SFR PCON contains two general-purpose flags. For example, the flag bits GF0 and GF1 can be used to indicate whether an interrupt occurred during normal operation or during idle mode. For that function, an instruction that activates idle mode can also set one or both flag bits. When idle mode is terminated by an interrupt, the interrupt service routine can examine the flag bits. Special Function Register PCON (Address 87H) Bit No. 87H MSB 7 SMOD Reset Value: 00H LSB 0 IDLE PCON 6 PDS 5 IDLS 4 SD 3 GF1 2 GF0 1 PDE The function of the shaded bit is not described in this section. Symbol PDS Function Power-Down Start bit The instruction that sets the PDS flag bit is the last instruction before entering the power-down mode IDLe Start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode. Slow-Down mode bit When set, the slow-down mode is enabled General-purpose flag General-purpose flag Power-Down Enable bit When set, starting of the power-down is enabled IDLe mode Enable bit When set, starting of the idle mode is enabled IDLS SD GF1 GF0 PDE IDLE User’s Manual 9-1 10.99 Power Saving Modes C505L Register LCON (Address F3DDH) Bit No. MSB 7 Reset Value: 00H LSB 0 LCEN LCON 6 DSB0 5 0 4 0 3 0 2 0 1 CSEL F3DDH DSB1 The functions of the shaded bits are not described in this section. Bit LCEN Function ENables LCD controller LCEN = 0: LCD Controller is disabled (default after reset). LCEN = 1: LCD Controller is enabled. LCD input Clock SELection CSEL = 1: Use RTC Clock input (32.768 KHz) for fLCDIN CSEL = 0: Use system clock (fOSC) for fLCDIN Reset Value: 00H LSB 0 RTCS RTCON CSEL Register RTCON (Address F3F0H) Bit No. F3F0H MSB 7 0 6 0 5 0 4 0 3 RTPD 2 IRTC 1 ERTC The functions of the shaded bits are not described in this section. Bit RTPD Function Real-Time clock Power-Down enable RTPD = 0: Real-Time clock is in operation RTPD = 1: Real-Time clock is powered down Real-Time clock is in operation by default after reset. Registers LCON and RTCON are used for controlling the power-down modes of the LCD controller and the real-time clock, respectively. Please refer to Section 9.4 for further details. User’s Manual 9-2 10.99 Power Saving Modes C505L Special Function Register PCON1 (Mapped Address 88H) Bit No. 88H MSB 7 EWPD Reset Value: 0XX0XXXXB LSB 0 – PCON1 6 – 5 – 4 WS 3 – 2 – 1 – Symbol EWPD Function External Wake-up from Power-Down enable bit Setting EWPD before entering power-down mode, enables wake-up from power-down mode capability. Wake-up from power-down Source select WS = 0: wake-up via P3.2/INT0 (external wake-up) WS = 1: wake-up via real-time clock interrupt Reserved bits for future use. Read by CPU returns undefined values. WS – User’s Manual 9-3 10.99 Power Saving Modes C505L 9.2 Idle Mode In the idle mode, the C505L’s oscillator continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter (ADC), the LCD controller, the real-time clock, and all timers with the exception of the watchdog timer are further provided with the clock. The CPU status is preserved in its entirety: The Stack Pointer, Program Counter, Program Status Word (PSW), accumulator, and all other registers maintain their data during idle mode. The reduction of power consumption which can be achieved in the idle mode depends on the number of peripherals running. If all timers are stopped, and the ADC and the serial interfaces are not running, the maximum power reduction can be achieved. This state is also the test condition for the idle mode current (IDD). Thus, the user has to take care as to which peripheral(s) should continue to run and which has to be stopped during idle mode. Also, the state of all port pins – either the pins controlled by their latches or controlled by their secondary functions – depends on the status of the controller when entering idle mode. Normally, the port pins hold the logical state they had at that time when the idle mode was activated. If some pins are programmed to serve as alternate functions they still continue to output during idle mode if the assigned function is on. This applies especially to the serial interface in case it cannot finish reception or transmission during normal operation. The control signals ALE and PSEN are held at logic high levels. As in normal operation mode, the ports can be used as inputs during idle mode. Thus a capture or reload operation can be triggered, the timers can be used to count external events, and external interrupts will be detected. The idle mode is a useful feature that makes it possible to “freeze” the processor’s status, either for a predefined time, or until an external event causes the controller to revert to normal operation, as discussed below. The watchdog timer is the only peripheral which is stopped automatically during idle mode. User’s Manual 9-4 10.99 Power Saving Modes C505L The idle mode is entered by two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5). The subsequent instruction sets the start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). The hardware ensures that a concurrent setting of both bits, IDLE and IDLS, does not initiate the idle mode. Bits IDLE and IDLS will be cleared automatically after being set. If one of these register bits is read, the value that appears is 0. This double instruction is implemented to minimize the chance of entering the idle mode unintentionally, which would leave the watchdog timer unable to protect the system. Note PCON is not a bit-addressable register, so the sequence mentioned above for entering the idle mode is accomplished by byte-handling instructions, as shown in the following example: ORL ORL PCON,#00000001B PCON,#00100000B ;Set bit IDLE, bit IDLS must not be set ;Set bit IDLS, bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode. There are two ways to terminate the idle mode: – The idle mode can be terminated by activating any enabled interrupt. The CPU operation is resumed, the interrupt will be serviced, and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bit IDLS. – The other way to terminate the idle mode is a hardware reset. Since the oscillator is still running, the hardware reset must be held active for only two machine cycles for a complete reset. User’s Manual 9-5 10.99 Power Saving Modes C505L 9.3 Slow-down Mode Operation In some applications where power consumption and dissipation are critical, the controller might run for a certain time at reduced speed (e.g. if the controller is waiting for an input signal). Since in CMOS devices there is an almost linear dependency between the operating frequency and the power supply current, a reduction of the operating frequency results in reduced power consumption. In the slow-down mode, all signal frequencies that are derived from the oscillator clock are divided by 32. The slow-down mode is activated by setting the bit SD in SFR PCON. If the slow-down mode is enabled, the clock signals for the CPU and the peripheral units are reduced to 1/32 of the nominal clock rate. The controller actually enters the slow-down mode after a short synchronization period (max. two machine cycles). The slow-down mode is terminated by clearing bit SD. The slow-down mode can be combined with the idle mode by performing the following double instruction sequence: ORL ORL PCON,#00000001B PCON,#00110000B ; preparing idle mode: set bit IDLE (IDLS not set) ; entering idle mode combined with the slow-down mode: ; (IDLS and SD set) There are two ways to terminate the combined idle and slow-down mode: – The idle mode can be terminated by activation of any enabled interrupt. The CPU operation is resumed, the interrupt will be serviced, and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bits IDLS and SD. Nevertheless the slow-down mode remains enabled, and if it is necessary to terminate this mode, that can be accomplished by clearing the bit SD in the corresponding interrupt service routine or at any point in the program where the user no longer requires the slow-down mode. – The combined idle and slow-down mode can also be terminated by a hardware reset. Since the oscillator is still running, the hardware reset has to be held active for only two machine cycles for a complete reset. User’s Manual 9-6 10.99 Power Saving Modes C505L 9.4 Software Power-down Modes In order to achieve different levels of power-saving, the C505L has three major software power-down modes as described below: – Software power-down mode 1, in which all the peripheral blocks and the CPU are stopped. In this mode, the RC oscillator and the on-chip oscillator that operates with the XTAL1 and XTAL2 pins are stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFRs are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFRs. The port pins that serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power-down mode. ALE and PSEN are held at logic low level (see Table 9-1). – Software power-down mode 2, in which only the Real-time clock and LCD controller are operating. In this mode, the CPU and the rest of the peripherals are stopped. The RC oscillator and the on-chip oscillator are stopped, the real-time clock oscillator that operates with the XTAL3 and XTAL4 pins is still running and the real-time count is maintained in this mode. – Software power-down mode 3, in which only the real-time clock is operating. In this mode, the clock input into the CPU, LCD controller and the rest of the peripherals are stopped. The only difference between this mode and mode 2 is that the LCD controller is also stopped in this mode. The LCD controller output pins are inactive in this stage and should not be used for any input function. In both software power-down modes 2 and 3, all the functions of the microcontroller other than those described above are stopped, and the contents of the on-chip RAM, XRAM and SFRs are maintained. The unused pins in these modes have the behavior as in the software power-down mode 1. In all the software power-down modes, VDD can be reduced to minimize power consumption. In the case of the software power-down mode 3, VDD can be reduced to 3 V (lower specification limit). It must be ensured, however, that VDD is not reduced before any of the power-down modes is invoked, and that VDD is restored to its normal operating level before leaving the power-down mode. Any of these software power-down modes can be exited either by an active reset signal or by a wake-up request. Using reset to leave power-down mode puts the microcontroller with its SFRs into the reset state. Program execution then starts from the address 0000H. Using a wake-up request to exit the power-down mode starts the RC oscillator and the on-chip oscillator and maintains the state of the SFRs, which were frozen when power-down mode was entered. When the C505L is in software power-down mode 1, a wake-up operation is possible only through P3.2/INT0. There are two ways to use a wake-up request to exit power-down modes 2 and 3: - Wake-up via P3.2/INT0 pin when bit WS in SFR PCON1 is cleared, and - Wake-up via the real-time clock interrupt when bit WS in SFR PCON1 is set User’s Manual 9-7 10.99 Power Saving Modes C505L 9.4.1 Invoking Software Power-down Modes The C505L’s software power-down modes can be entered as shown below: • Software Power-down Mode 1 - This mode is entered by first ensuring that both the LCD controller and the real-time clock are disabled. This is done by clearing bit LCEN (LCON.0) and setting bit RTPD (RTCON.3). Once these conditions are fulfilled, software power-down mode 1 is entered by two consecutive instructions. The first instruction has to set the flag bit PDE (PCON.1) and must not set bit PDS (PCON.6). The subsequent instruction has to set the start bit PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a concurrent setting of both bits, PDE and PDS, does not initiate the power-down mode. Bits PDE and PDS will be cleared automatically after having been set, and the value shown by reading one of these bits is always 0. The double instruction is implemented to minimize the chance of entering the power-down mode unintentionally, which could possibly “freeze” the chip’s activity in an undesired status. PCON is not a bit-addressable register, so the above mentioned sequence for entering the power-down mode can be accomplished by byte-handling instructions, as shown in the following example: ORL ORL PCON,#00000010B PCON,#01000000B ;set bit PDE, bit PDS must not be set ;set bit PDS, bit PDE must not be set, enter power-down • Software Power-down Mode 2 - This mode is entered by first ensuring that both the LCD controller and the real-time clock are enabled. The following conditions should be met: – bit LCEN (LCON.0) is set, – bit CSEL (LCON.1) is set, and – bit RTPD (RTCON.3) is cleared. Once these conditions are fulfilled, the C505L can enter software power-down mode 2 with the two instruction sequence as in mode 1. • Software Power-down Mode 3 - This mode is entered by first ensuring that the real-time clock is enabled and the LCD controller is disabled. The following conditions should be met: – bit RTPD (RTCON.3) is cleared, and – bit LCEN (LCON.0) is cleared. Once these conditions are fulfilled, the C505L can enter software power-down mode 3 with the two instruction sequence as in mode 1. In any of the above modes, the instruction that sets bit PDS is the last instruction executed before going into power-down mode. Note: Before entering the power-down mode, any A/D conversion in progress must be stopped. User’s Manual 9-8 10.99 Power Saving Modes C505L 9.4.2 Exit from Software Power-down Mode The C505L can exit the software power-down modes in one of the following 2 ways: – Hardware reset – Wake-up from power-down mode through pin P3.2/ INT0 or real-time clock interrupt If the bit EWPD in SFR PCON1 is 0 during power-down entry, the only way to exit from the power-down mode is a hardware reset. This reset will redefine all the SFRs but will not change the contents of the internal RAM and XRAM. The reset signal that terminates the power-down mode also restarts the RC oscillator and the on-chip oscillator. The reset operation should not be activated before VDD is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). If the wake-up from power-down capability is used, this function must be enabled using the following instruction sequence prior to entering the power-down mode. ORL ORL ANL SYSCON,#00010000B PCON1,#80H SYSCON,#11101111B ;set RMAP ;enable external wake-up from power-down by setting EWPD ;reset RMAP (for future SFR accesses) User’s Manual 9-9 10.99 Power Saving Modes C505L Figure 9-1 shows the procedure which must be executed when power-down modes are exited via the P3.2/INT0 wake-up request capability. Power Down Mode 1) P3.2/ INT0 Latch Phase 2) Watchdog Circuit Oscillator Start-up Phase 3) ~ ~ ~ ~ Execution of Interrupt at 007B H 4) 10 µ s min. 5 ms typ. RETI Instruction Detailed Timing of Beginning of Phase 4 ALE PSEN P2 P0 Invalid Address Invalid Address/Data 7B H 00 H 1st. Instr. of ISR MCT02597 Figure 9-1 Wake-up from Power-down Mode Procedure When the power-down mode wake-up capability has been enabled (bit EWPD in SFR PCON1 set) prior to entering power-down mode, and bit WS in SFR PCON1 is cleared, the power-down mode can be exited via INT0 while executing the following procedure: 1. In power-down mode, pin P3.2/INT0 must be held at high level. 2. Power-down mode is exited when P3.2/INT0 goes low for at least 10 µs (latch phase). After this delay, the internal RC oscillator, and the on-chip oscillator are started, the state of pin P3.2/INT0 is internally latched, and P3.2/INT0 can be set again to a high level if required. Thereafter, the oscillator watchdog unit controls the wake-up procedure in its start-up phase. 3. The oscillator watchdog unit starts operation. When the on-chip oscillator clock’s stable nominal frequency has been detected, the microcontroller starts again and initiates the power-down wake-up interrupt. The interrupt address of the first instruction to be executed after wake-up is 007BH. ALE and PSEN are in their power-down state up to this time. At the end of phase 3, the CPU processes the interrupt call and during these two machine cycles, ALE and PSEN behave as shown in Figure 9-1 (i.e., at the beginning of phase 4). Instruction fetches during the interrupt call are discarded, however. User’s Manual 9-10 10.99 Power Saving Modes C505L 4. After the RETI instruction of the power-down wake-up interrupt routine has been executed, the instruction that follows the double instruction sequence that initiates the power-down mode will be executed. The peripheral units timer 0/1/2 and watchdog timer are frozen until the end of phase 4. All of the C505L’s interrupts are disabled from phase 2 until the end of phase 4. Other interrupts can be handled first after the RETI instruction of the wake-up interrupt routine. Note: To avoid any unintentional external interrupt request, the user should ensure that P3.2/INT0 is set back to high level, after a wake-up request, prior to completion of the wake-up sequence. Prior to entering the software power-down mode, the port latch of SFR P3.2 (P3.2/INT0 pin) should contain a “1”. Otherwise, the wake-up sequence described above will be started immediately after the power-down mode has been entered. The wake-up routine initiated by the real-time clock interrupt is similar to the wake-up from P3.2/ INT0, and can be used to wake-up from power-down modes 2 and 3. For this to occur, it is necessary to enable both the wake-up capability (bit EWPD in SFR PCON1 should be set) and the real-time clock interrupt have to be enabled (bit ERTC in RTCON). Additionally, the real-time clock should be selected as the source of the wake-up request (bit WS in SFR PCON1 must be set). An interrupt can then be generated by the real-time clock at a predetermined time, depending on the setting of the RTINT register. This interrupt will then be used as a wake-up request. The flag IRTC is set by hardware and has to be cleared by software. The handling of such a wake-up request is, however, identical to the handling of the wake-up through P3.2/INT0. The real-time clock wake-up interrupt has no effect on the device, unless the C505L has entered the power-down mode. User’s Manual 9-11 10.99 Power Saving Modes C505L 9.5 State of Pins in Software-initiated Power-saving Mode In the idle mode and in the software power-down mode 1, the port pins of the C505L have a well-defined status which is listed in the following Table 9-1. This state of some pins also depends on the location of the code memory (internal or external). Table 9-1 Status of External Pins During Idle and Software Power-down Mode 1 Outputs Last Instruction Executed from Internal Code Memory Idle ALE PSEN PORT 0 PORT 2 PORT 1, 3, 4 and 5 High High Data Data Data/alternate outputs Power-down Low Low Data Data Data/last output Last Instruction Executed from External Code Memory Idle High High Float Address Data/alternate outputs Power-down Low Low Float Data Data/last output In software power-down mode 2, all the port pins are in the states as shown in Table 9-1, except for the enabled LCD output pins at Ports 3, 4 and 5. These pins output values corresponding to their digit registers. In the software power-down mode 3, all the port pins are in the states as shown in Table 9-1. User’s Manual 9-12 10.99 OTP Memory Operation C505L 10 OTP Memory Operation The C505L is the one-time programmable (OTP) version of the C505L microcontroller with a 32-Kbyte OTP program memory. The C505L has fast programming cycles (1 byte per 100 µs). Also, several levels of OTP memory protection can be selected. 10.1 Programming Configuration To program the device, the C505L must be put into the programming mode. Typically, this is done not “in-system” but with special programming hardware instead. In the programming mode, the C505L operates as a slave device similar to an EPROM stand-alone memory device, and must be controlled with address/data information, control lines, and an external 11.5 V programming voltage. In the programming mode, port 0 provides the bidirectional data lines and port 2 is used for the multiplexed address inputs. The upper address information at port 2 is latched with the signal PALE. The inputs RESET, PSEN, EA/VPP, ALE and PMSEL1/0 and PSEL are used for basic programming mode selection. Furthermore, the inputs PMSEL1,0 are required to select the access types (e.g., program/verify data, write lock-bits, and so forth) in the programming mode. VDD/VSS and a clock signal at the XTAL pins must be applied to the C505L in the programming mode. The 11.5 V external programming voltage is input through the EA/VPP pin. Figure 10-1 shows the pins of the C505L that are required for controlling of the OTP programming mode. V DD V SS P2.0 - 7 PALE Port 2 Port 0 P0.0 - 7 EA / V PP PMSEL0 PMSEL1 PROG C505L PRD RESET PSEN XTAL1 XTAL2 PSEL MCS03876 Figure 10-1 Programming Mode Configuration User’s Manual 10-1 10.99 OTP Memory Operation C505L 10.2 Pin Configuration Figure 10-2 shows the detailed pin configuration of the C505L in programming mode. D7 D6 D5 D4 D3 D2 D1 D0 60 61 A0 / A8 A1 / A9 A2 / A10 A3 / A11 A4 / A12 A5 / A13 A6 / A14 A7 N.C. N.C. V DD V SS XTAL1 XTAL2 EA / V PP PROG PSEN RESET PMSEL0 PMSEL1 55 50 45 41 40 65 35 V DD V SS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 70 C505L P - MQFP - 80 Package 30 75 25 80 1 5 10 15 21 20 PSEL PRD PALE N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. MCP03877 Figure 10-2 OTP Programming Mode Pin Configuration (top view) User’s Manual 10-2 10.99 OTP Memory Operation C505L 10.3 Pin Definitions Table 10-2 is a functional description of all C505L pins that are required for OTP memory programming. Table 10-2 Pin Definitions and Functions of the C505L in Programming Mode Symbol RESET Pin Number P-MQFP-80 43 I Reset This input must be at static “1” (active) level during the whole programming mode. Programming Mode SELection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PMSEL1 0 0 1 1 PSEL 40 I PMSEL0 0 1 0 1 Access Mode Reserved Read signature bytes Program/read lock-bits Program/read OTP memory byte I/O *) Function PMSEL0 PMSEL1 42 41 I I Basic Programming mode SELect This input is used for the basic programming mode selection and must be switched according to Figure 10-3. Programming mode ReaD strobe This input is used for read access control for OTP memory read, version byte read, and lock-bit read operations. Programming Address Latch Enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at a low level when the logic level of PMSEL1,0 is changed. XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the oscillator amplifier. PRD 39 I PALE 38 I XTAL2 XTAL1 47 48 O I *) I = Input O = Output User’s Manual 10-3 10.99 OTP Memory Operation C505L Table 10-2 Pin Definitions and Functions of the C505L in Programming Mode (cont’d) Symbol Pin Number P-MQFP-80 49, 70 50, 69 60-53 I/O *) Function – – I Circuit ground potential Must be applied in programming mode. Power supply terminal Must be applied in programming mode. Address lines P2.0-7 are used as multiplexed address input lines A0-A7 and A8-A14. A8-A14 must be latched with PALE. Program Store ENable This input must be at static “0” level during the whole programming mode. PROGramming mode write strobe This input is used in programming mode as a write strobe for OTP memory program, and lock-bit write operations. During basic programming mode selection a low level must be applied to PROG. Programming voltage This pin must be at 11.5 V (VPP) voltage level during programming of an OTP memory byte or lock-bit. During an OTP memory read operation, this pin must be at VIH high level. This pin is also used for basic programming mode selection. At basic programming mode selection a low level must be applied to EA/VPP. Data lines 0-7 During programming mode, data bytes are transferred via the bidirectional D7-0 lines that are located at port 0. Not Connected These pins should not be connected in programming mode. VSS VDD P2.0-7 PSEN 44 I PROG 45 I EA/VPP 46 – P0.7-0 68-61 I/O N.C. 1-37, 51-52, 71-80 – *) I = Input O = Output User’s Manual 10-4 10.99 OTP Memory Operation C505L 10.4 Programming Mode Selection The selection of the OTP programming mode can be separated into two different parts: – Basic programming mode selection – Access mode selection With basic programming mode selection, the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic. After selection of the basic programming mode, OTP memory accesses are executed by using one of the access modes. These access modes include OTP memory byte program/read, version byte read, and program/ read lock byte operations. 10.4.1 Basic Programming Mode Selection The basic programming mode selection scheme is shown in Figure 10-3. V DD Clock (XTAL1 / XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE "0" "0" "1" 0,1 Stable "1" "0" 5V V PP EA / V PP During this period signals are not actively driven 0V V IH2 Ready for access mode selection MCS03878 Figure 10-3 Basic Programming Mode Selection User’s Manual 10-5 10.99 OTP Memory Operation C505L The basic programming mode is selected by executing the following steps: – With a stable VDD a clock signal is applied to the XTAL pins; the RESET pin is set to “1” level and the PSEN pin is set to “0” level. – PROG, PALE, PMSEL1 and EA/VPP are set to “0” level; PRD, PSEL, and PMSEL0 are set to “1” level. – PSEL is switched from “1” to “0” level and thereafter PROG is switched to “1” level. – PMSEL1,0 can now be changed; after EA/VPP has been set to VIH high level or to VPP the OTP memory is ready for access. The pins RESET and PSEN must stay at static signal levels “1” and “0”, respectively, during the whole programming mode. With a falling edge of PSEL, the logic state of PROG and EA/VPP is latched internally. These two signals are now used as programming write-pulse signal (PROG) and as programming voltage for input pin VPP. After the falling edge of PSEL, PSEL must stay at “0” state during all programming operations. Note: If protection level 1 to 3 has been programmed (see Section 10.6) and the programming mode has been left, it is no longer possible to enter the programming mode! 10.4.2 OTP Memory Access Mode Selection When the C505L has been put into the programming mode using the basic programming mode selection, several access modes of the OTP memory programming interface are available. The conditions for the different control signals of these access modes are listed in Table 10-3. Table 10-3 Access Modes Selection Access Mode Program OTP memory byte Read OTP memory byte Program OTP lock-bits Read OTP lock-bits Read OTP version byte EA/ VPP VPP VIH VPP VIH VIH PROG PRD H PMSEL 1 H H L 0 H L H Address (Port 2) A0-7 A8-14 – Byte addr. of version byte Data (Port 0) D0-7 D1, D0 see Table 10-4 D0-7 H H H H The access modes shown above are selected by setting the two PMSEL1,0 lines to the required logic level. The PROG and PRD signal are the write and read strobe signal. Data is transferred via port 0 and addresses are applied to port 2. The following sections describe the various access modes. User’s Manual 10-6 10.99 OTP Memory Operation C505L 10.5 Program/Read OTP Memory Bytes The program/read OTP memory byte access mode is defined by PMSEL1,0 = 1,1. It is initiated when the PMSEL1,0 = 1,1 is valid at the rising edge of PALE. With the falling edge of PALE, the upper addresses A8-A14 of the 15-bit OTP memory address are latched. After A8-A14 has been latched, A0-A7 is put on the address bus (port 2). A0-A7 must be stable when PROG is low or PRD is low. If subsequent OTP address locations are accessed with constant address information at the high address lines A8-A14, A8-A14 must be latched only once (page address mechanism). Figure 10-4 shows a typical basic OTP memory programming cycle with a subsequent OTP memory read operation. In this example A8-A14 of the read operation are identical to A8-A14 of the proceeding programming operation. PMSEL1,0 Port 2 PALE Port 0 A8-A14 1,1 A0-A7 D0 - D7 min. 100 µ s D0 - D7 PROG min. 100 ns PRD MCS03879 Figure 10-4 Programming/Verify OTP Memory Access Waveform If the address lines A8-A14 must be updated, PALE must be activated to latch the new A8-A14 value. Control, address, and data information must only be switched when the PROG and PRD signals are at a high level. The PALE high pulse must always be executed if a different access mode has been used prior to the actual access mode. User’s Manual 10-7 10.99 OTP Memory Operation C505L Figure 10-5 shows a waveform example of the program/read mode access for several OTP memory bytes. In this example, OTP memory locations 3FDH to 400H are programmed. Thereafter, OTP memory locations 400H and 3FDH are read. PMSEL1, 0 PALE 3FD Port 2 Port 0 PROG PRD 03 FD Data 1 3FE FE Data 2 3FF FF Data 3 1, 1 400 04 00 Data 4 400 00 Data 4 03 3FD FD Data 1 MCT03364 Figure 10-5 Typical OTP Memory Programming/Verify Access Waveform User’s Manual 10-8 10.99 OTP Memory Operation C505L 10.6 Programming and Reading Lock Bits The C505L has two programmable lock-bits that, when programmed according to Table 10-4, provide four levels of protection for the on-chip OTP code memory. Table 10-4 Lock Bit Protection Types Lock Bits at D1, D0 Protection Protection Type Level D1 D0 1 1 1 0 Level 0 Level 1 The OTP lock feature is disabled. During normal operation of the C505L, the state of the EA pin is not latched on reset. During normal operation of the C505L, MOVC instructions executed from external program memory are prevented from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible in the OTP verification mode. Further programming of the OTP memory is disabled (reprogramming security). Same as level 1, but OTP memory read operation using OTP verification mode is disabled. Same as level 2, but external code execution by setting EA = low during normal operation of the C505L is not possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the OTP memory boundary), is still possible. 0 0 1 0 Level 2 Level 3 Note: A “1” means that the lock-bit is unprogrammed. “0” means that lock-bit is programmed. For an OTP verify operation at protection level 1, the C505L must be put into the OTP verification mode. If a device is programmed with protection level 2 or 3, it is no longer possible to verify the OTP content of a customer rejected (FAR) OTP device. When a protection level has been activated by programming the lock-bits, the basic programming mode must be exited in order to activate the protection mechanisms. This means that after the activation of a protection level, further OTP program/verify operations are still possible if the basic programming mode is maintained. The state of the lock-bits can always be read if protection level 0 is selected. If protection level 1 to 3 has been programmed and the programming mode has been exited, it is not possible to re-enter the programming mode. In this case, the lock-bits cannot be read anymore. Figure 10-6 shows the waveform of a lock-bit write/read access. For a simple drawing, the PROG pulse is shortened. In practice, a 100 µs PROG low pulse must be applied for lock-bit programming. User’s Manual 10-9 10.99 OTP Memory Operation C505L PMSEL1,0 PALE Port 0 (D1, D0) PROG PRD 1,0 1,0 1,0 MCT03365 The example shows the programming and reading of a protection level 1. Figure 10-6 Write/Read Lock Bit Waveform User’s Manual 10-10 10.99 OTP Memory Operation C505L 10.6.1Access of Version Bytes The C505L provides 3 version bytes at address locations FCH, FDH, and FEH. The information stored in the version bytes, is defined by the mask of each microcontroller step. Therefore, the version bytes can be read but not written. The three version registers hold information such as manufacturer’s code, device type, and stepping code. To read the version bytes the control lines must be used according to Table 10-3 and Figure 10-7. The address of the version byte must be applied to the port 2 address lines. PALE must not be activated. PMSEL 1,0 PALE Port 2 Port 0 PROG PRD FC Ver. 0 0,1 FD Ver. 1 FE Ver. 2 MCT03366 Figure 10-7 Read Version Register(s) Waveform Version bytes are typically used by programming systems for adapting the programming firmware to specific device characteristics such as OTP size etc. Note: The 3 version bytes are implemented in a way that allows them be read during normal program execution mode as a mapped register with bit RMAP in Special Function register (SFR) SYSCON set. The addresses of the version bytes in normal mode and programming mode are identical and therefore they are located in the SFR address range. The steppings of the C505L versions will contain the following version register/byte information: Stepping C505L ES-AA-Step Version Byte 0 = VR0 Version Byte 1 = VR1 Version Byte 2 = VR2 (mapped addr. FEH) (mapped addr. FCH) (mapped addr. FDH) C5H 85H 01H Note: Future steppings of C505L would have a different version byte 2 content. User’s Manual 10-11 10.99 OTP Memory Operation C505L 10.7 OTP Verification Mode The OTP verification mode shown in Figure 10-8 is used to verify the contents of the OTP when the protection level 1 has been set. The detailed timing characteristics of the OTP verification mode are shown in the AC specifications (refer to Data Sheet). RESET 6 CLP 1. ALE pulse after reset ALE Latch Port 0 Data for Addr. 0 Latch Data for Addr. 1 Data for Ad. X 16 - 1 3 CLP Latch Data for Addr. X 16 Latch Data for Addr. X 16 + 1 P3.5 Inputs : ALE = V SS PSEN = V IH , EA = V IH2 RESET = Low: Verify Error High: Verify ok MCT03289 Figure 10-8 OTP Verification Mode OTP verification mode is selected if the inputs PSEN, EA, and ALE are set at the specified logic levels. With RESET going inactive, the OTP verification mode sequence is started. The C505L outputs an ALE signal with a period of 3 clock periods (CLP) and expects data bytes at port 0. The data bytes at port 0 are assigned to the OTP addresses in the following way: 1. Data Byte = content of OTP address 0000H 2. Data Byte = content of OTP address 0001H 3. Data Byte = content of OTP address 0002H : 16. Data Byte = content of OTP address 000FH : The C505L does not output any address information during the OTP verification mode. The first data byte to be verified is always the byte that is assigned to the OTP address 0000H, and it must be put onto the data bus with the falling edge of RESET. With each following ALE pulse, the OTP address pointer is internally incremented and the expected data byte for the next OTP address must be delivered externally. User’s Manual 10-12 10.99 OTP Memory Operation C505L Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared internally with the OTP content of the actual address. If a verify error is detected, the error condition is stored internally. After each 16th data byte, the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail and high for pass) during the time when the subsequent 16 bytes are checked. In OTP verification mode, the C505L must be provided with a system clock at the XTAL pins. Figure 10-9 shows an application example of an external circuitry that allows verification of the OTP, with protection level 1, inside the C505L in the OTP verification mode. When RESET goes inactive, the C505L starts the OTP verify sequence. Its ALE is clocking a 15-bit address counter. This counter generates the addresses for an external EPROM that is programmed with the contents of the OTP. The verify detect logic typically displays the pass/fail information of the verify operation. P3.5 can be latched with the falling edge of ALE. When the last byte of the OTP has been handled, the C505L starts generating a PSEN signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end of the OTP verification. User’s Manual 10-13 10.99 OTP Memory Operation C505L P3.5 Verify Detect Logic Carry CLK 2K 15 - Bit Address Counter S A0 - A14 ALE C505L & Compare Code ROM V DD & RESET Port 0 D0 - D7 V DD EA PSEN CS OE MCS03880 Figure 10-9 OTP Verification Mode - External Circuitry Example User’s Manual 10-14 10.99 Index C505L 11 Index A/D converter . . . . . . . . . . . . . . . 6-80–6-92 Analog input pin selection . . . . . . . . 6-92 Block diagram . . . . . . . . . . . . . . . . . 6-81 Calibration mechanisms . . . . . . . . . 6-91 Clock selection . . . . . . . . . . . . . . . . . 6-86 Conversion time calculation . . . . . . . 6-89 Conversion timing . . . . . . . . . . . . . . 6-87 General operation . . . . . . . . . . . . . . 6-80 Registers . . . . . . . . . . . . . . . . . 6-82–6-86 System clock relationship . . . . . . . . 6-88 AC . . . . . . . . . . . . . . . . . . . . . . . . .2-4, 3-16 ACC . . . . . . . . . . . . . . . . . . . 2-3, 3-12, 3-17 ADCL1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 ADCON0 . . . . . . . . . . 3-13, 3-16, 5-8, 6-48 ADCON02 . . . . . . . . . . . . . . . . . . . . . . 3-12 ADCON1 . . . . . . . . . . . . . . . . . . . 3-12, 3-17 ADDATH . . . . . . . . . . . . . . . . . . . 3-12, 3-16 ADDATL . . . . . . . . . . . . . . . . . . . 3-12, 3-16 ADM . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 ALE signal . . . . . . . . . . . . . . . . . . . . . . . 4-4 A COCAH2 . . . . . . . . . . . . . . . . . . . . . . . .3-16 COCAH3 . . . . . . . . . . . . . . . . . . . . . . . .3-16 COCAL0 . . . . . . . . . . . . . . . . . . . . . . . .3-16 COCAL1 . . . . . . . . . . . . . . . . . . . . . . . .3-16 COCAL2 . . . . . . . . . . . . . . . . . . . . . . . .3-16 COCAL3 . . . . . . . . . . . . . . . . . . . . . . . .3-16 CPU Accumulator . . . . . . . . . . . . . . . . . . . .2-3 B register . . . . . . . . . . . . . . . . . . . . . . .2-4 Basic timing . . . . . . . . . . . . . . . . . . . . .2-5 Fetch/execute diagram . . . . . . . . . . . .2-6 Functionality . . . . . . . . . . . . . . . . . . . .2-3 Program status word . . . . . . . . . . . . . .2-3 Stack pointer . . . . . . . . . . . . . . . . . . . .2-4 CPU timing . . . . . . . . . . . . . . . . . . . . . . .2-6 CRCH . . . . . . . . . . . . . . . . . . . . . . . . . .3-13 CRCL . . . . . . . . . . . . . . . . . . . . . . . . . .3-13 CY . . . . . . . . . . . . . . . . . . . . . . . . . 2-4, 3-16 D DAC0 . . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 Datapointers . . . . . . . . . . . . . . . . . . 4-6–4-9 Application examples . . . . . . . . . 4-7–4-9 DPSEL register . . . . . . . . . . . . . . . . . .4-6 Functionality . . . . . . . . . . . . . . . . . . . .4-6 DIGn1 . . . . . . . . . . . . . . . . . . . . . . . . . .3-18 DIGn5 . . . . . . . . . . . . . . . . . . . . . . . . . .3-14 DPH . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-15 DPL . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-15 DPSEL . . . . . . . . . . . . . . . . . . . . 3-12, 3-15 B B . . . . . . . . . . . . . . . . . . . . . 2-4, 3-12, 3-17 Basic CPU timing . . . . . . . . . . . . . . . . . 2-5 BD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Block diagram . . . . . . . . . . . . . . . . . . . . 2-2 BSY . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 C C/T . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 CCEN . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCH1 . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCH2 . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCH3 . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCL1 . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCL2 . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CCL3 . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 CLKOUT . . . . . . . . . . . . . . . . . . . . . . . 3-15 CLREG0 . . . . . . . . . . . . . . . . . . . 3-14, 3-18 CLREG1 . . . . . . . . . . . . . . . . . . . 3-14, 3-18 CLREG2 . . . . . . . . . . . . . . . . . . . 3-14, 3-18 CLREG3 . . . . . . . . . . . . . . . . . . . 3-14, 3-18 CLREG4 . . . . . . . . . . . . . . . . . . . 3-14, 3-18 COCAH0 . . . . . . . . . . . . . . . . . . . . . . . 3-16 COCAH1 . . . . . . . . . . . . . . . . . . . . . . . 3-16 E EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 EADC . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-6 EALE . . . . . . . . . . . . . . . . . . . . . . . 1-8, 3-16 EAN0 . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 EAN1 . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 EAN2 . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 EAN3 . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 EAN4 . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 EAN5 . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 EAN6 . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 EAN7 . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 EAN7-0 . . . . . . . . . . . . . . . . . . . . . . . . .6-92 Emulation concept . . . . . . . . . . . . . . . . .4-5 ERTC . . . . . . . . . . . . . . . . . . . . . . . . . .3-18 ES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 ESWI . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-6 ET0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 10.99 User’s Manual 11-1 Index C505L ET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 ET2 . . . . . . . . . . . . . . . . . . . . . . . .3-15, 7-5 EWPD . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 EX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 EX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 EX3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 EX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 EX5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 EX6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Execution of instructions . . . . . . . . . . . . 2-6 EXEN2 . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-6 EXF2 . . . . . . . . . . . . . . . . . . . . . . .3-16, 7-9 External bus interface . . . . . . . . . . . . . . 4-1 ALE signal . . . . . . . . . . . . . . . . . . . . . 4-4 ALE switch-off control . . . . . . . . . . . . 4-4 Overlapping of data/program memory 4-3 Program memory access . . . . . . . . . . 4-3 Program/data memory timing . . . . . . 4-2 PSEN signal . . . . . . . . . . . . . . . . . . . . 4-3 Role of P0 and P2 . . . . . . . . . . . . . . . 4-1 F F0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Fail save mechanisms . . . . . . . . . . .8-1–8-8 Fast power-on reset . . . . . . . . . . . .5-3, 8-8 Features . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Functional units . . . . . . . . . . . . . . . . . . . 1-1 Fundamental structure . . . . . . . . . . . . . 2-1 IEN12 . . . . . . . . . . . . . . . . . . . . . 3-12, 3-13 IEX3 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 IEX4 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 IEX5 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 IEX6 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 INT1 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 INT4 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 INT5 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 Interrupt system . . . . . . . . . . . . . . 7-1–7-17 Interrupts Block diagram . . . . . . . . . . . . . . . 7-2–7-4 Enable registers . . . . . . . . . . . . . 7-5–7-9 External interrupts . . . . . . . . . . . . . . .7-16 Handling procedure . . . . . . . . . . . . . .7-14 Priority registers . . . . . . . . . . . . . . . .7-12 Priority within level structure . . . . . . .7-13 Request flags . . . . . . . . . . . . . . 7-7–7-11 Response time . . . . . . . . . . . . . . . . .7-17 Sources and vector addresses . . . . .7-15 Introduction . . . . . . . . . . . . . . . . . . . . . . .1-1 IP0 . . . . . . . . . . . . . . . . . . . . 3-15, 8-3, 8-6 IP02 . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-13 IP1 . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-16 IRCON . . . . . . . . . . . 3-12, 3-16, 6-31, 6-85 IRTC . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18 IT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 IT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 G GATE . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 GF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 GF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 L LCD Controller . . . . . . . . . . . . . . 6-62–6-72 Clocking . . . . . . . . . . . . . . . . . 6-65–6-66 Block Diagram . . . . . . . . . . . . . . . .6-66 Frequency . . . . . . . . . . . . . . . . . . .6-65 Column singals . . . . . . . . . . . . . . . . .6-68 Display voltage . . . . . . . . . . . . . . . . .6-72 D/A Converter . . . . . . . . . . . . . . . .6-72 LCD Cell Organization . . . . . . . . . . .6-62 Power Saving Mode . . . . . . . . . . . . .6-72 Registers . . . . . . . . . . . . . . . . . . . . . .6-63 Control register . . . . . . . . . . . . . . .6-63 Digit registers . . . . . . . . . . . . . . . . .6-64 Row signals . . . . . . . . . . . . . . . . . . . .6-67 LCD Controller/RTC Access control . . . . . . . . . . . . . . . . . . .3-3 LCON . . . . . . . . . . . . . . . . . 3-14, 3-18, 9-2 LCRH . . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 LCRL . . . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 H Hardware reset . . . . . . . . . . . . . . . . . . . 5-1 I I/O ports . . . . . . . . . . . . . . . . . . . . .6-1–6-17 I3FR . . . . . . . . . . . . . . . . . . . . . . . .3-16, 7-8 IADC . . . . . . . . . . . . . . . . . . 3-16, 6-85, 7-9 IDLE . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Idle mode . . . . . . . . . . . . . . . . . . . . .9-4–9-5 IDLS . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 IE0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 IE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 IEN0 . . . . . . . . . . . . . . . . . . 3-15, 6-31, 8-3 IEN02 . . . . . . . . . . . . . . . . . . . . . 3-12, 3-13 IEN1 . . . . . . . . . . . . . 3-16, 6-31, 6-85, 8-3 User’s Manual 11-2 10.99 Index C505L Logic symbol . . . . . . . . . . . . . . . . . . . . . 1-3 M M0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 M1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Memory organization . . . . . . . . . . . . . . . 3-1 Data memory . . . . . . . . . . . . . . . . . . . 3-2 General purpose registers . . . . . . . . . 3-2 Memory map . . . . . . . . . . . . . . . . . . . 3-1 Program memory . . . . . . . . . . . . . . . . 3-2 MX0 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 3-17 MX1 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 3-17 MX2 . . . . . . . . . . . . . . . . . . . . . . . 3-16, 3-17 O Oscillator operation . . . . . . . . . . . . .5-6–5-7 External clock source . . . . . . . . . . . . . 5-7 On-chip oscillator circuitry . . . . . . . . . 5-7 Recommended oscillator circuit . . . . . 5-6 Oscillator watchdog . . . . . . . . . . . . .8-6–8-8 Behaviour at reset . . . . . . . . . . . . . . . 5-3 Block diagram . . . . . . . . . . . . . . . . . . 8-7 OTP memory . . . . . . . . . . . . . . . 10-1–10-14 Access of Version Bytes . . . . . . . . 10-11 Basic Mode Selection . . . . . . . . . . . 10-5 Pin Configuration . . . . . . . . . . . . . . . 10-1 Program/read operation . . . . . . . . . . 10-7 Verification example . . . . . . . . . . . 10-14 Verification Mode . . . . . . . . . . . . . . 10-12 Verification mode timing . . . . . . . . 10-12 OV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 OWDS . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Pin Definitions and functions (OTP Mode) . . . . . . . . . . . . . . 10-3–10-4 Ports . . . . . . . . . . . . . . . . . . . . . . . 6-1–6-17 Alternate functions . . . . . . . . . . . . . . .6-3 Loading and interfacing . . . . . . . . . . .6-16 Output drivers circuitry . . . . . . . . . . .6-10 Mixed digital/analog I/O pins . . . . .6-12 Multifunctional digital I/O pins . . . .6-10 Output/input sample timing . . . . . . . .6-15 Read-modify-write operation . . . . . . .6-17 Types and structures . . . . . . . . . . . . . .6-1 Port 0 circuitry . . . . . . . . . . . . . . . . .6-6 Port 1/3/4 circuitry . . . . . . . . . . . . . .6-7 Port 2 circuitry . . . . . . . . . . . . . . . . .6-8 Standard I/O port circuitry . . . . 6-4–6-5 Power saving modes . . . . . . . . . . 9-1–9-12 Control registers . . . . . . . . . . . . . 9-1–9-3 Idle mode . . . . . . . . . . . . . . . . . . 9-4–9-5 Slow down mode . . . . . . . . . . . . . . . . .9-6 Software power down mode Entry procedure . . . . . . . . . . . . . . . .9-8 Exit (wake-up) procedure . . . . . . . .9-9 Software power down modes . . 9-7–9-11 State of pins . . . . . . . . . . . . . . . . . . .9-12 PSEN signal . . . . . . . . . . . . . . . . . . . . . .4-3 PSW . . . . . . . . . . . . . . . . . . 2-3, 3-12, 3-16 R RB8 . . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-46 RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 Real-Time Clock . . . . . . . . . . . . . 6-73–6-79 Control Register . . . . . . . . . . . . . . . .6-74 Functionality . . . . . . . . . . . . . . . . . . .6-77 Oscillator . . . . . . . . . . . . . . . . . . . . . .6-73 Wake-up interrupt . . . . . . . . . . . . . . .6-78 REN . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Fast power-on reset . . . . . . . . . . . . . .5-3 Hardware reset timing . . . . . . . . . . . . .5-5 Power-on reset timing . . . . . . . . . . . . .5-4 Reset circuitries . . . . . . . . . . . . . . . . . .5-2 RI . . . . . . . . . . . . . . . . . . . 3-15, 6-46, 7-11 RMAP . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 RS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 RS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 RTCON . . . . . . . . . . . . . . . . 3-14, 3-18, 9-2 RTCR0 . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 RTCR1 . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 P P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 P0 . . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-15 P1 . . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-15 P1ANA . . . . . . . . . . . . . . . . . 3-12, 3-15, 6-2 P2 . . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-15 P3 . . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-16 P4 . . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-17 P5 . . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-17 Parallel I/O . . . . . . . . . . . . . . . . . . .6-1–6-17 PCON . . . . . . . . . . . . . . . . 3-13, 3-15, 6-48 PCON1 . . . . . . . . . . . . . . . . . . . . 3-13, 3-15 PDE . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 PDS . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Pin Configuration . . . . . . . . . . . . . . . . . . 1-4 Pin Definitions and functions . . . . . . . . . 1-5 User’s Manual 11-3 10.99 Index C505L RTCR2 . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 RTCR3 . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 RTCR4 . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 RTCS . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 RTINT0 . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 RTINT1 . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 RTINT2 . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 RTINT3 . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 RTINT4 . . . . . . . . . . . . . . . . . . . . 3-14, 3-18 RTPD . . . . . . . . . . . . . . . . . . . . . . .3-18, 9-2 RxD . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 S SBUF . . . . . . . . . . . . . . . . . 3-13, 3-15, 6-46 SCON . . . . . . . . . . . 3-13, 3-15, 6-46, 7-11 SCON2 . . . . . . . . . . . . . . . . . . . . . . . . 3-12 SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Serial interface (USART) . . . . . . . 6-45–6-61 Baudrate generation . . . . . . . . . . . . 6-48 with internal baud rate generator . 6-50 with timer 1 . . . . . . . . . . . . . . . . . . 6-52 Multiprocessor communication . . . . 6-46 Operating mode 0 . . . . . . . . . . 6-53–6-55 Operating mode 1 . . . . . . . . . . 6-56–6-58 Operating mode 2 and 3 . . . . . 6-59–6-61 Registers . . . . . . . . . . . . . . . . . . . . . 6-46 SM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 SM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 SM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 SMOD . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 SP . . . . . . . . . . . . . . . . . . . . 2-4, 3-12, 3-15 Special Function Registers . . . . . . . . . 3-11 Access with RMAP . . . . . . . . . . . . . 3-11 Table - address ordered . . . . . 3-15–3-18 Table - functional order . . . . . . 3-12–3-14 SRELH . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 SRELL . . . . . . . . . . . . . . . . . . . . . 3-13, 3-15 SWDT . . . . . . . . . . . . . . . . . . . . . . 3-16, 8-3 SWI . . . . . . . . . . . . . . . . . . . . . . . .3-16, 7-9 SYSCON . . . . . . . 3-3, 3-11, 3-12, 3-16, 4-4 System clock output . . . . . . . . . . . .5-8–5-9 T T0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 T2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 T2CM . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 T2CON . . . . . . . . . . . . . . . . 3-13, 3-16, 7-8 T2CON2 . . . . . . . . . . . . . . . . . . . . . . . 3-12 User’s Manual T2EX . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 T2I0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 T2I1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 T2PS . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 T2R0 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 T2R1 . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 TB8 . . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-46 TCON . . . . . . . . . . . . . . . . . 3-13, 3-15, 7-7 TCON2 . . . . . . . . . . . . . . . . . . . . . . . . .3-12 TF0 . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-7 TF1 . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 7-7 TF2 . . . . . . . . . . . . . . . . . . . . . . . . 3-16, 7-9 TH0 . . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-15 TH1 . . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-15 TH2 . . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 TI . . . . . . . . . . . . . . . . . . . . 3-15, 6-46, 7-11 Timer/counter . . . . . . . . . . . . . . . . . . . .6-18 Timer/counter 0 and 1 . . . . . . . 6-18–6-25 Mode 0, 13-bit timer/counter . . . . .6-22 Mode 1, 16-bit timer/counter . . . . .6-23 Mode 2, 8-bit rel. timer/counter . . .6-24 Mode 3, two 8-bit timer/counter . . .6-25 Registers . . . . . . . . . . . . . . . 6-19–6-21 Timer/counter 2 . . . . . . . . . . . . 6-26–6-45 Block diagram . . . . . . . . . . . . . . . .6-27 Capture function . . . . . . . . . 6-43–6-45 Compare function . . . . . . . . 6-35–6-40 Compare mode 0 . . . . . . . . . 6-35–6-38 Compare mode 1 . . . . . . . . . 6-39–6-40 Compare mode interrupts . . . . . . .6-41 General operation . . . . . . . . . . . . .6-33 Port functions . . . . . . . . . . . . . . . . .6-26 Registers . . . . . . . . . . . . . . . 6-28–6-32 Reload configuration . . . . . . . . . . .6-34 TL0 . . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-15 TL1 . . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-15 TL2 . . . . . . . . . . . . . . . . . . . . . . . 3-13, 3-16 TMOD . . . . . . . . . . . . . . . . . . . . . 3-13, 3-15 TR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 TR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 TxD . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 V VR0 . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-17 VR1 . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-17 VR2 . . . . . . . . . . . . . . . . . . . . . . . 3-12, 3-17 W Watchdog timer . . . . . . . . . . . . . . . . 8-1–8-5 10.99 11-4 Index C505L Block diagram . . . . . . . . . . . . . . . . . . 8-1 Control/status flags . . . . . . . . . . . . . . 8-3 Input clock selection . . . . . . . . . . . . . 8-2 Refreshing of the WDT . . . . . . . . . . . 8-5 Reset operation . . . . . . . . . . . . . . . . . 8-5 Starting of the WDT . . . . . . . . . . . . . . 8-4 Time-out periods . . . . . . . . . . . . . . . . 8-2 WDT . . . . . . . . . . . . . . . . . . . . . . .3-15, 8-3 WDTPSEL . . . . . . . . . . . . . . . . . . . . . . 3-15 WDTREL . . . . . . . . . . . . . . . . . . . 3-13, 3-15 WDTS . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 WR . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 WS . . . . . . . . . . . . . . . . . . . . . . . . .3-15, 9-3 X XMAP0 . . . . . . . . . . . . . . . . . . . . . . . . 3-16 XMAP1 . . . . . . . . . . . . . . . . . . . . . . . . 3-16 XPAGE . . . . . . . . . . . . . . . . . . . . 3-12, 3-15 XRAM operation . . . . . . . . . . . . . . . . . . 3-3 Access control . . . . . . . . . . . . . . . . . . 3-3 Accessing through DPTR . . . . . . . . . 3-5 Accessing through R0/R1 . . . . . . . . . 3-5 Behaviour of P2/P0 . . . . . . . . . . . . . . 3-9 Reset operation . . . . . . . . . . . . . . . . . 3-9 XPAGE register . . . . . . . . . . . . . . . . . 3-5 Use of P2 as I/O port . . . . . . . . . . . 3-8 Write page address to P2 . . . . . . . . 3-6 Write page address to XPAGE . . . . 3-7 User’s Manual 11-5 10.99 Infineon goes for Business Excellence “Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG