C868-1S

User’s M anual, V 0.4, Jan. 2002 C868 8 - Bit CMOS Microcontroller M i c r o c o n t ro l le r s Never stop thinking. Edition 2002-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2002. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. User ’ s M a n u a l , V 0. 4 , J a n . 2 0 0 2 C868 8 - B i t C M O S M ic r o co n t ro l l e r M i c r o c o n t ro l le r s Never stop thinking. C868 Revision History: Previous Version: Page 2002-01 V 0.4 Subjects (major changes since last revision) Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com C868 1 1.1 1.2 1.3 2 2.1 2.2 3 3.1 3.2 3.2.1 3.3 3.3.1 3.3.2 3.3.2.1 3.3.2.2 3.3.2.3 3.3.2.4 3.4 4 4.1 4.2 4.2.1 4.3 4.4 4.4.1 4.5 4.5.1 4.5.1.1 4.5.1.2 4.5.1.3 4.5.1.4 4.5.1.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.5.1 4.6.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-4 1-5 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Memory, “Code Space” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Memory, “Data Space” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program and Data Memory Organisation . . . . . . . . . . . . . . . . . . . . . . . . Special function register SYSCON1 . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XRAM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-2 3-2 3-3 3-3 3-5 3-6 3-6 3-6 3-8 3-9 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Dedicated Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Port 1, Port 3 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Read-Modify-Write Feature of Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Timer 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Timer 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Functional Description of Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . 4-19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 Auto-Reload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 Up/Down Count Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 Up/Down Count Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 -1 V 0.4, 2002-01 User’s Manual C868 4.6.6 4.6.7 4.6.8 4.6.9 4.7 4.7.1 4.7.1.1 4.7.1.2 4.7.1.3 4.7.1.4 4.7.1.5 4.7.1.6 4.7.1.7 4.7.1.8 4.7.1.9 4.7.1.10 4.7.1.11 4.7.2 4.7.2.1 4.7.2.2 4.7.2.3 4.7.2.4 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.4.1 4.8.4.2 4.9 4.9.1 4.9.1.1 4.9.1.2 4.9.2 4.9.3 4.10 4.10.1 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 Baudrate Generator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 Count Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Module Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Capture/Compare Unit (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 Timer T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 Counting Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 Switching Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 Duty Cycle of 0% and 100% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 Compare Mode of T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 Switching Examples in edge-aligned Mode . . . . . . . . . . . . . . . . . . 4-40 Switching Examples in center-aligned Mode . . . . . . . . . . . . . . . . . 4-40 Dead-time Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43 Single Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44 Hysteresis-Like Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46 Timer T13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48 Single Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 Synchronization of T13 to T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 Multi-channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50 Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 Hall Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58 Module Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58 Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59 Timer12 - Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59 Timer13 - Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66 Modulation Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82 Global Module Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82 Multi-Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-100 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-103 Baud Rate in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104 Baud Rate in Mode 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-106 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-110 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114 Register Definition of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-115 -2 V 0.4, 2002-01 User’s Manual C868 4.10.2 4.10.3 4.10.4 4.11 4.11.1 5 5.1 5.2 5.3 5.4 5.5 5.5.1 5.5.2 5.5.3 5.6 5.6.1 5.7 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 8.5 8.5.1 ................................................... Operation of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Module Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion and Sample Time Control . . . . . . . . . . . . . . . . . . . . . . . . . A/D Converter Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-117 4-118 4-118 4-119 4-121 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 VCO Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 K-Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Determining the PLL Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Slow Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Switching Between PLL Clock and SDD Clock . . . . . . . . . . . . . . . . . . 5-8 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Fail Save Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Definition of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clock Selection .................................... 6-1 6-1 6-1 6-5 6-5 6-6 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Structure of the Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Interrupt Request Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Interrupt Control Registers for CCU6 . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Mode Control Registers ........................ Register Description ..................................... Idle Mode ............................................... Slow Down Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exit from Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-2 8-4 8-5 8-6 8-6 User’s Manual -3 V 0.4, 2002-01 C868 User’s Manual -4 V 0.4, 2002-01 C868 Introduction 1 Introduction The C868 is a member of the Infineon Technologies C800 family of 8-bit microcontrollers. It is fully compatible to the standard 8051 microcontroller. Its features include the capture compare unit (CCU6) which is useful in motor control applications, extended power saving provisions, on-chip RAM and RFI related improvements. The C868 has a maximum CPU clock rate of 40MHz. At 40MHz it achieves a 300ns instruction cycle time. The C868 basically operates with internal program memory only. The C868-1R contains 8K x 8 on-chip ROM of program memory and the C868-1S contains 8K x 8 of on-chip RAM of program memory. Different operating modes are provided to allow flexibility in the access of the different types of memory. An additional RAM, XRAM, is provided for the implementation of in-system programming. Figure 1-1 shows the different functional units of the C868 and Figure 1-2 shows the simplified logic symbol of the C868. RAM 256Ω 8 Timer 0 Timer 1 8-bit UART Timer 2 Port 1 I/O 5-bit XRAM 256 Ω8 CPU 8 datapointers ROM/RAM 8K Ω 8 16-bit Capture/ Compare Unit 16-bit Compare Unit Port 3 I/O 8-bit Boot ROM 4K x 8 Watchdog Timer 8-Bit ADC Analog/ Digital Input Figure 1-1 C868 Functional Units User’s Manual 1-1 V 0.4, 2002-01 C868 Introduction 1.1 Summary of Basic Features Listed below is a summary of the main features of the C868: • C800 core : –Fully compatible to standard 8051 microcontroller –Superset of the 8051 architecture with 8 datapointers • 6.25 - 40 MHz internal system clock (built-in PLL with software configurable divider) –external clock of 6.67 - 10.67 MHz –300ns instruction cycle time (@40 MHz system clock) • 8 Kbyte on-chip Program ROM for C868-1R and 8 KByte on-chip Program RAM for C868-1S • In-system programming support for programming the XRAM(C868-1R) or XRAM/ Program RAM(C868-1S) –This feature is realized through 4KB Boot ROM • 256 byte on-chip RAM • 256 byte on-chip XRAM • One 8-bit and one 5 bits general purpose push-pull I/O ports – Enhanced sink current of 10 mA on Port 1/3 (total sink current of 46 mA @ 100oC) • Three 16-bit timers/counters –Timer 0 / 1 –Timer/counter 2 (up/down counter feature) –Timer 1 or 2 can be used for serial baudrate generator • Capture/compare unit (CCU6) for PWM signal generation –3-channel, 16-bit capture/compare unit –1-channel, 16-bit compare unit • Full duplex serial interface (UART) • 5 channel 8-bit A/D Converter • 13 interrupt vectors with 2 priority levels • Programmable 16-bit Watchdog Timer • Brown out detection • Power Saving Modes –Slow-down mode –Idle mode (can be combined with slow-down mode) –Power-down mode with wake up capability through INT0 or RxD pins. • Individual power-down control for timer/counter 2, capture/compare unit and A/D converter. • P-DSO-28-1, P-TSSOP-38-1 packages • Temperature ranges: SAB-C868-1RR,SAB-C868-1SR,SAB-C868-1RG,SAB-C868-1SG TA = 0 to 70 oC SAF-C868-1RR,SAF-C868-1SR,SAF-C868-1RG,SAF-C868-1SG TA = – 40 to 85 oC User’s Manual 1-2 V 0.4, 2002-01 C868 Introduction VDDP VSSP VAREF VAGND Port 1 5-bit Digital I/O Port 3 8-bit Digital I/O C868 5 ADC channels RESET ALE/BSL CTRAP TxD RxD 4 External Interrupts VDDC VSSC Figure 1-2 Logic Symbol User’s Manual 1-3 V 0.4, 2002-01 C868 Introduction 1.2 Pin Configuration P1.4/RxD P1.3/INT3 P1.2 P1.1/EXF2 1 2 3 38 37 36 35 34 33 32 31 RESET 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 NC P1.0/TxD P3.7/CC60 P3.6/COUT60 NC ALE/BSL P3.1/CTRAP P3.0/COUT63 NC NC VDDP VSSP P3.4/COUT61 XTAL2 XTAL1 C868 30 29 28 27 26 25 24 23 22 21 20 CCPOS0/T2/INT0/AN0 CCPOS1/T2EX/INT1/AN1 VDDC CCPOS2/INT2/AN2 VAGND VAREF VSSC P3.3/CC62 P3.2/COUT62 P3.5/CC61 AN3 AN4 NC NC NC NC NC NC Figure 1-3 C868 Pin Configuration P-TSSOP-38 Package (top view) P3.4/COUT61 P3.0/COUT63 P3.1/CTRAP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 XTAL2 XTAL1 ALE/BSL P3.6/COUT60 P3.7/CC60 RESET P1.4/RxD P1.3/INT3 P1.2 P1.1/EXF2 P1.0/TxD VDDP VSSP VDDC VSSC P3.3/CC62 P3.2/COUT62 P3.5/CC61 AN4 AN3 VAREF C868 22 21 20 19 18 17 16 15 VAGND CCPOS2/INT2/AN2 CCPOS1/T2EX/INT1/AN1 CCPOS0/T2/INT0/AN0 Figure 1-4 User’s Manual C88 Pin Configuration P-DSO-28 Package (top view) 1-4 V 0.4, 2002-01 C868 Introduction 1.3 Table 1-1 Symbol Pin Definitions and Functions Pin Definitions and Functions Pin Numbers PDSO28 PTSSOP38 6,4-1 I/O Port 1 is a 5-bit push-pull bidirectional I/O port. As alternate digital functions, port 1 contains the interrupt 3, timer 2 overflow flag, receive data input and transmit data output of serial interface. The alternate functions are assigned to the pins of port 1 as follows: P1.0/TxD Transmit data of serial interface P1.1/EXF2 Timer 2 overflow flag P1.2 P1.3/INT3 Interrupt 3 P1.4/RxD Receive data of serial interface Port 3 is an 8-bit push-pull bidirectional I/O port. This port also serves as alternate functions for the CCU6 functions. The functions are assigned to the pins of port 3 as follows : P3.0/COUT63 16 bit compare channel output P3.1/CTRAP CCU trap input P3.2/COUT62 Output of capture/compare ch 2 P3.3/CC62 Input/output of capture/compare ch 2 P3.4/COUT61 Output of capture/compare ch 1 P3.5/CC61 Input/output of capture/compare ch 1 P3.6/COUT60 Output of capture/compare ch 0 P3.7/CC60 Input/output of capture/compare ch 0 – – Reference voltage for the A/D converter. Reference ground for the A/D converter. I/O*) Function This section describes all external signals of the C868 with its function. P1.0– P1.4 12-8 12 11 10 9 8 P3.0– P3.7 6 4 3 2 1 2,3,23, 32,33,25, I/O 24,1, 26,31,24, 22,5,6 36,37 2 3 23 24 1 22 5 6 VAREF VAGND *)I=Input O=Output 19 18 32 33 25 26 31 24 36 37 15 14 User’s Manual 1-5 V 0.4, 2002-01 C868 Introduction Table 1-1 Symbol Pin Definitions and Functions Pin Numbers PDSO28 AN4 AN3 21 20 PTSSOP38 17 16 13 I I I Analog Input Channel 4 is input channel 4 to the ADC unit. Analog Input Channel 3 is input channel 3 to the ADC unit. External Interrupt 2 Input/ Analog Input Channel 2 Multiplexed external interrupt input or Hall input signal and input channel 2 to the ADC unit. Timer 2 Trigger/External Interrupt 1 Input/ Analog Input Channel 1/ Multiplexed external interrupt input or Hall input signal, input channel 1 to the ADC unit, trigger to Timer 2. Input to Counter 2/External Interrupt 0 Input/ Analog Input Channel 0 Multiplexed external interrupt input or Hall input signal, counter 2 input or input channel 0 to the ADC unit. RESET A low level on this pin for two machine cycle while the oscillator is running resets the device. Address Latch Enable/Bootstrap Mode A high level on this pin during reset allows the device to go into the bootstrap mode. After reset, this pin will output the address latch enable signal. The ALE can be disabled by bit EALE in SFR SYSCON0. IO Ground (0V) IO Power Supply (+3.3V) Core Ground (0V) Core Power Supply (+2.5V) I/O*) Function CCPOS0/ 17 INT2/AN2 CCPOS1/ 16 T2EX/ INT1/AN1 12 I CCPOS0/ 15 T2/INT0/ AN0 11 I RESET 7 38 I ALE/BSL 4 34 I/O VSSP VDDP VSSC VDDC *)I=Input O=Output 14 13 25 26 10 9 27 28 – – – – User’s Manual 1-6 V 0.4, 2002-01 C868 Introduction Table 1-1 Symbol Pin Definitions and Functions Pin Numbers PDSO28 NC – PTSSOP38 5,7,8,18, – 1920,21, 22,23,35 29 30 I O Not connected I/O*) Function XTAL1 XTAL2 27 28 XTAL1 Output of the inverting oscillator amplifier. XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generation circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. *)I=Input O=Output User’s Manual 1-7 V 0.4, 2002-01 C868 Introduction User’s Manual 1-8 V 0.4, 2002-01 C868 Fundamental Structure 2 Fundamental Structure The C868 is fully compatible to the architecture of the standard 8051 microcontroller family. While maintaining all architectural and operational characteristics of the 8051, the C868 incorporates a CPU with 8 datapointers, a 8-bit A/D converter, a 16-bit capture/ compare unit, a 16 bit timer 2 that can be used as baudrate generator, an interrupt structure with 2 priority levels, built-in PLL with a fixed factor of 15 and a variable divider, an XRAM data memory as well as some enhancements in the Fail Save Mechanism Unit. Figure 2-1 shows a block diagram of the C868. User’s Manual 2-1 V 0.4, 2002-01 C868 Fundamental Structure VDDC VSSC XTAL1 XTAL2 PLL 256 x 8 256 x 8 C868 OSC XRAM RAM ROM/ RAM 8k x 8 Boot/ Self Test ROM 4k x 8 RESET CPU 8 datapointers Port 1 5-bit digital I/O Programmable Watchdog Timer Timer 0 Timer 1 Timer 2 Port 1 UART Port 3 Capture/Compare Unit 4 external interrupts VAREF VAGND 5-Bit Analog In Port 3 8-bit digital I/O Interrupt Unit VDDP A/D Converter 8-Bit VSSP Figure 2-1 Block Diagram of the C868 User’s Manual 2-2 V 0.4, 2002-01 C868 Fundamental Structure 2.1 CPU The C868 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 10.67 MHz external crystal (giving a 40MHz CPU clock), 58% of the instructions execute in 300 ns. The CPU (Central Processing Unit) of the C868 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. These internal signals have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BCD-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set-andclear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, the ALU can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Additionally to the CPU functionality of the 8051 standard microcontroller, the C868 contains 8 datapointers. For complex applications with peripherals located in the external data memory space or extended data storage capacity, this turned out to be a "bottle neck" for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. Accumulator ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. User’s Manual 2-3 V 0.4, 2002-01 C868 Fundamental Structure PSW Program Status Word Register D7H CY rwh D6H AC rwh D5H F0 rw D4H RS1 rw D3H RS0 rw D2H OV rwh [Reset value: 00H] D1H F1 rw D0H P rwh Field P Bits 0 Typ Description rwh Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. rw General Purpose Flag rwh Overflow Flag Used by arithmetic instructions. rw Register Bank select control bits These bits are used to select one of the four register banks. Table 1 : RS1 RS0 Function 0 0 1 1 0 1 0 1 Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH F1 OV RS0 RS1 1 2 3 4 F0 AC CY 5 6 7 rw General Purpose Flag rwh Auxiliary Carry Flag Used by instructions which execute BCD operations. rwh Carry Flag Used by arithmetic instructions. User’s Manual 2-4 V 0.4, 2002-01 C868 Fundamental Structure B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. User’s Manual 2-5 V 0.4, 2002-01 C868 Fundamental Structure 2.2 CPU Timing A machine cycle of the C868 consists of 6 states (12 system clock periods). Each state is divided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 12 internal clock periods, numbered S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts two internal clock periods. Typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in Figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figure 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most C868 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-2 (c) and (d) show the timing for a normal 1-byte, 2cycle instruction and for a MOVX instruction. User’s Manual 2-6 V 0.4, 2002-01 C868 Fundamental Structure S1 S2 S1 S2 S3 S4 S5 S6 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 fSYS ALE Read Opcode Read Next Opcode (Discard) Read Next Opcode Again S1 S2 S3 S4 S5 S6 (a) 1-Byte, 1-Cycle Instruction, e.g. INC A Read Opcode Read 2nd Byte Read Next Opcode S1 S2 S3 S4 S5 S6 (b) 2 Byte, 1-Cycle Instruction, e.g. ADD A #Data Read Opcode Read Next Opcode Again Read Next Opcode (Discard) S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 (c) 1-Byte, 2-Cycle Instruction, e.g. INC DPTR Read Opcode (MOVX) S1 S2 S3 S4 Read Next Opcode (Discard) S5 S6 S1 Read Next Opcode Again No No Fetch Fetch No ALE S2 DATA S3 S4 S5 S6 (d) MOVX (1-Byte, 2-Cycle) ADDR Access of External Memory Figure 2-2 Fetch Execute Sequence User’s Manual 2-7 V 0.4, 2002-01 C868 Fundamental Structure User’s Manual 2-8 V 0.4, 2002-01 C868 Memory Organization 3 Memory Organization – up to 8 Kbyte of RAM internal program memory : 8K ROM for C868-1R : 8K RAM for C868-1S – – – – 4 Kbyte of internal Self test and Boot ROM 256 bytes of internal data memory 256 bytes of internal XRAM data memory 128 byte special function register area The C868 CPU manipulates operands in the following five address spaces: Figure 3-1 illustrates the memory address spaces of the C868. Internal XRAM FFFFH FF00H 1FFFH indirect addr. Internal RAM direct addr. Special FFH Function Regs. 80H Internal RAM 7FH 00H Internal Internal Self Test and Boot ROM (4 KByte) 0000H "Data Space" "Code Space" "Internal Data Space" Figure 3-1 C868 Memory Map The internal Self Test and Boot ROM overlaps the internal program memory in the address range from 0000H to 0FFFH. Depending on the selected operating mode (chipmode), either internal program memory or the internal Self Test and Boot ROM is accessed in this address range. User’s Manual 3-1 V 0.4, 2002-01 C868 Memory Organization 3.1 Program Memory, “Code Space” The C868-1S has 8 Kbytes of random access program memory (RAM) and 4 Kbytes of Boot and Self Test ROM. In the normal mode the C868-1S executes program code out of the internal RAM. The Boot ROM includes a bootstrap loader program for the bootstrap loader of the C8681S. The software routines of the bootstrap loader program allow the easy and quick programming or loading of the internal program RAM via the serial interface while the MCU is in-circuit. The C868-1R has 8Kbytes of ROM and 4 Kbytes of Self Test ROM. The Self Test ROM has a self test program for the self test mode of the C868. 3.2 Data Memory, “Data Space” The data memory address space consists of an internal and an external(XRAM) memory space. The internal data memory is divided into three physically separate and distinct blocks: the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing only; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 00H through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. The internal XRAM is located in the in the external data memory area and must be accessed by external data memory instructions (MOVX). 3.2.1 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 and RS1, select the active register bank. This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction opcode indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). User’s Manual 3-2 V 0.4, 2002-01 C868 Memory Organization Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. 3.3 Program and Data Memory Organisation The C868 can operate in four different operating modes (chipmodes) with different program and data memory organisations: – – – – Normal Mode Normal XRAM Mode Bootstrap Mode Bootstrap XRAM Mode 3.3.1 Special function register SYSCON1 There are four control bits located in SFR SYSCON1 which control the code and data memory organisation of the C868. Two of these bits (BSLEN and SWAP) cannot be programmed as normal bits but with a special software unlock sequence. The special software unlock sequence was implemented to prevent unintentional changing of these bits and consists of consecutive followed instructions which have to set set two dedicated enable bits. SYSCON1 System Control Register 1 7 ESWC w 6 SWC w 5 r 4 r 3 r [Reset value: 00XXX0X0B] 2 BSLEN rw 1 r 0 SWAP rw Field SWAP Bits 0 Typ Description rw SWAP Code and Data Memory SWAP = 0 : Code and data memory are in their standard locations (default) SWAP = 1 : Code and data memory are swapped The modification of this bit is by software only and must be completed by the special software unlock sequence in order to effect the mode change. Otherwise, this bit automatically reverts to its previous value with the third EOI (end of instruction) after this bit is modified. This is to prevent any incorrect status read. 3-3 V 0.4, 2002-01 User’s Manual C868 Memory Organization Field BSLEN Bits 2 Typ Description rw Bootstrap Mode Enable BSLEN = 1 : Bootstrap mode BSLEN = 0 : Normal mode (default) This bit is initialised to the reverse of the value at external pin ALE/BSL latched at the rising edge of RESET. This bit can be set/cleared by software to change between the modes. The modification of this bit by sofware must be completed by the special software unlock sequence in order to effect the mode change. Otherwise, this bit automatically reverts to its previous value with the third EOI (end of instruction) after this bit is modified. This is to prevent any incorrect status read. Switch Mode The SWC bit must be set as the second instruction in a special software unlock sequence directly after having set bit ESWC. The new chipmode becomes active after the second EOI (end of instruction) after this event and the SWC bit is also cleared simultaneously. SWC is a write only bit. Reading SWC returns a ’0’. Enable Switch Mode The ESWC bit must be set during the first instruction in the special software unlock sequence. The bit ESWC will be cleared by hardware with the third EOI (end of instruction) after this event. ESWC is a write only bit. Reading ESWC returns a ’0’. SWC 6 w ESWC 7 w - [7:2] r reserved; returns ’0’ if read; should be written with ’0’; User’s Manual 3-4 V 0.4, 2002-01 C868 Memory Organization 3.3.2 Chip Modes The various chip modes supported are shown in Figure 3-2. Normal Mode Bootstrap Mode Normal XRAM Mode Hardware Software Bootstrap XRAM Mode Figure 3-2 Entry and exit of Chip Modes A valid hardware reset would, of course, override any of the above entry or exit procedures. Table 3-1 Hardware and Software Selection of Chipmodes Hardware Selection ALE/BSL pin = high RESET rising edge Not possible Software Selection ALE/BSL = don’t care; setting bits BSLEN, SWAP = 0,0; execute unlocking sequence setting bits BSLEN,SWAP = 0,1; execute unlocking sequence setting bits BSLEN,SWAP = 1,1; execute unlocking sequence ALE/BSL = don’t care; setting bits BSLEN, SWAP = 1,0; execute unlocking sequence Operating Mode (Chipmode) Normal Mode Normal XRAM Mode Bootstrap XRAM Mode Not possible Bootstrap Mode ALE/BSL pin = low RESET rising edge User’s Manual 3-5 V 0.4, 2002-01 C868 Memory Organization 3.3.2.1 Table 3-2 Normal Mode Normal Memory Configuration for C868 Memory Boundary RAM/ROM: 0000H to 1FFFH XRAM: FF00H to FFFFH The normal mode is the standard 8051 compatible operating mode of the C800. Memory Space Code Space Internal Data Space 3.3.2.2 Bootstrap Mode In the bootstrap mode, code is fetched from the boot-ROM when PC is less than 1000H. A dedicated 4 Kbyte boot-ROM is implemented to support this function. The actual code inside the boot-ROM could be made up of various components such as programming code for RAM module, download code, initialization routines or diagnostic software. The bootstrap mode can be entered via one of the possible ways: – hardware start-up sequence, or – software entry using special unlock sequence The exit from the bootstrap mode is possible via one of the possible ways: – hardware reset, or – software using special unlock sequence The memory mapping for this mode is shown in the Table 3-3 Table 3-3 Bootstrap Memory Configuration for C868-1R Memory Boundary Boot ROM: 0000H to 0FFFH XRAM: FF00H to FFFFH, ROM/RAM: 0000H to 1FFFH Memory Space Code Space Internal Data Space Once in the bootstrap mode, the on-chip XRAM is always enabled irrespective of the XMAP0 bit in SFR SYSCON0. Exiting the bootstrap mode via software, the on-chip XRAM access returns to the state prior to entering this mode, depending on XMAP0. 3.3.2.3 XRAM Modes In the XRAM modes, code and data memory are swapped and in this case the code can be fetched from the data space. This is useful for running diagnostic software. The entry and exit into this mode is always through the special software unlock sequence. The XRAM mode could be entered from either the normal mode or the User’s Manual 3-6 V 0.4, 2002-01 C868 Memory Organization bootstrap mode. Table 3-4 and Table 3-5 show the various memory configurations respectively in an example. Table 3-4 Normal XRAM Mode Memory Boundary XRAM: FF00H to FFFFH ROM/RAM: 0000H to 1FFFH Memory Space Code Space Data Space Table 3-5 Bootstrap XRAM Mode Memory Boundary Boot ROM: 0000H to 0FFFH XRAM: FF00H to FFFFH RAM/ROM: 0000H to 1FFFH Memory Space Code Space Data Space The on-chip XRAM, which is in the upper part of the 64 KB data space, is always enabled in this mode for code access irrespective of the XMAP0 bit. The external data space also becomes code space. The actual physical sizes of the various memory types as mentioned above are product specific. In the C868, the external accesses are prohibited. For code spaces, appropriate branch instructions must therefore be inserted. The on-chip data space is accessible, as usual, via MOVX instructions. The on-chip data memory accesses to RAM/ROM are restricted by the physical memory available in the respective product. For the C868-1R, the option to disable the access to the ROM is selectable upon request. This option is reflected in SFR Version bit 7(1 for access disabled). An exit from the XRAM mode is possible by software only. In this mode the on-chip XRAM is disabled as data space irrespective of XMAP0 bit in SFR SYSCON0. It will remain disabled after exit from XRAM mode unless the XMAP0 had been cleared prior to entering this mode. User’s Manual 3-7 V 0.4, 2002-01 C868 Memory Organization 3.3.2.4 Software Unlock Sequence A special software unlock sequence is required to enter or exit the various chip modes supported. The bits ESWC and SWC in SFR SYSCON1 are implemented in a way to prevent unintentional changing of the bits SWAP and BSLEN. Any change of the bits SWAP or BSLEN not accompanied by the software unlock sequence will have no effect and the above bits will revert back to their previous values two instructions after being changed. The following programming steps must be executed at the ESWC/SWC unlock sequence: i) First Instruction: This instruction should set the ESWC bit and modify of SWAP and/or BSLEN, as necessary. MOV SYSCON1,#10000X0YB ;X is BSLEN, Y is SWAP ii) Second Instruction : The second instruction must set the SWC bit. If this instruction sequence is followed, then only the mode change in the previous instructions will come into effect. Otherwise the previous mode will be retained and both bits ESWC and SWC are cleared. The new chip mode becomes effective after the end of the second instruction after the writing of the bit SWC. MOV SYSCON1,#11000X0YB ;X is BSLEN, Y is SWAP iii) Third Instruction: The instruction following this sequence should be used for initialization of the program counter to the 16 bit start-address of the new code memory resource, e.g. with : LJMP 0XXXXH ;XXXX is the 16-bit hexadecimal address in new code memory If both SWAP and BSLEN bits are set in the first instruction, both modes will still be entered. It is, in any case, the responsibility of the user to provide the appropriate relocation address depending on the mode prior to the execution of this sequence. The special software unlock instruction sequence cannot be interrupted by an interrupt request. Any read or write operation to SFR SYSCON1 will block the interrupt generation for the first cycle of the directly following instruction. Therefore, the response time of an interrupt request may be additionally delayed. User’s Manual 3-8 V 0.4, 2002-01 C868 Memory Organization 3.4 Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. For accessing the mapped special function area, bit RMAP in special function register SYSCON0 must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0“). SYSCON0 System Control Register 0 7 r 6 r 5 EALE rw 4 RMAP rw 3 r [Reset value: XX10XXX1B] 2 r 1 r 0 XMAP0 rw The functions of the shaded bits are not described here Field RMAP Bits 4 Typ Description rw Special Function Register Map Control RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area is enabled. - [7:2] r reserved; returns ’0’ if read; should be written with ’0’; As long as bit RMAP is set, the mapped special function register area can be accessed. This bit is not cleared automatically by hardware. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. The 109 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All available SFRs whose address bits 0-2 are 0 (e.g. 80H, 88H, 90H, ..., F0H, F8H ) are bit- addressable. Totally there are 128 directly addressable bits within the SFR area. All SFRs are listed in Table 3-6 and Table 3-7. In Table 3-6 they are organized in groups which refer to the functional blocks of the C868-1R, C868-1S. Table 3-7 illustrates the contents (bits) of the SFRs User’s Manual 3-9 V 0.4, 2002-01 C868 Memory Organization Table 3-6 Special Function Registers - Functional Blocks Name Add- Contents ress after Reset E0H1) F0H1) 83H 82H 84H D0H1) 81H 98H1) 99H A8H1) A9H AAH B8H1) ACH 88H1) 89H 8AH 8BH 8CH 8DH 87H 8EH 9FH 91H 92H 93H E8H1) F8H1) C0H1) F9H ADH AFH 00H 00H 00H 00H 00H 00H 07H 00H 00H 0X000000B2) XXXXX000B2) XX0000XXB2) XX000000B2) XX000000B2) 00H 00H 00H 00H 00H 00H 0XXX0000B 2) XXX00000B2) 10011111B XXXXXX00B2) XXXXXX00B2) XXXXXXX0B2) XXXXX000B2) XXXXX000B2) X0X00000B2) 00H XX10XXX1B2) 00XXX0X0B2) Block Symbol C800 ACC core B DPH DPL DPSEL PSW SP SCON SBUF IEN0 IEN1 IEN2 IP0 IP1 TCON TMOD TL0 TL1 TH0 TH1 PCON System PMCON0 CMCON EXICON IRCON0 IRCON1 PMCON1 PMCON2 SCUWDT VERSION SYSCON0 SYSCON1 Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer Serial Channel Control Register Serial Data Buffer Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 interrupt Priority Register 1 Timer 0/1 Control Register Timer Mode Register Timer 0, Low Byte Timer 1, Low Byte Timer 0, High Byte Timer 1, High Byte Power Control Register Wake-up Control Register Clock Control Register External Interrupt Control Register External Interrupt Request Register Peripheral Interrupt Request Register Peripheral Management Ctrl Register Peripheral Management Status Register SCU/Watchdog Control Register ROM Version Register System Control Register 0 System Control Register 1 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0 User’s Manual 3-10 V 0.4, 2002-01 C868 Memory Organization Table 3-6 Special Function Registers - Functional Blocks (cont’d) Name Add- Contents ress after Reset D8H1) 0000X000B2) D9H XXXX0000B2) DBH 00H 90H1) 90H1) B0H1) B0H1) B1H B4H A2H A3H B2H B3H C8H1) C9H CBH CAH CDH CCH XXX11111B XXX11111B FFH FFH 00H XXX00X00B2) XXXXXX00B2) 00H 00H 00H 00H XXXXXXX0B2) 00H 00H 00H 00H Block Symbol A/D- ADCON0 Con- ADCON1 verter ADDATH Ports P1 4) P1DIR 3) P3 4) P3DIR 3) P3ALT P1ALT A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register Port 1 Register Port 1 Direction Register Port 3 Register Port 3 Direction Register Port 3 Alternate Function Register Port 1 Alternate Function Register Watchdog Timer Control Register Watchdog Timer Reload Register Watchdog Timer, Low Byte Watchdog Timer, High Byte Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture, High Byte Timer 2 Reload/Capture, Low Byte Timer 2, High Byte Timer 2, Low Byte Watch WDTCON dog WDTREL WDTL WDTH Timer T2CON 2 T2MOD RC2H RC2L T2H T2L 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0 User’s Manual 3-11 V 0.4, 2002-01 C868 Memory Organization Table 3-6 Special Function Registers - Functional Blocks (cont’d) Name Add- Contents ress after Reset ECH EDH EEH EFH DEH DFH D2H D3H C2H C3H C4H C5H C6H C7H D4H D5H E6H E7H F4H F5H EAH EBH E2H E3H F2H F2H F3H E4H E5H BCH BDH BCH BDH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0H 00H 00H 00H 00H 00H 00H 00H Block Symbol Capture/ Compare Unit T12L T12H T13L T13H T12PRL T12PRH T13PRL T13PRH CC60RL CC60RH CC61RL CC61RH CC62RL CC62RH CC63RL CC63RH T12DTCL T12DTCH CMPSTATL CMPSTATH CMPMODIFL CMPMODIFH TCTR0L TCTR0H TCTR2L3) TCTR4L4) TCTR4H4) ISL ISH ISSL4) ISSH4) ISRL3) ISRH3) Timer T12 Counter Register, Low Byte Timer T12 Counter Register, High Byte Timer T13 Counter Register, Low Byte Timer T13 Counter Register, High Byte Timer T12 Period Register, Low Byte Timer T12 Period Register, High Byte Timer T13 Period Register, Low Byte Timer T13 Period Register, High Byte Capture/Compare Ch 0 Reg, Low Byte Capture/Compare Ch 0 Reg, High Byte Capture/Compare Ch 1 Reg, Low Byte Capture/Compare Ch 1 Reg, High Byte Capture/Compare Ch 2 Reg, Low Byte Capture/Compare Ch 2 Reg, High Byte T13 Compare Register, Low Byte T13 Compare Register, High Byte Timer T12 Dead Time Ctrl, Low Byte Timer T12 Dead Time Ctrl, High Byte Compare Timer Status, Low Byte Compare Timer Status, High Byte Compare Timer Modification, Low Byte Compare Timer Modification, High Byte Timer Control Register 0, Low Byte Timer Control Register 0, High Byte Timer Control Register 2, Low Byte Timer Control Register 4, Low Byte Timer Control Register 4, High Byte Cap/Com Interrupt Register, Low Byte Cap/Com Interrupt Register, High Byte Cap/Com Int Status Set Reg, Low Byte Cap/Com Int Status Set Reg, High Byte Cap/Com Int Status Reset Reg, Low Byte Cap/Com Int Status Reset Reg,High Byte 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0 User’s Manual 3-12 V 0.4, 2002-01 C868 Memory Organization Table 3-6 Special Function Registers - Functional Blocks (cont’d) Name Add- Contents ress after Reset BEH BFH BEH BFH FAH FBH FCH FDH FEH FFH B6H B7H D6H D7H CEH CFH A6H DCH DDH DCH DDH D6H F6H F7H 40H 39H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Block Symbol Capture/ Compare Unit INPL3) INPH3) IENL4) IENH4) CC60SRL CC60SRH CC61SRL CC61SRH CC62SRL CC62SRH CC63SRL CC63SRH MODCTRL3) MODCTRH3) TRPCTRL TRPCTRH PSLRL MCMOUTL4) MCMOUTH4) MCMOUTSL3) MCMOUTSH3) MCMCTRL4) T12MSELL T12MSELH Cap/Com Int Node Ptr Reg, Low Byte Cap/Com Int Node Ptr Reg, High Byte Cap/Com Interrupt Register, Low Byte Cap/Com Interrupt Register, High Byte Cap/Com Channel 0 Shadow, Low Byte Cap/Com Channel 0 Shadow, High Byte Cap/Com Channel 1 Shadow, Low Byte Cap/Com Channel 1 Shadow, High Byte Cap/Com Channel 2 Shadow, Low Byte Cap/Com Channel 2 Shadow, High Byte T13 Compare Shadow Reg, Low Byte T13 Compare Shadow Reg, High Byte Modulation Control Register, Low Byte Modulation Control Register, High Byte Trap Control Register, Low Byte Trap Control Register, High Byte Passive State Level Register, Low Byte MCM Output Register, Low Byte MCM Output Register, High Byte MCM Output Shadow Register, Low Byte MCM Output Shadow Register,High Byte MCM Control Register, Low Byte T12 Cap/Com Mode Sel Reg, Low Byte T12 Cap/Com Mode Sel Reg, High Byte 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0 User’s Manual 3-13 V 0.4, 2002-01 C868 Memory Organization Table 3-7 Addr Register 81H 82H 83H 84H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H2) SP DPL DPH Contents of the SFRs, SFRs in numeric order of their addresses Content after Reset1) Bit 7 .7 .7 .7 – Bit 6 .6 .6 .6 – Bit 5 .5 .5 .5 – – TF0 Bit 4 .4 .4 .4 – SD TR0 Bit 3 .3 .3 .3 – GF1 IE1 Bit 2 .2 .2 .2 D2 GF0 IT1 Bit 1 .1 .1 .1 D1 PDE IE0 Bit 0 .0 .0 .0 D0 IDLE IT0 07H 00H 00H DPSE 00H L PCON 0XX0 SMOD – 0000B TCON 00H TMOD 00H TL0 TL1 TH0 TH1 00H 00H 00H 00H TF1 TR1 GATE C/NT1 M1(1) M0(1) GATE C/NT0 M1(0) M0(0) 1 0 .7 .7 .7 .7 .6 .6 .6 .6 – .5 .5 .5 .5 – .4 .4 .4 .4 EBO .3 .3 .3 .3 BO REL3 .3 .3 – – – .2 .2 .2 .2 .1 .1 .1 .1 .0 .0 .0 .0 EPWD REL0 .0 .0 PMCO XXX0 – N0 0000B SDST WS AT REL2 .2 .2 – – – REL1 .1 .1 CMCO 1001 KDIV2 KDIV1 KDIV0 REL4 N 1111B P1 XXX1 – – – .4 1111B – – – – – – – – .4 – – – 90H3) P1DIR XXX1 – 1111B 91H 92H 93H EXICO XXXX – N XX00B IRCO N0 IRCO N1 XXXX – XX00B XXXX – XXX0B ESEL3 ESEL2 EXINT EXINT 3 2 – IADC 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers User’s Manual 3-14 V 0.4, 2002-01 C868 Memory Organization Table 3-7 Addr Register 98H 99H A2H A3H A6H A8H A9H AAH ACH ADH AFH Contents of the SFRs, SFRs in numeric order of their addresses Content after Reset1) Bit 7 SM0 .7 Bit 6 SM1 .6 – .6 Bit 5 SM2 .5 – .5 PSL5 ET2 – Bit 4 REN .4 – .4 PSL4 ES – Bit 3 TB8 .3 – .3 PSL3 ET1 – Bit 2 RB8 .2 – .2 PSL2 EX1 EX3 Bit 1 TI .1 – .1 PSL1 ET0 EX2 Bit 0 RI .0 WDT RIN .0 PSL0 EX0 EADC – .0 XMAP 0 SWAP .0 .0 SCON 00H SBUF 00H WDTC XXXX – ON XX00B WDTR 00H EL .7 PSLRL 00H PSL63 – IEN0 0X00 EA – 0000B IEN1 IEN2 IP1 XXXX – X000B XX00 – 00XXB XX00 – 0000B – – – EINP3 EINP2 EINP1 EINP0 – .5 EALE _ .5 .5 .4 .3 .2 – BSLE N .2 .2 .1 – _ .1 .1 SYSC XX10 – – ON0 XXX1B SYSC 00XX ESWC SWC ON1 X0X0B FFH .7 .7 CC60 .7 .7 .6 .6 RMAP – _ .4 .4 _ .3 .3 B0H2) P3 B0H3) P3DIR FFH B1H P3ALT 00H B2H B3H B4H B6H WDTL 00H WDTH 00H COUT CC61 60 .6 .6 _ .6 .5 .5 _ .5 COUT CC62 61 .4 .4 RxD .4 .3 .3 INT3 .3 COUT CTRA COUT 62 P 63 .2 .2 _ .2 .1 .1 EXF2 .1 .0 .0 TxD .0 P1ALT XXX0 _ 0X00B CC63 00H SRL .7 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers User’s Manual 3-15 V 0.4, 2002-01 C868 Memory Organization Table 3-7 Addr Register B7 H B8H Contents of the SFRs, SFRs in numeric order of their addresses Content after Reset1) Bit 7 .7 Bit 6 .6 – Bit 5 .5 .5 Bit 4 .4 .4 Bit 3 .3 .3 Bit 2 .2 .2 Bit 1 .1 .1 Bit 0 .0 .0 CC63 00H SRH IP0 XX00 – 0000B 00H 00H 00H 00H 00H 00H 00H 00H BCH2) ISSL BCH3) ISRL BDH2) ISSH BDH3) ISRH BEH2) IENL BEH3) INPL BFH2) IENH BFH3) INPH C0H C2H C3H C4H C5H ST12P ST12O SCC62 SCC62 SCC62 SCC62 SCC62 SCC62 M M F R F R F R RT12P RT12O RCC6 RCC6 RCC6 RCC6 RCC6 RCC6 M M 2F 2R 2F 2R 2F 2R – – SIDLE SWHE SCHE – RIDLE RWHE RCHE – STRP ST13P ST13C F M M RTRP RT13P RT13C F M M ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC PM OM 62F 62R 61F 61R 60F 60R INPCH INPCH INPCC INPCC INPCC INPCC INPCC INPCC E.1 E.0 62.1 62.0 61.1 61.0 60.1 60.0 – – – .7 .7 .7 .7 ENIDL ENWH EN E E CHE – PLLR .6 .6 .6 .6 – ENTR ENT13 ENT13 PF PM CM INPT1 INPT1 INPT1 INPT1 INPER INPER 3.1 3.0 2.1 2.0 R.1 R.0 – .5 .5 .5 .5 WDTR WDTE WDTD WDTR WDTR OI IS S E .4 .4 .4 .4 .3 .3 .3 .3 .2 .2 .2 .2 .1 .1 .1 .1 .0 .0 .0 .0 SCUW 00H DT CC60 00H RL CC60 00H RH CC61 00H RL CC61 00H RH 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers User’s Manual 3-16 V 0.4, 2002-01 C868 Memory Organization Table 3-7 Addr Register C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H D2H D3H D4H D5H Contents of the SFRs, SFRs in numeric order of their addresses Content after Reset1) Bit 7 .7 .7 TF2 Bit 6 .6 .6 EXF2 – .6 .6 .6 .6 – Bit 5 .5 .5 Bit 4 .4 .4 Bit 3 .3 .3 Bit 2 .2 .2 Bit 1 .1 .1 C/T2 – .1 .1 .1 .1 TRP1 Bit 0 .0 .0 CP/ RL2 DCEN .0 .0 .0 .0 TRP0 CC62 00H RL CC62 00H RH T2CO 00H N RCLK TCLK – .5 .5 .5 .5 – – .4 .4 .4 .4 – EXEN TR2 2 – .3 .3 .3 .3 – – .2 .2 .2 .2 TRP2 T2MO XXXX – D XXX0B RC2L 00H RC2H 00H TL2 TH2 00H 00H .7 .7 .7 .7 – TRPC 00H TRL TRPC 00H TRH PSW 00H T13PR 00H L T13PR 00H H CC63 00H RL CC63 00H RH TRPE TRPE TRPE TRPE TRPE TRPE TRPE TRPE N N13 N5 N4 N3 N2 N1 N0 CY .7 .7 .7 .7 – AC .6 .6 .6 .6 – F0 .5 .5 .5 .5 RS1 .4 .4 .4 .4 RS0 .3 .3 .3 .3 OV .2 .2 .2 .2 F1 .1 .1 .1 .1 P .0 .0 .0 .0 D6H2) MCMC 00H TRLL D6H3) MODC 00H TRL SWSY SWSY – N1 N0 SWSE SWSE SWSE L2 L1 L0 MCME – N T12M T12M T12M T12M T12M T12M ODEN ODEN ODEN ODEN ODEN ODEN 5 4 3 2 1 0 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers User’s Manual 3-17 V 0.4, 2002-01 C868 Memory Organization Table 3-7 Addr Register Contents of the SFRs, SFRs in numeric order of their addresses Content after Reset1) Bit 7 – Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7H3) MODC 00H TRH D8H D9H DBH T13M T13M T13M T13M T13M T13M T13M ODEN ODEN ODEN ODEN ODEN ODEN ODEN 6 5 4 3 2 1 0 ADCH ADCH ADCH 2 1 0 ADST ADCT ADCT C0 C1 C0 .2 .1 .0 ADCO 0000 ADST ADBS ADM1 ADM0 – N0 X000B Y ADCO X1XX – CAL – – ADST N1 0000B C1 ADDA 00H TH .7 – .6 R .5 .4 .3 DCH2) MCMO 00H UTL DCH3) MCMO 00H UTSL DDH2) MCMO 00H UTH DDH3) MCMO 00H UTSH DEH DFH E0H E2H E3H E4H E5H T12PR 00H L T12PR 00H H ACC 00H TCTR 00H 0L TCTR 10H 0H ISL ISH 00H 00H MCMP MCMP MCMP MCMP MCMP MCMP 5 4 3 2 1 0 MCMP MCMP MCMP MCMP MCMP MCMP S5 S4 S3 S2 S1 S0 CURH CURH CURH EXPH EXPH EXPH 2 1 0 2 1 0 CURH CURH CURH EXPH EXPH EXPH S2 S1 S0 S2 S1 S0 .5 .5 .5 .4 .4 .4 .3 .3 .3 .2 .2 .2 .1 .1 .1 .0 .0 .0 STRM – CM – – STRH – P .7 .7 .7 CTM – .6 .6 .6 CDIR – STE12 T12R STE13 T13R T12PR T12CL T12CL T12CL E K2 K1 K0 T13 PRE T13 CLK2 T13CL T13CL K1 K0 T12PM T12O M – IDLE ICC62 ICC62 ICC61 ICC61 ICC60 ICC60 F R F R F R WHE CHE TRPS TRPF T13PM T13C M 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers User’s Manual 3-18 V 0.4, 2002-01 C868 Memory Organization Table 3-7 Addr Register E6H E7H E8H EAH EBH ECH EDH EEH EFH F0H Contents of the SFRs, SFRs in numeric order of their addresses Content after Reset1) Bit 7 Bit 6 – Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T12DT 00H CL T12DT 00H CH – DTM5 DTM4 DTM3 DTM2 DTM1 DTM0 DTE2 DTE1 DTE0 DTR2 DTR1 DTR0 – – – – – – .4 .4 .4 .4 .4 – – – – .3 .3 .3 .3 .3 PMCO XXXX – N1 X000B CMPM 00H ODIFL CMPM 00H ODIFH T12L T12H T13L T13H B 00H 00H 00H 00H 00H – – .7 .7 .7 .7 .7 CCUDI T2DIS ADCDI S S MCC6 MCC6 MCC6 2S 1S 0S MCC6 MCC6 MCC6 2R 1R 0R .2 .2 .2 .2 .2 .1 .1 .1 .1 .1 .0 .0 .0 .0 .0 MCC6 – 3S MCC6 – 3R .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 F2H2) TCTR 00H 4L F2H3) TCTR 00H 2L F3H2) TCTR 00H 4H F4H F5H F6H F7H CMPS 00H TATL CMPS 00H TATH T12M 00H SELL T12M 00H SELH T12ST T12ST – D R – DTRE T12RE T12RS T12RR S S T13TE T13TE T13TE T13TE T13TE T13SS T12SS D1 D0 C2 C1 C0 C C – – – – T13RE T13RS T13RR S CC62S CC61S CC60S T T T T13ST T13ST – D R – CC63S – T T13IM COUT COUT CC62P COUT CC61P COUT CC60P 63PS 62PS S 61PS S 60PS S MSEL MSEL MSEL MSEL MSEL MSEL MSEL MSEL 613 612 611 610 603 602 601 600 – – – – MSEL MSEL MSEL MSEL 623 622 621 620 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers User’s Manual 3-19 V 0.4, 2002-01 C868 Memory Organization Table 3-7 Addr Register F8H F9H FAH FBH FCH FDH FEH FFH Contents of the SFRs, SFRs in numeric order of their addresses Content after Reset1) Bit 7 Bit 6 – Bit 5 – Bit 4 – Bit 3 – Bit 2 Bit 1 Bit 0 ADCS T PMCO XXXX – N2 X000B VERSI 00H ON CC60 00H RL CC60 00H RH CC61 00H RL CC61 00H RH CC62 00H RL CC62 00H RH CCUS T2ST T PROT VER6 VER5 VER4 VER3 VER2 VER1 VER0 .7 .7 .7 .7 .7 .7 .6 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 .5 .4 .4 .4 .4 .4 .4 .3 .3 .3 .3 .3 .3 .2 .2 .2 .2 .2 .2 .1 .1 .1 .1 .1 .1 .0 .0 .0 .0 .0 .0 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers User’s Manual 3-20 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4 On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the C868 except for the integrated interrupt controller, which is described separately in chapter 7. 4.1 Ports The C868 has two kinds of ports. The first kind is push-pull ports instead of the traditional quasi-bidirectional ports. The ports belonging to this kind is port 1 which is a 5-bit I/O port and port 3 which is an eight-bit I/O port. When configured as inputs, these ports will be high impedance with Schmitt trigger feature. Port 3 is alternate for capture/compare functions whereas, port 1 has alternate functions for some of the pins. The second kind is dedicated ports which are shared by the interrupts, timer 2 inputs, capture/compare hall inputs and analog inputs. 4.2 I/O Ports Port 1 and 3 are push-pull ports. Port 1 and port 3 can function as normal I/O ports which have associated SFRs at address 90H and B0H respectively. These ports also have alternate functions as listed in Table 4-2. There are three SFRs dedicated for each of these ports. The first one is the port latch (P1/P3) and second one is direction control register (P1DIR/P3DIR) which is used to set the direction for each pin. In P1DIR/P3DIR, if the bit is set to 0 the respective port pin is an output, and 1 means an input. After reset, by default all the Port 1 and 3 pins are input. The third one is the alternate function register (P1ALT/P3ALT) which is used to set the function of each pin. When used as alternate function, the direction of the pins has to be set accordingly. When the bit is set an input, any read operation will return the value at the port. When the bit is set as an output, a read operation will return the latched value if it is part of a read-modify-write operation, otherwise a read operation will return the value at the port. Note: While in the idle mode or the power down mode the I/O ports hold the last values. User’s Manual 4-1 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.2.1 Table 4-1 Register P1 P1DIR P3 P3DIR P3ALT P1ALT Register Overview Memory Organization Register Overview Description Port 1 SFR Port 1 Direction Port 3 SFR Port 3 Direction Port 3 Alternate Function Port 1 Alternate Function 90H 90H B0H B0H B1H B4H Address The following table lists the port SFR registers. They contain the value in the port latches. P1 and P1DIR is mapped on the same address and depend on the RMAP (SYSCON0.4) bit to select between the two registers. By default (bit = 0), P1 occupies the address. If the bit is set to 1 then P1DIR occupy the address. P3 and P3DIR is mapped on the same address and depend on the RMAP (SYSCON0.4) bit to select between the two registers. By default (bit = 0), P3 occupies the address. If the bit is set to 1 then P3DIR occupy the address. Ports 1 and 3 also serves alternate functions as listed in the Table 4-2. To select between the alternate function and normal I/O, registers P1ALT and P3ALT are used. Each can be set to ’1’ for alternate functions, or reset to ’0’ for normal I/O. Table 4-2 Port 1 1 1 1 3 3 3 3 3 3 3 3 User’s Manual Ports 1 and 3 Alternate Functions Pin P1.0 P1.1 P1.3 P1.4 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alt-Function TxD EXF2 INT3 RxD COUT63 CTRAP COUT62 CC62 COUT61 CC61 COUT60 CC60 4-2 Description Transmit data of serial interface Timer 2 overflow flag Interrupt 3 Receive data of serial interface 16 bit compare channel output CCU trap input Output of CCU6 channel 2 Input/output of CCU6 channel 2 Output of CCU6 channel 1 Input/output of CCU6 channel 1 Output of CCU6 channel 0 Input/output of CCU6 channel 0 V 0.4, 2002-01 C868 On-Chip Peripheral Components P1 Port 1 Register 94H r r r 93H [Reset value: XXX11111B] 92H P1[4:0] rw 91H 90H Field P1.4-0 Bits [4:0] Typ Description rw Port 1 Latch. This SFR appears at address 90H, only if bit RMAP (SYSCON0.4) is ‘0’. reserved; returns ’0’ if read; should be written with ’0’; - [7:5] r P1DIR Port 1 Direction Register 94H r r r 93H [Reset value: XXX11111B] 92H P1DIR[4:0] rw 91H 90H Field P1DIR.4-0 Bits [4:0] Typ Description rw Port 1 Direction Register. This SFR appears at address 90H, only if bit RMAP (SYSCON0.4) is ‘1’ 0: The associated pin is an output. 1: The associated pin is an input (default). reserved; returns ’0’ if read; should be written with ’0’; - [7:5] r User’s Manual 4-3 V 0.4, 2002-01 C868 On-Chip Peripheral Components P3 Port 3 Register B7H B6H B5H B4H P3 rw B3H B2H [Reset value: FFH] B1H B0H Field P3 Bits [7:0] Typ Description rw Port 3 Latch. This SFR appears at address B0H, only if bit RMAP (SYSCON0.4) is ‘0’. P3DIR Port 3 Direction Register B7H B6H B5H B4H P3DIR rw B3H B2H [Reset value: FFH] B1H B0H Field P3DIR Bits [7:0] Typ Description rw Port 3 Direction Register. This SFR appears at address B0H, only if bit RMAP (SYSCON0.4) is ‘1’ 0: The associated pin is an output. 1: The associated pin is an input (default). User’s Manual 4-4 V 0.4, 2002-01 C868 On-Chip Peripheral Components P1ALT Port 1 Alternate Function Register 7 r 6 r 5 r 4 3 [Reset value: XXX00X00B] 2 r 1 0 P1ALT[4:3] rw P1ALT[1:0] rw Field P1ALT.1-0 P1ALT.4-3 Bits [1:0] [4:3] Typ Description rw Port 1 Alternate Function Switch 0: The associated pin is a normal I/O. (default) 1: The associated pin is an alternate function. Please see Table 4-2. All the other bits in this register are reserved for the future use. reserved; returns ’0’ if read; should be written with ’0’; - [7:5],2 r P3ALT Port 3 Alternate Function Register 7 6 5 4 P3ALT rw 3 2 [Reset value: 00H] 1 0 Field P3ALT Bits [7:0] Typ Description rw Port 3 Alternate Function Switch 0: The associated pin is a normal I/O. (default) 1: The associated pin is an alternate function. Please see Table 4-2. User’s Manual 4-5 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.3 Dedicated Ports Beside I/O Port, the rest of the ports are dedicated ports. These dedicated ports do not require bit latches as it uses the ’alternate access’. ANALOG[4:0]: These are pure analog inputs to the ADC module. The signals from the pin should be rightaway directed to the ADC module. These pins are used as digital input for the interrupts, hall inputs to the CCU6 module and inputs to the timer 2 module. User’s Manual 4-6 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.4 Port 1, Port 3 Circuitry The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to implement special features as listed in Table 4-2. Figure 4-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of the I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P1 and P3) activate the "read-latch" signal, while others activate the "read-pin" signal. Figure 4-1 shows a functional diagram of a port latch with alternate function. Read Latch Alternate Output Function Int. Bus Write to Latch D Q Bit Latch CLK Q Port Driver Circuit Port Pin Read Pin Alternate Input Function Figure 4-1 Ports 1 and 3 User’s Manual 4-7 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.4.1 Read-Modify-Write Feature of Ports Some port-reading instructions read the latch and others read the pin. The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write"- instructions, which are listed in 4-3. If the destination is a port or a port pin, these instructions read the latch rather than the pin. Note that all other instructions which can be used to read a port, exclusively read the port pin. In any case, reading from latch or pin, resp., is performed by reading the SFR P3; for example, "MOV A, P3" reads the value from port 3 pins, while "ANL P3, #0AAH" reads from the latch, modifies the value and writes it back to the latch. It is not obvious that the last three instructions in Figure 4-3 are read-modify-write instructions, but they are. The reason is that they read the port byte, all 8 bits, modify the addressed bit, then write the complete byte back to the latch. Table 4-3 "Read-Modify-Write"-Instructions Instruction ANL ORL XRL JBC CPL INC DEC DJNZ CLR Px.y SETB Px.y Function Logic AND; e.g. ANL P1, A Logic OR; e.g. ORL P2, A Logic exclusive OR; e.g. XRL P3, A Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL Complement bit; e.g. CPL P3.0 Increment byte; e.g. INC P4 Decrement byte; e.g. DEC P5 Decrement and jump if not zero; e.g. DJNZ P3, LABEL Clear bit y of port x Set bit y of port x MOV Px.y,C Move carry bit to bit y of port x The reason why read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "1" is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transitor (approx. 0.7 V, i.e. a logic low level!) and interpret it as "0". For example, when modifying a port bit by a SETB or CLR instruction, another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to th latch. However, reading the latch rater than the pin will return the correct value of "1". User’s Manual 4-8 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.5 Timers/Counters The C868 contains three 16-bit timers/counters, timer 0, timer 1 and timer/counter 2, which are useful in many applications for timing and counting. The timer register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 12 periods, the counter rate is 1/12 of the system frequency. 4.5.1 Timer 0 and 1 Timer 0 and 1 of the C868 are fully compatible with timer 0 and 1 can be used in the same four operating modes: Mode 0:8-bit timer with a divide-by-32 prescaler Mode 1:16-bit timer Mode 2:8-bit timer with 8-bit auto-reload Mode 3:Timer 0 is configured as two 8-bit timers. Timer 1 in this mode holds its count. The effect is the same as setting TR1 = 0. External inputs INT0 and INT1 can be programmed to function as a gate for timer 0 and 1 to facilitate pulse width measurements. Each timer consists of two 8-bit registers (TH0 and TL0 for timer 0, TH1 and TL1 for timer 1) which may be combined to one timer configuration depending on the mode that is established. The functions of the timers are controlled by two special function registers TCON and TMOD. In the following descriptions the symbols TH0 and TL0 are used to specify the high-byte and the low-byte of timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for timer 0. If not explicity noted, this applies also to timer 1. User’s Manual 4-9 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.5.1.1 Timer 0 and 1 Registers Totally seven special function registers control the timer 0 and 1 operation : – TL0/TH0 and TL1/TH1 - timer registers, low and high part – TCON and IEN0 - control and interrupt enable – TMOD - mode select TLx(x=0..1) Timer x Low Register 7 6 5 4 TLx7..0 rwh 3 2 [Reset value: 00H] 1 0 THx(x=0..1) Timer x High Register 7 6 5 4 THx7..0 rwh 3 2 [Reset value: 00H] 1 0 Field TLx.7-0(x=0..1) Bits [7:0] Typ Description rwh Timer/counter 0/1 low register Operating Mode 0 1 Description "TLx" holds the 5-bit prescaler value. "TLx" holds the lower 8-bit part of the 16-bit timer/ counter value. "TLx" holds the 8-bit timer/ counter value. TL0 holds the 8-bit timer/ counter value; TL1 is not used. 2 3 User’s Manual 4-10 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field THx.7-0(x=0..1) Bits [7:0] Typ Description rwh Timer 0/1 high register Operating Mode 0 1 2 3 Description "THx" holds the 8-bit timer value. "THx" holds the higher 8-bit part of the 16-bit timer value "THx" holds the 8-bit reload value. TH0 holds the 8-bit timer value; TH1 is not used. User’s Manual 4-11 V 0.4, 2002-01 C868 On-Chip Peripheral Components TCON Power Control Register 8FH TF1 rwh 8EH TR1 rw 8DH TF0 rwh 8CH TR0 rw 8BH IE1 rwh 8AH IT1 rw [Reset value: 00H] 89H IE0 rwh 88H IT0 rw The functions of the shaded bits are not described here Field TR0 TF0 Bits 4 5 Typ Description rw Timer 0 run control bit Set/cleared by software to turn timer 0 ON/OFF. rwh Timer 0 overflow flag Set by hardware on timer overflow. Cleared by hardware when processor vectors to interrupt routine. rw Timer 1 run control bit Set/cleared by software to turn timer 1 ON/OFF. TR1 TF1 6 7 rwh Timer 1 overflow flag Set by hardware on timer overflow. Cleared by hardware when processor vectors to interrupt routine. User’s Manual 4-12 V 0.4, 2002-01 C868 On-Chip Peripheral Components TMOD Timer Register 7 GATE1 rw 6 C/NT1 rw 5 M1(1) rw 4 M0(1) rw 3 GATE0 rw 2 C/NT0 rw [Reset value: 00H] 1 M1(0) rw 0 M0(0) rw Field M0(0) M1(0) M0(1) M1(1) Bits 0 1 4 5 Typ Description rw Mode select bits M1(x) 0 M0(x) 0 Function 8-bit timer: "THx" operates as 8-bit timer "TLx" serves as 5-bit prescaler 16-bit timer. "THx" and "TLx" are cascaded; there is no prescaler 8-bit auto-reload timer. "THx" holds a value which is to be reloaded into "TLx" each time it overflows Timer 0 : TL0 is an 8-bit timer controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only controlled by timer 1 control bits. Timer 1 : Timer/counter 1 stops 0 1 1 0 1 1 C/NT0 C/NT1 GATE0 GATE1 2 6 3 7 rw Counter or timer select bit Cleared for timer operation (input from internal system clock). Gating control rw When set, timer "x" is enabled only while "INT x" pin is high and "TRx" control bit is set. 4-13 V 0.4, 2002-01 User’s Manual C868 On-Chip Peripheral Components IEN0 Interrupt Enable Register AFH EA rw AEH r ADH ET2 rw ACH ES rw ABH ET1 rw AAH EX1 rw [Reset value: 00H] A9H ET0 rw A8H EX0 rw The functions of the shaded bits are not described here Field ET0 ET1 Bits 1 3 Typ Description rw rw Timer 0 overflow interrupt enable. If ET0 = 0, the timer 0 interrupt is disabled. Timer 1 overflow interrupt enable. If ET1 = 0, the timer 1 interrupt is disabled. User’s Manual 4-14 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.5.1.2 Mode 0 Putting either timer 0, 1 into mode 0 configures it as an 8-bit timer with a divide-by-32 prescaler. Figure 4-2 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1 (setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR0, TF0, TH0, TL0 and INT0 for the corresponding timer 1 signals in Figure 4-2. There are two different gate bits, one for timer 1 (TMOD.7) and one for timer 0 (TMOD.3). fSYS 12 C/T = 0 TH0 TL0 (5 Bits) (8 Bits) TF0 Interrupt Control TR0 =1 Gate 1 INT0/INT1 Pin Figure 4-2 Timer 0, Mode 0: 13-Bit Timer User’s Manual 4-15 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.5.1.3 Mode 1 Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in Figure 4-3. fSYS 12 C/T = 0 TH0 TL0 (8 Bits) (8 Bits) TF0 Interrupt Control TR0 =1 Gate 1 INT0/INT1 Pin Figure 4-3 Timer 0, Mode 1: 16-Bit Timer/Counter User’s Manual 4-16 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.5.1.4 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 4-4. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. fSYS 12 C/T = 0 TL0 (8 Bits) TF0 Interrupt Control TR0 Reload =1 Gate 1 TH0 (8 Bits) INT0/INT1 Pin Figure 4-4 Timer 0,1, Mode 2: 8-Bit Timer/Counter with Auto-Reload User’s Manual 4-17 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.5.1.5 Mode 3 Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 as two seperate counters. The logic for mode 3 on timer 0 is shown in Figure 4-5. TL0 uses the timer 0 control bits: C/T, Gate, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the "timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When timer 0 is in mode 3 and when TR1 is set, timer 1 can be turned on by switching it to any mode other than 3 and off by switching it into its own mode 3, or can still be used by the serial channel as a baud rate generator, or in fact, in any application not requiring an interrupt from timer 1 itself. fSYS 12 C/T = 0 Timer Clock TL0 (8 Bits) Control TF0 Interrupt TR0 Gate =1 1 TR0 INT0/INT1 Pin TH0 (8 Bits) TR1 TF1 Interrupt Figure 4-5 Timer 0, Mode 3: Two 8-Bit Timers/Counters User’s Manual 4-18 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.6 Functional Description of Timer/Counter 2 Timer two serves as a 16-bit timer/counter for which is also capable of being used as a baudrate generator for the UART module. 4.6.1 Features • 16-bit auto-reload mode – selectable up or down counting • one channel 16-bit capture mode • Baudrate generator for UART • Timer/counter powerdown in normal, idle and slow-down modes 4.6.2 Overview Timer 2 is a 16-bit general purpose timer/counter which can additionally function as a baudrate generator. This module is functionally compatible to the Timer 2 in the C501 product family. Timer/counter 2 can function as a timer or counter in each of its modes. As a timer, it counts with an input clock of fSYS/12. As a counter, it counts 1-to-0 transitions on pin T2. In the counter mode the maximum resolution for the count is fSYS/24. 4.6.3 Register Description The T2CON register is used for controlling the various modes of timer/counter 2 module. Additionally, this register also indicates the status of the timer/counter 2 functions (flags). T2MOD Timer 2 Mode Register,Low Byte 7 r 6 r 5 r 4 r 3 r 2 r [Reset value: 00H] 1 r 0 DCEN rw Field DCEN Bits 0 Typ Description rw Up/Down Counter Enable 0 :Up/Down Counter function is disabled 1 :Up/Down Counter function is enabled and controlled by pin T2EX (Up=1,Down=0) reserved; returns ’0’ if read; should be written with ’0’; 4-19 V 0.4, 2002-01 - [7:6] r User’s Manual C868 On-Chip Peripheral Components T2CON Timer 2 Control Register,Low Byte CFH TF2 rwh CEH EXF2 rwh CDH RCLK rw CCH TCLK rw CBH EXEN2 rw CAH TR2 rw [Reset value: 00H] C9H C/T2 rw C8H CP/RL2 rw Field CP/RL2 Bits 0 Typ Description rw Capture / Reload Select 0 :Reload upon overflow or upon negative transition at pin T2EX (when EXEN2=1) 1 :Capture timer/counter 2 data register contents on negative transition at pin T2EX, provided EXEN2 = 1 If TCLK/RCLK=1, this bit is ignored. Timer or Counter Select 0 :Timer function selected 1 :Count upon negative edge at pin T2 Timer/counter 2 Start / Stop Control 0 :Stop Timer/counter 2 1 :Start Timer/counter 2 Timer/counter 2 External Enable Control 0 :External events are disabled 1 :External events Capture/Reload enabled Transmit Clock Enable 0 :Timer/counter 2 overflow is not used for UART transmitter clock 1 :Timer/counter 2 overflow is used for UART transmitter clock Receiver Clock Enable 0 :Timer/counter 2 overflow is not used for UART receiver clock 1 :Timer/counter 2 overflow is used for UART receiver clock C/T2 1 rw TR2 2 rw EXEN2 3 rw TCLK 4 rw RCLK 5 rw User’s Manual 4-20 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field EXF2 Bits 6 Typ Description rwh Timer/counter 2 External Flag This bit is set by hardware when a capture/reload occurred upon a negative transition at pin T2EX, if bit EXEN=1. An interrupt request to the core is generated, unless bit DCEN=1. This bit must be cleared by software. rw Timer/counter 2 Overflow Flag Set by a timer/counter 2 overflow. Must be cleared by software. TF2 will not be set when either RCLK=1 or TCLK=1. TF2 7 User’s Manual 4-21 V 0.4, 2002-01 C868 On-Chip Peripheral Components The RC2L/H registers are used for a 16-bit reload of the timer/counter count upon overflow or a capture of current timer/counter count depending on the mode selected. RC2L Timer 2 Reload/Capture Register, Low Byte 7 6 5 4 RC2 7..0 rw 3 2 [Reset value: 00H] 1 0 RC2H Timer 2 Reload/Capture Register, High Byte 7 6 5 4 RC2 15..8 rw 3 2 [Reset value: 00H] 1 0 Field RC2 Bits Typ Description Reload/Capture Value These contents are loaded into the timer/counter registers upon an overflow condition, if CP/RL2=0. If CP/RL2 = 1, this registers are loaded with the current timer count upon a negative transition at pin T2EX when EXEN2=1. [7:0] of rw RC2L, [7:0] of RC2H User’s Manual 4-22 V 0.4, 2002-01 C868 On-Chip Peripheral Components The T2L/H registers holds the current 16-bit value of the Timer 2 count. T2L Timer 2, Low Byte 7 6 5 4 T2 7..0 rh 3 2 [Reset value: 00H] 1 0 T2H Timer 2, High Byte 7 6 5 4 T2 15..8 rh 3 2 [Reset value: 00H] 1 0 Field T2 Bits Typ Description Timer 2 Value These bits indicate the current timer value. [7:0] of rh T2L, [7:0] of T2H User’s Manual 4-23 V 0.4, 2002-01 C868 On-Chip Peripheral Components T2DIS in PMCON1 register controls the powerdown of timer/counter 2, T2ST in PMCON2 shows the power status of timer/counter 2. PMCON1 Peripheral Management Control Register 7 r 6 r 5 r 4 r 3 r [Reset value: XXXXX000B] 2 CCUDIS rw 1 T2DIS rw 0 ADCDIS rw The functions of the shaded bits are not described here Field T2DIS Bits 1 Typ Description rw Timer 2 Disable Request. 0 : Timer 2 will continue normal operation. (default) 1 : Request to disable the Timer 2 is active. PMCON2 Peripheral Management Status Register 7 r 6 r 5 r 4 r 3 r [Reset value: XXXXX000B] 2 CCUST rh 1 T2ST rh 0 ADCST rh The functions of the shaded bits are not described here Field T2ST Bits 1 Typ Description rh Timer 2 Disable Status 0 : Timer 2 is not disabled. (default) 1 : Timer 2 is disabled, clock is gated off. User’s Manual 4-24 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.6.4 Operating Mode Selection The operating mode of timer/counter 2 is controlled by register T2CON. This register serves two purposes: – during initialization it provides access to a set of control bits – during timer operation it provides access to a set of status flags. The different modes of operation are: – Auto-Reload Mode, – Capture Mode, and – Baudrate Generator Mode 4.6.5 Auto-Reload Mode In the auto-reload mode, timer/counter 2 counts to an overflow value and then reloads its registers contents with a 16-bit value start value for a fresh counting sequence. The overflow condition is indicated by setting the bit TF2 in the T2CON register. This will then generate an interrupt request to the core by an active high signal. The overflow flag TF2 must be cleared by software. The auto-reload mode is further classified into two categories depending upon the DCEN control bit. 4.6.5.1 Up/Down Count Disabled If DCEN=0, the up-down count selection is disabled. The timer/counter, therefore, functions as a pure up timer/counter only. The operational block diagram is shown in Figure 4-6. In this mode if EXEN2=0, the timer/counter starts to count up to a maximum of FFFFH, once TR2 is set. Upon overflow, bit TF2 is set and the timer register is reloaded with a 16-bit reload of the RC2L/H registers. A fresh count sequence is started and the timer/ counter counts up from this reload value as in the previous count sequence. This reload value is chosen by software, prior to the occurrence of an overflow condition. If EXEN2=1, the timer/counter counts up to a maximum to FFFFH, once TR2 is set. A 16-bit reload of the timer registers from register RC2L/H is triggered either by an overflow condition or by a negative edge at input pin T2EX. If an overflow caused the reload, the overflow flag TF2 is set. If a 1-to-0 transition at pin T2EX caused a reload, bit EXF2 is set. In either case, an interrupt is generated to the core and the timer/counter proceeds to its next count sequence. The EXF2 flag, similar to the TF2, must be cleared by software. Note: In counter mode, if the reload via T2EX and the count clock T2 are detected simultaneously the reload takes precedence over the count. The counter increments its value with the following T2 count clock. User’s Manual 4-25 V 0.4, 2002-01 C868 On-Chip Peripheral Components fSYS 12 C/T2 = 0 T2L/H C/T2 = 1 TR2 Pin T2 Overflow OR RC2L/H TF2 Timer 2 OR Interrupt EXF2 EXEN2 Pin T2EX Figure 4-6 Auto-Reload Mode (DCEN = 0) 4.6.5.2 Up/Down Count Enabled If DCEN=1, the up-down count selection is enabled. The direction of count is determined by the level at input pin T2EX. The operational block diagram is shown in Figure 4-7. A logic 1 at pin T2EX sets the timer/counter 2 to up counting mode. The timer/counter, therefore, counts up to a maximum of FFFFH. Upon overflow, bit TF2 is set and the timer/ counter registers are reloaded with a 16-bit reload of the RC2L/H registers. A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence. This reload value is chosen by software, prior to the occurrence of an overflow condition. A logic 0 at pin T2EX sets the timer/counter 2 to down counting mode. The timer/counter counts down and underflows when the T2L/H value reaches the value stored at registers User’s Manual 4-26 V 0.4, 2002-01 C868 On-Chip Peripheral Components RC2L/H. The underflow condition sets the TF2 flag and causes FFFFH to be reloaded into the T2L/H registers. A fresh down counting sequence is started and the timer/ counter counts down as in the previous counting sequence. In this mode, bit EXF2 toggles whenever an overflow or an underflow condition is detected. This flag, however, does not generate an interrupt request. Note: In counter mode, if the reload via T2EX and the count clock T2 are detected simultaneously the reload takes precedence over the count. The counter increments its value with the following T2 count clock. FFFFH (Down count reload) EXF2 Underflow fSYS 12 C/T2 = 0 C/T2 = 1 TR2 Pin T2 Overflow 16-bit Comparator Timer 2 T2L/H OR TF2 Interrupt RC2L/H Pin T2EX Figure 4-7 Auto-Reload Mode (DCEN = 1) User’s Manual 4-27 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.6.6 Capture Mode In order to enter the 16-bit capture mode, bits CP/RL2 and EXEN2 in register T2CON must be set. In this mode, the down count function must remain disabled. The timer/ counter functions as a 16-bit timer or counter and always counts up to FFFFH and overflows. Upon an overflow condition, bit TF2 is set and the timer/counter reloads its registers with 0000H. The setting of TF2 generates an interrupt request to the core. Additionally, with a falling edge on pin T2EX the contents of the timer/counter registers (T2L/H) are captured into the RC2L/H registers. If the capture signal is detected while the counter is being incremented, the counter is first incremented before the capture operation is performed. This ensures that the latest value of the timer/counter registers are always captured. When the capture operation is completed, bit EXF2 is set and can be used to generate an interrupt request. Figure 4-8 describes the capture function of timer/counter 2. fSYS 12 C/T2 = 0 T2L/H C/T2 = 1 TR2 Pin T2 Overflow RC2L/H TF2 Timer 2 OR Interrupt EXF2 EXEN2 Pin T2EX Figure 4-8 User’s Manual Capture Mode 4-28 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.6.7 Baudrate Generator Mode The baudrate generator mode of timer/counter 2 can be selected by setting the bits TCLK and/or RCLK in register T2CON. So the baudrate for the receive and transmit functions can be individually controlled. The timer/counter itself functions similar to the auto-reload mode with up/down counting is disabled. The timer/counter counts up and overflows but the overflow condition does not set the TF2 flag. An interrupt request to the core is not generated. Upon an overflow condition, the timer/counter registers are reloaded with the RC2L/H registers content and continues counting as before. The overflow signal is provided as an output of the timer/counter 2 block. This is active for one clock cycle only. Additionally, the status of the TCLK and RCLK bits are also provided as outputs of the timer 2 block. The UART, for e.g., could use these signals to control its baudrates. The main difference between the auto-reload mode and the baudrate generator mode is that timer 2 as a baudrate generator uses fSYS/2 as the count clock. In the auto-reload mode the timer/counter 2 uses fSYS/12 as the count clock. If EXEN2=1, in the baudrate generator mode, a falling edge on pin T2EX can be used to generate an interrupt. In this case, flag EXF2 will be set. Note: When timer/counter 2 is in the baudrate generator mode, an increment of the timer register happens for every other fSYS. Therefore, software should not access the T2L/H registers. Software may however, read the RC2L/H registers. Software write into these registers may coincide with a timer update or reload cycle and should therefore be avoided. User’s Manual 4-29 V 0.4, 2002-01 C868 On-Chip Peripheral Components fSYS 12 C/T2 = 0 C/T2 = 1 TR2 Pin T2 Overflow OV_CLK T2L/H RC2L/H Pin T2EX EXEN2 EXF2 Timer 2 Interrupt Figure 4-9 Baudrate Generator Mode 4.6.8 Count Clock The count clock for the auto-reload mode is chosen by the bit C/T2 in register T2CON. If C/T2 = 0, a count clock of fSYS/12 is used for the count operation. If C/T2 = 1, timer 2 behaves as a counter that counts 1-to-0 transitions of input pin T2. The counter samples pin T2 over 2 fSYS cycles. If a 1 was detected during the first clock and a 0 was detected in the following clock, then the counter increments by one. Therefore, the input levels should be stable for at least 1 clocks. 4.6.9 Module Powerdown The timer/counter 2 is disabled when the chip goes into the powerdown mode as describe in . Or it can be individually disabled by setting T2DIS in register PMCON1. This helps to reduce current consumption in the normal, slow down and idle modes of operation if the timer/counter 2 is not utilized. Bit T2ST in register PMCON2 reflects the powerdown status of timer/counter 2. User’s Manual 4-30 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.7 Capture/Compare Unit (CCU6) The CCU6 provides two independent timers (T12, T13), which can be used for PWM generation, especially for AC-motor control. Additionally, special control modes for block commutation and multi-phase machines are supported. Timer 12 Features • Three capture/compare channels, each channel can be used either as capture or as compare channel. • Generation of a three-phase PWM supported (six outputs, individual signals for highside and lowside switches) • 16 bit resolution, maximum count frequency = system clock • Dead-time control for each channel to avoid short-circuits in the power stage • Concurrent update of the required T12/13 registers • Center-aligned and edge-aligned PWM can be generated • Single-shot mode supported • Many interrupt request sources • Hysteresis-like control mode Timer 13 Features • • • • • One independent compare channel with one output 16 bit resolution, maximum count frequency = system clock Can be synchronized to T12 Interrupt generation at period-match and compare-match Single-shot mode supported Additional Features • • • • • • • • Block commutation for Brushless DC-drives implemented Position detection via Hall-sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage Capture/compare unit can be powerdown in normal, idle and slow-down modes The timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. The timer T13 can work in compare mode only. The multichannel control unit generates output patterns which can be modulated by T12 and/or T13. The modulation sources can be selected and combined (refer to figure ’Modulation Selection, Passive Level and Alternate Output Enable of T12’) for the signal modulation. User’s Manual 4-31 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.7.1 4.7.1.1 Timer T12 Overview The timer T12 is used for capture/compare purposes with three independent channels. The timer T12 is a 16-bit wide counter. Three channel registers (CC60R, CC61R, CC62R), which are built with shadow registers (CC60SR, CC61SR, CC62SR), contain the compare value or the captured timer value. In compare mode, the software writes to the shadow registers and their contents are transferred simultaneously to the actual compare registers during the T12 shadow transfer. In capture mode, the captured value of T12 can be read from the channel registers. The period of the timer T12 is fixed by the period register T12PR, which is also built with a shadow register. The write access from the CPU targets the corresponding shadow registers, whereas the read access targets the registers actually used (except for the three compare channels, where the actual and the shadow registers can be read). =1? =0? =? 16 one-match zero-match period-match T12PR compare-match 16 T12PS period shadow transfer compare shadow transfer CC6xSR capture events according to bitfield MSEL6x =? CC6xR 16 counter register T12 T12clk Figure 4-10 T12 Overview While timer T12 is running, write accesses to register T12 are not taken into account. If the timer T12 is stopped and the dead-time counters are 0, write actions to register T12 are immediately taken into account. User’s Manual 4-32 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.7.1.2 Counting Rules Referring to T12 input clock the counting sequence is defined by the following counting rules: T12 in edge-aligned mode: • The counter is reset to zero and (if desired) the T12 shadow transfer takes place if the period-match is detected. The counting direction is always upwards. T12 in center-aligned mode: • The count direction is set to counting up (CDIR=’0’) if the one-match is detected while counting down. • The count direction is set to counting down (CDIR=’1’) if the period-match is detected while counting up. • The counter counts up while CDIR=’0’ and it counts down while CDIR=’1’. • If enabled the shadow transfer takes place: • if the period-match is detected while counting up • if the one-match is detected while counting down The timer T12 prescaler is reset while T12 is not running to ensure reproducible timings and delays. The counting rules lead to the following sequences: . T12clk T12P T12P-1 T12P-2 period-match zero-match 1 0 up=0 value n value n+1 CDIR CC6x T12 shadow transfer Figure 4-11 T12 in edge-aligned mode User’s Manual 4-33 V 0.4, 2002-01 C868 On-Chip Peripheral Components In the center-aligned mode (T12 counts up and down), the counting rules lead to the following behavior: T12clk one-match 1 0 zero-match down=1 value n up=0 value n+1 shadow transfer Figure 4-12 T12 in center-aligned mode, one-match detected 2 2 1 T12 CDIR CC6x T12clk T12P+1 T12P T12P-1 period-match T12 up=0 value n down=1 value n+1 shadow transfer CDIR CC6x Figure 4-13 T12 in center-aligned mode, period-match detected User’s Manual 4-34 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.7.1.3 Switching Rules The compare actions take place in parallel for the three compare channels. Depending on the count direction, the compare matches have different meanings. In order to get the PWM information independent from the output levels, two different states have been introduced for the compare actions: The active state and the passive state, which are used to generate the desired PWM as a combination of the states delivered by T13, the trap control unit and the multi-channel control unit. If the active state is interpreted as a ’1’ and the passive state as a ’0’, the state information is combined with a logical AND function. • active AND active = active • active AND passive = passive • passive AND passive = passive The compare states change with the detected compare-matches and are indicated by the CC6xST bits. The compare states of T12 are defined as follows: • passive if the counter value is below the compare value • active if the counter value is above the compare value This leads to the following switching rules for the compare states: • set to the active state when the counter value reaches the compare value while counting up • reset to the passive state when the counter value reaches the compare value while counting down • reset to the passive state in case of a zero-match without compare-match while counting up • set to the active state in case of a zero-match with a parallel compare-match while counting up T12clk compare-match 2 1 0 active Figure 4-14 2 1 T12 passive compare state Compare States for Compare Value = 2 User’s Manual 4-35 V 0.4, 2002-01 C868 On-Chip Peripheral Components The switching rules are only taken into account while the timer is running. As a result, write actions to the timer registers while the timer is stopped do not lead to compare actions. 4.7.1.4 Duty Cycle of 0% and 100% These counting and switching rules ensure a PWM functionality in the full range between 0% and 100% duty cycle (duty cycle = active time / total PWM period). In order to obtain a duty cycle of 0% (compare state never active), a compare value of T12P+1 has to be programmed (for both compare modes). A compare value of 0 will lead to a duty cycle of 100% (compare state always active). 4.7.1.5 Compare Mode of T12 The following figure shows the setting and resetting of the compare state bit CC6xST. In order to simplify the description, only one out of the three parallel channels is described. The letter ’x’ in the simplified bit names and signal names indicates that there are more than one channel. The CC6xST bit is the compare state bit in register CMPSTAT, the bit CC6xPS represents passive state select bit. The timer T12 generates pulses indicating events like compare-matches, periodmatches and zero-matches, which are used to set (signal T12_xST_se) and to reset (signal T12_xST_re) the corresponding compare state bit (CC6xST) according to the counting direction. The timer T12 modulation output lines T12xO (two for each channel) can be selected to be in the active state while the corresponding compare state is ’0’ (with CC6xPS=’0’) or while the corresponding compare state is ’1’ (with CC6xPS=’1’). The bit COUT6xPS has the same effect for the second output of the channel. The example is shown without dead-time. User’s Manual 4-36 V 0.4, 2002-01 C868 On-Chip Peripheral Components period value compare value T12 0 compare state=0 T12_xST_re =1 =1 =0 T12_xST_se CC6xST CC6x_T12_xO (CC6xPS=0) CC6x_T12_xO (CC6xPS=1) passive active passive active passive active Figure 4-15 Compare States of Timer T12 According to the desired capture/compare mode, the compare state bits have to be switched. Therefore, an additional logic (see Figure 4-16) selects how and by which event the compare state bits are modified. The mode selection (by bitfields MSEL6x in register T12MSEL) enables the setting and the resetting of the compare state bits due to compare actions of timer T12. The HW modifications of the compare state bits is only possible while the timer T12 is running. Therefore, the bit T12R is used to enable/disable the modification by HW. For the hysteresis-like compare mode (MSEL6x=’1001’), the setting of the compare state bit is only possible while the corresponding input CCPOSx=’1’ (inactive). If the Hall Sensor mode (MSEL6x=’1000’) is selected, the compare state bits of the compare channels 1 and 2 are modified by the timer T12 in order to indicate that a programmed time has elapsed. User’s Manual 4-37 V 0.4, 2002-01 C868 On-Chip Peripheral Components T12R T12 T12_xST_se T12_xST_re T12_xST_sen A N D T12_xST_so O R T12 prescaler fper end_of_period in single shot mode AND CCPOSx=’1’ OR A N D T12_xST_ren T12_xST_ro OR MSEL6x= ’0001’ or ’0010’ or ’0011’ or ’1000’ (ch 1, 2 only) MSEL6x= ’1001’ Figure 4-16 T12 Compare Logic The T12 compare output lines T12_xST_so (to set bit CC6xST) and T12_xST_ro (to reset bit CC6xST) are also used to trigger the corresponding interrupt flags and to generate interrupts. The signal T12_xST_so indicates the interrupt event for the rising edge (ICC6xR), whereas the signal T12_xST_ro indicates the falling edge event (ICC6xF) in compare mode. The compare state bits indicate the occurrence of a capture or compare event of the corresponding channel. It can be set (if it is ’0’) by the following events: • upon a software set (CC6xS) • upon a compare set event (see switching rules) if the T12 runs and if the T12 set event is enabled • upon a capture set event The bit CC6xST can be reset (if it is ’1’) by the following events: • upon a software reset (CC6xR) • upon a compare reset event (see switching rules) if the T12 runs and if the T12 reset event is enabled (including in single shot mode the end of the T12 period) • upon a reset event in the hysteresis-like control mode User’s Manual 4-38 V 0.4, 2002-01 C868 On-Chip Peripheral Components hyst_x_state CC6xS T12_xST_so Cap_xST_so T12_xST_ro hyst_x_ev CC6xR OR Hall_edge_o DTCx_rl dead-time generation Figure 4-17 T12 Logic for CC6xST Control CC6xPS A N D 0 1 O R A N D CC6x_ T12_o set CC6xST reset Q Q O R A N D A N D COUT6x_ T12_o 0 1 T12clk DTCx_o COUT6xPS The events triggering the set and reset action of the CC6xST bits have to be combined, see Figure 4-17. The occurrence of the selected capture event (signal Cap_xST_so) or the setting of CC6xS in register CMPMODIF also leads to a set action of bit CC6xST, whereas the negative edge at pin CCPOSx (in hysteresis-like mode, signal hyst_x_ev) or the setting of bit CC6xR leads to reset action. The set signal is only generated while bit CC6xST is reset, a reset can only take place while the bit is set. This permits the OR-combination of the resulting set and reset signals to one common signal (DTCx_rl) triggering the reload of the dead-time counter. It is only triggered if bit CC6xST is changed, permitting a correct PWM generation with dead-time and the complete duty cycle range of 0% to 100% in edge-aligned and in center-aligned mode. In the case that the dead-time generation is enabled, the change of bit CC6xST triggers the dead-time unit and a signal DTCx_o is generated. The length of the ’0’ level of this signal corresponds to the desired dead-time, which is used to delay the rising edge (passive to active edge) of the output signal. In order to generate independent PWM patterns for the highside and the lowside switches of the power inverter, the interval when a PWM signal should be active can be selected by the bits CC6xPS. They select if the PWM signal is active while the compare state bit is ’0’ (T12 counter value below the compare value) or while it is ’1’ (T12 counter value above the compare value). User’s Manual 4-39 V 0.4, 2002-01 C868 On-Chip Peripheral Components In Figure 4-17, the signals CC6x_T12_o and COUT6x_T12_o are inputs to the modulation control block, where they can be combined with other PWM signals. 4.7.1.6 Switching Examples in edge-aligned Mode The following figure shows two switching examples in edge-aligned mode with duty cycles near to 0% and near to 100%. The compare-, period- or zero-matches lead to modifications of the compare state and the shadow transfer (if requested by STE12=’1’) in the next clock cycle. T12clk T12P T12P-1 T12P-2 compare-match = period-match zero-match 1 0 0 1 < T12P-3 active T12 shadow transfer 0 0 1 T12P passive 0 0 T12P active 0 CDIR STE12 CC6x compare state T12P-1 T12P-2 compare-match = period-match zero-match 1 T12 T12P T12 shadow transfer Figure 4-18 Switching Examples in edge-aligned Mode 4.7.1.7 Switching Examples in center-aligned Mode The following figures show examples of the switching of the compare state and the T12 shadow transfer according to the programmed compare values. User’s Manual 4-40 V 0.4, 2002-01 C868 On-Chip Peripheral Components T12clk compare-match 2 1 0 1 1 1 active 0 0 2 passive T12 shadow transfer active T12 shadow transfer 1 1 1 1 2 2 1 0 0 0 0 CDIR STE12 CC6x compare state 1 compare-match 2 T12 Figure 4-19 Switching Example for Duty Cycles near to 100% T12clk T12P+1 T12P T12P-1 compare-match 0 1 T12P-1 passive active T12 shadow transfer 1 0 T12P 0 1 T12P passive active T12 shadow transfer compare-match 1 0 T12P+1 CDIR STE12 CC6x compare state T12P+1 T12P T12 T12P-1 Figure 4-20 Switching Example for Duty Cycles near to 0% 4.7.1.8 Dead-time Generation The generation of (complementary) signals for the highside and the lowside switches of one power inverter phase is based on the same compare channel. For example, if the User’s Manual 4-41 V 0.4, 2002-01 C868 On-Chip Peripheral Components highside switch should be active while the T12 counter value is above the compare value (compare state =’1’), then the lowside switch should be active while the counter value is below (compare state =’0’). The compare state, which may lead to an active output (respecting other modulation sources and the trap functionality) can be selected by the CC6xPS bits. T12 CC6xST CC6xST DTCx_o CC6xST AND DTCx_o CC6xST AND DTCx_o CC6xPS 1 CC6x_T12_o 0 COUT6xPS 1 COUT6x_T12_o 0 Figure 4-21 PWM-signals with Dead-time Generation In most cases, the switching behavior of the connected power switches is not symmetrical concerning the times needed to switch on and to switch off. A general problem arises if the time to switch on is smaller than the time to switch off the power device. In this case, a short-circuit in the inverter bridge leg occurs, which may damage the complete system. In order to solve this problem by HW, this capture/compare unit contains a programmable dead-time counter, which delays the passive to active edge of the switching signals (the active to passive edge is not delayed), see Figure 4-21. The dead-time generation logic (see Figure 4-22) is built in a similar way for all three channels of T12. Each change of the CC6xST bits triggers the corresponding dead-time counter (6 bit down counter, clocked with T12clk). The trigger pulse (DTCx_rl) leads to a reload of the dead-time counter with the value, which has been programmed in bit field User’s Manual 4-42 V 0.4, 2002-01 C868 On-Chip Peripheral Components DTM. This reload can only take place if the dead-time feature is enabled by bit DTEx and while the counter is zero. While counting down (zero is not yet reached), the output line DTCx_o becomes ’0’. This output line is combined with the T12 modulation signals, leading to a delay of the passive to active edge of the resulting signal, which is shown in Figure 4-21. When reaching the counter value zero, the dead-time counter stops counting and the signal DTCx_o becomes ’1’. The dead-time counter can not be reloaded while it is counting. DTC2_rl DTC1_rl DTC0_rl DTM 6 6 6 channel 2 channel 1 channel 0 (channel 0 only) DTE0 A N D DTC0_1o 6 bit down-counter T12clk =0 =1 DTC2_o DTC1_o DTC0_o Figure 4-22 Dead-time Counter Each of the three channels works independently with its own dead-time counter and the trigger and enable signals. The value of bit field DTM is valid for all of the three channels. In the Hall sensor mode, timer T12 is used to measure the rotational speed of the motor (channel 0 in capture mode) and to control the phase delay before switching to the next state (channel 1 in compare mode). Furthermore, channel 2 can be used to generate a time-out signal (in compare mode). As a result, T12 can not be used for modulation and, due to the block commutation patterns, a dead-time generation is not required. In order to built an efficient noise filter for the Hall signals, channel 0 of the dead-time unit is triggered (reloaded) with each detected edge of the Hall signals, see signal Hall_edge_o in Figure 4-17. For this feature, channel 0 also generates a pulse if its counter value is one. 4.7.1.9 Capture Mode In capture mode the bits CC6xST indicate the occurrence of the selected capture event according to the bit fields MSEL6x. A rising and/or a falling edge on the pins CC6x can User’s Manual 4-43 V 0.4, 2002-01 C868 On-Chip Peripheral Components be selected as capture event, that is used to transfer the contents of timer T12 to the CC6xR and CC6xSR registers. In order to work in capture mode, the capture pins have to be configured as inputs. CC6x_in fper in R edge detection Capt_fe F Capt_re function select tr_T_R tr_T_SR tr_SR_R MSEL6x Figure 4-23 Capture Logic The block diagram of the capture logic for one channel is shown in Figure 4-23. This logic is identical for all three independent channels of timer T12. The input signal (CC6x_in) from the input pin CC6x is connected to an edge detection logic delivering two output signals, one for the rising edge (Capt_re) and one for the falling edge (Capt_fe). These signals are also used as trigger sources for the channel interrupts if capture mode is selected. There are several possibilities to store the captured values in the registers. In double register capture mode the timer value is stored in the channel shadow register CC6xSR. The value formerly stored in this register is simultaneously copied to the channel register CC6xR.This mode can be used if two capture events occur with very few time between them. The SW can then check the new captured value and has still the possibility to read the value captured before. The selection of the capture mode is done by bitfield MSEL6x. According to the selected mode and the detected capture event, the signals tr_T_R (transfer T12 contents to register CC6xR), tr_T_SR (transfer T12 contents to register CC6xSR) or tr_SR_R (transfer contents of CC6xSR to register CC6xR) are activated. Note: In capture mode, a shadow transfer can be requested according to the shadow transfer rules, except for the capture / compare registers, that are left unchanged. 4.7.1.10 Single Shot Mode In single shot mode, the timer T12 stops automatically at the end of the its counting period. Figure 4-24 shows the functionality at the end of the timer period in edge-aligned User’s Manual 4-44 V 0.4, 2002-01 C868 On-Chip Peripheral Components and in center-aligned mode. If the end of period event is detected while bit T12SSC is set, the bits T12R and all CC6xST bits are reset. edge-aligned mode T12P T12P-1 T12P-2 period-match while counting up center-aligned mode if T12SSC = ’1’ 0 T12 T12R CC6xST Figure 4-24 End of Single Shot Mode of T12 2 1 if T12SSC = ’1’ one-match while counting down 0 T12 T12R CC6xST User’s Manual 4-45 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.7.1.11 Hysteresis-Like Control Mode The hysteresis-like control mode (MSEL6x = ’1001’) offers the possibility to switch off the PWM output if the input CCPOSx becomes ’0’ by resetting bit CC6xST. This can be used as a simple motor control feature by using a comparator indicating e.g. over current. While CCPOSx=’0’, the PWM outputs of the corresponding channel are driving their passive levels. The setting of bit CC6xST is only possible while CCPOSx=’1’. OR CCPOSx fper in R edge detection F hyst_x_state AND hyst_x_ev MSEL6x= ’1001’ Figure 4-25 Hysteresis-Like Control Mode Logic User’s Manual 4-46 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.7.2 4.7.2.1 Timer T13 Overview The timer T13 is built similar to T12, but only with one channel in compare mode. The counter can only count up (similar to the edge-aligned mode of T12). The T13 shadow transfer in case of a period-match is enabled by bit STE13 in register TCTR0. During the T13 shadow transfer, the contents of register CC63SR is transferred to register CC63R. Both registers can be read by SW, whereas only the shadow register can be written by SW. The bits CC63PS, T13IM and PSL63 have shadow bits. The contents of the shadow bits is transferred to the actually used bits during the T13 shadow transfer. Write actions target the shadow bits, read actions deliver the value of the actually used bit. =0? =? 16 zero-match period-match T13PR compare-match 16 T13PS T13 shadow transfer CC63SR =? CC63R counter register T13 16 T13clk Figure 4-26 T13 Overview Timer T13 counts according to the same counting and switching rules as timer T12 in edge-aligned mode. User’s Manual 4-47 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.7.2.2 Compare Mode The compare structure of T13 is based on the compare signals T13_ST_se (compare match detected) and T13_ST_re (zero-match detected without compare-match). These compare signals may modify bit CC63ST only while the timer is running (T13R=’1’). T13R T13 T13_ST_se T13_ST_re A N D O R A N D T13_ST_so T13_ST_ro T13 prescaler fper Figure 4-27 T13 Compare Logic end_of_period in single shot mode Similar to T12, bit CC63ST can be modified by SW by bits CC63S and CC63R. The output line COUT63_T13_o can generate a T13 PWM at the output pin COUT63. The signal MOD_T13_o can be used to modulate the other output signals with a T13 PWM. In order to decouple COUT63 from the internal modulation, the compare state leading to an active signal can be selected independently by bits T13IM and COUT63PS. User’s Manual 4-48 V 0.4, 2002-01 C868 On-Chip Peripheral Components CC63S O R T13_ST_so T13_ST_ro O R CC63R A N D T13IM set CC63ST reset Q Q 0 1 MOD_ T13_o A N D COUT63_ T13_o 0 1 COUT63PS Figure 4-28 T13 Logic for CC6xST Control 4.7.2.3 Single Shot Mode The single shot mode of T13 is similar to the single shot mode of T12 in edge-aligned mode. 4.7.2.4 Synchronization of T13 to T12 The timer T13 can be synchronized on a T12 event. The bit fields T13TEC and T13TED select the event, which is used to start timer T13. This event sets bit T13R per HW and T13 starts counting. Combined with the single shot mode, this feature can be used to generate a programmable delay after a T12 event. User’s Manual 4-49 V 0.4, 2002-01 C868 On-Chip Peripheral Components 5 compare-match while counting up T12 0 2 T13 T13R 1 0 2 1 4 3 Figure 4-29 Synchronization of T13 to T12 This figure shows the synchronization of T13 to a T12 event. The selected event in this example is a compare-match (compare value = 2) while counting up. The clocks of T12 and T13 can be different (other prescaler factor), but for reasons of simplicity, this example shows the case for T12clk equal to T13clk. 4.7.3 Multi-channel Mode The multi-channel mode offers a possibility to modulate all six T12-related output signals within one instruction. The bits in bit field MCMP are used to select the outputs that may become active. If the multi-channel mode is enabled (bit MCMEN=’1’), only those outputs may become active, which have a ’1’ at the corresponding bit position in bit field MCMP. This bit field has its own shadow bit field MCMPS, which can be written by SW. The transfer of the new value in MCMPS to the bit field MCMP can be triggered by and synchronized to T12 or T13 events. This structure permits the SW to write the new value, which is then taken into account by the HW at a well-defined moment and synchronized to a PWM period. This avoids unintended pulses due to unsynchronized modulation sources (T12, T13, SW). User’s Manual 4-50 V 0.4, 2002-01 C868 On-Chip Peripheral Components SW SEL Correct Hall Event T13pm T12pm T12om T12c1cm no action T12zm write to bitfield MCMPS with STRMCM = ’1’ Figure 4-30 O R set write by software 6 MCMPS reset R O R A N D MCMP clear 6 T13zm direct SW SYN to modulation selection IDLE Modulation Selection and Synchronization Figure 4-30 shows the modulation selection for the multi-channel mode. The event that triggers the update of bit field MCMP is chosen by SWSEL. If the selected switching event occurs, the reminder flag R is set. This flag monitors the update request and it is automatically reset when the update takes place. In order to synchronize the update of MCMP to a PWM generated by T12 or T13, bit field SWSYN allows the selection of the synchronization event, which leads to the transfer from MCMPS to MCMP. Due to this structure, an update takes place with a new PWM period. If it is explicitly desired, the update takes place immediately with the setting of flag R when the direct synchronization mode is selected. The update can also be requested by SW by writing to bit field MCMPS with the shadow transfer request bit STRMCM set. If this bit is set during the write action to the register, the flag R is automatically set. By using the direct mode and bit STRMCM, the update takes place completely under SW control. The possible HW request events are: • a T12 period-match while counting up (T12pm) • a T12 one-match while counting down (T12om) • a T13 period-match (T13pm) User’s Manual 4-51 V 0.4, 2002-01 C868 On-Chip Peripheral Components • a T12 compare-match of channel 1 (T12c1cm) • a correct Hall event The possible HW synchronization events are: • a T12 zero-match while counting up (T12zm) • a T13 zero-match (T13zm) • 4.7.4 Trap Handling The trap functionality permits the PWM outputs to react on the state of the input pin CTRAP. This functionality can be used to switch off the power devices if the trap input becomes active (e.g. as emergency stop). During the trap state, the selected outputs are forced to the passive state and no active modulation is possible. The trap state is entered immediately by HW if the CTRAP input signal becomes active and the trap function is enabled by bit TRPPEN. It can also be entered by SW by setting bit TRPF (trap input flag), leading to TRPS=’1’ (trap state indication flag). The trap state can be left when the input is inactive, by SW control and synchronized to the following events: • TRPF is automatically reset after CTRAP becomes inactive (if TRPM2=’0’) • TRPF has to be reset by SW after CTRAP becomes inactive (if TRPM2=’1’) • synchronized to T12 PWM after TRPF is reset (T12 period-match in edge-aligned mode or one-match while counting down in centeraligned mode) • synchronized to T13 PWM after TRPF is reset (T13 period-match) • no synchronization to T12 or T13 User’s Manual 4-52 V 0.4, 2002-01 C868 On-Chip Peripheral Components T12 T13 TRPF TRPS TRPS TRPS Figure 4-31 CTRAP active sync. to T13 sync. to T12 no sync. Trap State Synchronization (with TRM2=’0’) 4.7.5 Modulation Control The modulation control part combines the different modulation sources (CC6x_T12_o, COUT6x_T12_o = six T12-related signals from the three compare channels), the T13related signal (MOD_T13_o) and the multi-channel modulation signals (MCMP bits). each modulation source can be individually enabled for each output line. Furthermore, the trap functionality is taken into account to disable the modulation of the corresponding output line during the trap state (if enabled). User’s Manual 4-53 V 0.4, 2002-01 C868 On-Chip Peripheral Components OR T12MODENx CC6x_T12_o, COUT6x_T12_o T13MODENx O R MOD_T13_o MCMEN O R MCMPx 1 0 O R 0 = passive state 1 = active state A N D to output pin CC6x, COUT6x TRPENx TRPS A N D PSLx (1 x for each T12-related output) Figure 4-32 Modulation Control of T12-related Outputs The logic shown in Figure 4-32 has to be built separately for each of the six T12-related output lines, referring to the index ’x’ in the figure above. The output level, that is driven while the output is in the passive state is defined by the corresponding bit in bit field PSL. If the resulting modulation signal is active, the inverted level of the PLSx bit is driven by the output stage. The modulation control part for the T13-related output COUT63 combines the T13 output signal (COUT63_T13_o) and the enable bit ECT13O with the trap functionality. The output level of the passive state is selected by bit PSL63. User’s Manual 4-54 V 0.4, 2002-01 C868 On-Chip Peripheral Components ECT13O COUT63_T13_o TRPEN13 TRPS Figure 4-33 A N D A N D 0 = passive state 1 = active state 1 0 A N D to output pin COUT63 PSL63 Modulation Control of the T13-related Output COUT63 Note: In order to avoid spikes on the output lines, the seven output signals (CC60, COUT60, CC61, COUT61, CC62, COUT62, COUT63) are registered out with the peripheral clock. 4.7.6 Hall Sensor Mode In Brushless-DC motors the next multi-channel state values depend on the pattern of the Hall inputs. There is a strong correlation between the Hall pattern (CURH) and the modulation pattern (MCMP). Because of different machine types the modulation pattern for driving the motor can be different. Therefore it is wishful to have a wide flexibility in defining the correlation between the Hall pattern and the corresponding modulation pattern. The CCU6 offers this by having a register which contains the actual Hall pattern (CURHS), the next expected Hall pattern (EXPHS) and its output pattern (MCMPS). At every correct Hall event (CHE, see figure Hall Event Actions) a new Hall pattern with its corresponding output pattern can be loaded (from a predefined table) by software into the register MCMOUTS. Loading this shadow register can also be done by a write action on MCMOUTS with bit STRHP = ’1’. The sampling of the Hall pattern (on CCPOSx) is done with the T12 clock. By using the dead-time counter DTC0 (mode MSEL6x= ’1000’) a hardware noise filter can be implemented to suppress spikes on the Hall inputs due to high di/dt in rugged inverter environment. In case of a Hall event the DTC0 is reloaded and starts counting. When the counter value of one is reached, the CCPOSx inputs are sampled (without noise and spikes) and are compared to the current Hall pattern (CURH) and to the expected Hall pattern (EXPH). If the sampled pattern equals to the current pattern the edge on CCPOSx was due to a noise spike and no action will be triggered (implicit noise filter). If User’s Manual 4-55 V 0.4, 2002-01 C868 On-Chip Peripheral Components the sampled pattern equals to the next expected pattern the edge on CCPOSx was a correct Hall event, the bit CHE is set which causes an interrupt and the resets T12 (for speed measurement, see description mode ’1000’ below). This correct Hall event can be used as a transfer request event for register MCMOUTS. The transfer from MCMOUTS to MCMOUT transfers the new CURH-pattern as well as the next EXPH-pattern. In case of the sampled Hall inputs were neither the current nor the expected Hall pattern, the bit WHE (wrong Hall event) is set which also can cause an interrupt and sets the IDLE mode clearing MCMP (modulation outputs are inactive). To restart from IDLE the transfer request of MCMOUTS have to be initiated by software (bit STRHP and bitfields SWSEL/SWSYN). write by software 6 STRHP ENIDLE CURHS EXPHS OR AND set IDLE CURH 3 EXPH 3 DTC0_1o = = N O R A N D WHEEN sampled Hall pattern reset_T12 3 O int_event R A N D set set AND MSEL6x= ’1000’ CHEEN CHE Correct Hall Event WHE Wrong Hall Event Figure 4-34 Hall Logic User’s Manual 4-56 V 0.4, 2002-01 C868 On-Chip Peripheral Components For Brushless-DC motors there is a special mode (MSEL6x = ’1000b’) which is triggered by a change of the Hall-inputs (CCPOSx). This mode shows the capabilities of the CCU6 (see also figures Multi-channel Selection and Synchronization, Hall Event Actions, Modulation Selection and Alternate Output Enable of T12 and Timer T12 Brushless-DC Mode). Here T12’s channel 0 acts in capture function, channel 1 and 2 in compare function (without output modulation) and the multi-channel-block is used to trigger the output switching together with a possible modulation of T13. After the detection of a valid Hall edge the T12 count value is captured to channel 0 (representing the actual motor speed) and resets the T12. When the timer reaches the compare value in channel 1, the next multi-channel state is switched by triggering the shadow transfer of bit field MCMP (if enabled in bit field SWEN). This trigger event can be combined with several conditions which are necessary to implement a noise filtering (correct Hall event) and to synchronize the next multi-channel state to the modulation sources (avoiding spikes on the output lines). This compare function of channel 1 can be used as a phase delay for the position input to the output switching which is necessary if a sensorless back-EMF technique is used instead of Hall sensors. The compare value in channel 2 can be used as a time-out trigger (interrupt) indicating that the motors destination speed is far below the desired value which can be caused by a abnormal load change. In this mode the modulation of T12 has to be disabled (T12MODENx = ’0’). CC60 act. speed CC61 phase delay ch0 gets captured value for act. speed ch2 compare for timeout CC62 timeout capture event resets T12 1 0 1 1 0 0 1 1 0 0 1 0 0 1 1 ch1 compare for phase delay CCPOS0 CCPOS1 CCPOS2 CC6x COUT6y 0 0 1 Figure 4-35 Timer T12 Brushless-DC Mode (MSEL6x = 1000) User’s Manual 4-57 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.7.7 Interrupt Generation The interrupt structure is shown in Figure 4-36. The interrupt event or the corresponding interrupt set bit (in register ISS) can trigger the interrupt generation. The interrupt pulse is generated independently from the interrupt flag in register IS. The interrupt flag can be reset by SW by writing to the corresponding bit in register ISR. If enabled by the related interrupt enable bit in register IEN, an interrupt pulse can be generated at one of the four interrupt output lines of the module (length 2 clock cycles). If more than one interrupt source is connected to the same interrupt node pointer (in register INP), the requests are combined to one common line. int_reset_SW int_event int_set_SW int_enable O R int_flag INP to I0 A N D O R to I1 to I2 to I3 other interrupt sources on the same INP Figure 4-36 Interrupt Generation 4.7.8 Module Powerdown The CCU6 is disabled when the chip goes into the powerdown mode as describe in . Or it can be individually disabled by setting CCUDIS in register PMCON1. This helps to reduce current consumption in the normal, slow down and idle modes of operation if the CCU6 is not utilized. Bit CCUST in register PMCON2 reflects the powerdown status of CCU6. User’s Manual 4-58 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.8 4.8.1 4.8.2 Kernel Description Register Overview Timer12 - Related Registers The generation of the patterns for a 3-channel pulse width modulation (PWM) is based on timer T12. The registers related to timer T12 can be concurrently updated (with welldefined conditions) in order to ensure consistency of the three PWM channels. Timer T12 supports capture and compare modes, which can be independently selected for the three channels CC60, CC61 and CC62. Register T12 represents the counting value of timer T12. It can only be written while the timer T12 is stopped. Write actions while T12 is running are not taken into account. Register T12 can always be read by SW. In edge-aligned mode, T12 only counts up, whereas in center-aligned mode, T12 can count up and down. T12L Timer T12 Counter Register, Low Byte 7 6 5 4 T12CV7..0 rwh 3 2 [Reset value: 00H] 1 0 T12H Timer T12 Counter Register, High Byte 7 6 5 4 3 2 [Reset value: 00H] 1 0 T12CV15..8 rwh Field T12CV Bits Typ Description [7:0] of rwh Timer 12 Counter Value T12 This register represents the 16-bit counter value of CVL, Timer12. [7:0] of T12 CVH 4-59 V 0.4, 2002-01 User’s Manual C868 On-Chip Peripheral Components Note: While timer T12 is stopped, the internal clock divider is reset in order to ensure reproducible timings and delays. Note: The timer period, compare values, passive state selects bits and passive levels bits for both timers are written to shadow registers and not directly to the actual registers. Thus the values for a new output signal can be programmed without disturbing the currently generated signal(s). The transfer from the shadow registers to the actual registers is enabled by setting the respective shadow transfer enable bit STEx. If the transfer is enabled the shadow registers are copied to the respective registers as soon as the associated timer reaches the value zero the next time (being cleared in edge aligned mode or counting down from 1 in center aligned mode). When timer T12 is operating in center aligned mode, it will also copy the registers (if enabled by STE12) if it reaches the currently programmed period value (counting up). When a timer is stopped (TxR=’0’), the shadow transfer takes place immediately if the corresponding bit STEx is set. After the transfer the respective bit STEx is cleared automatically. User’s Manual 4-60 V 0.4, 2002-01 C868 On-Chip Peripheral Components Register T12PR contains the period value for timer T12. The period value is compared to the actual counter value of T12 and the resulting counter actions depend on the defined counting rules. This register has a shadow register and the shadow transfer is controlled by bit STE12. A read action by SW delivers the value which is currently used for the compare action, whereas the write action targets a shadow register. The shadow register structure allows a concurrent update of all T12-related values. T12PRL Timer T12 Period Register, Low Byte 7 6 5 4 T12PV7..0 rwh 3 2 [Reset value: 00H] 1 0 T12PRH Timer T12 Period Register, High Byte 7 6 5 4 3 2 [Reset value: 00H] 1 0 T12PV15..8 rwh Field T12PV Bits Typ Description [7:0] of rwh T12 Period Value T12 The value T12PV defines the counter value for T12, PRL, which leads to a period-match. When reaching this [7:0] of value, the timerT12 is set to zero (edge-aligned T12 mode) or changes its count direction to down PRH counting (center-aligned mode). User’s Manual 4-61 V 0.4, 2002-01 C868 On-Chip Peripheral Components In compare mode, the registers CC6xR (x=0,1,2) are the actual compare registers for T12. The values stored in CC6xR are compared (all three channels in parallel) to the counter value of T12. In capture mode, the current value of the T12 counter register is captured by registers CC6xR if the corresponding capture event is detected. The registers CC6xR can only be read by SW, the modification of the value is done by a shadow register transfer from register CC6xSR. The corresponding shadow registers CC6xSR can be read and written by SW. In capture mode, the value of the T12 counter register can also be captured by registers CC6xSR if the selected capture event is detected (depending on the selected mode). CC6xRL (x=0,1,2) Capture/Compare Register for Channel CC6x, Low Byte 7 6 5 4 3 2 [Reset value: 00H] 1 0 CC6xV7..0(X=0,1,2) rh CC6xRH (X=0,1,2) Capture/Compare Register for Channel CC6x, High Byte 7 6 5 4 3 2 [Reset value: 00H] 1 0 CC6xV15..8(X=0,1,2) rh Field Bits Typ Description Shadow Register for Channel x Capture/ Compare Value In compare mode, the bitfields contents of CC6xS are transferred to the bitfields CC6xV during a shadow transfer. In capture mode, the captured value of T12 can be read from these registers. CC6xV (x=0, 1, 2) [7:0] of rh CC6x RL, [7:0] of CC6x RH User’s Manual 4-62 V 0.4, 2002-01 C868 On-Chip Peripheral Components CC6xSRL (x=0,1,2) Capture/Compare Shadow Register for Channel CC6x, Low Byte[Reset value: 00H] 7 6 5 4 3 2 1 0 CC6xS7..0(X=0,1,2) rwh CC6xSRH (x=0,1,2) Capture/Compare Shadow Register for Channel CC6x, High Byte[Reset value:00H] 7 6 5 4 3 2 1 0 CC6xS15..8(X=0,1,2) rwh Field Bits Typ Description CC6xS (x=0, 1, 2) [7:0] of rwh Shadow Register for Channel x Capture/ CC6x Compare Value SL, In compare mode, the bitfields contents of CC6xS [7:0] of are transferred to the bitfields CC6xV during a CC6x shadow transfer. In capture mode, the captured SH value of T12 can be read from these registers. User’s Manual 4-63 V 0.4, 2002-01 C868 On-Chip Peripheral Components Register T12DTC controls the dead-time generation for the timer T12 compare channels. Each channel can be independently enabled/disabled for dead-time generation. If enabled, the transition from passive state to active state is delayed by the value defined by bit field DTM. The dead-time counter can only be reloaded while it is zero. T12DTCL Timer T12 Dead-Time Control Register,Low Byte 7 r 6 r 5 4 3 DTM rw 2 [Reset value: 00H] 1 0 Field DTM Bits [5:0] Typ Description rw Dead-Time Bit field DTM determines the programmable delay between switching from the passive state to the active state of the selected outputs. The switching from the active state to the passive state is not delayed. reserved; returns ’0’ if read; should be written with ’0’; - [7:6] r User’s Manual 4-64 V 0.4, 2002-01 C868 On-Chip Peripheral Components T12DTCH Timer T12 Dead-Time Control Register,High Byte 7 r 6 5 DTR rh 4 3 r 2 [Reset value: 00H] 1 DTE rw 0 Field DTE Bits [2:0] Typ Description rw Dead Time Enable Bits Bits DTE0..DTE2 enable and disable the dead time generation for each compare channel (0, 1, 2) of timer T12. 0Dead time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay. 1Dead time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bitfield DTM. Dead Time Run Indication Bits Bits DTR0..DTR2 indicate the status of the dead time generation for each compare channel (0, 1, 2) of timer T12. 0The value of the corresponding dead time counter channel is 0. 1The value of the corresponding dead time counter channel is not 0. reserved; returns ’0’ if read; should be written with ’0’; DTR [6:4] rh - 7,3 r Note: The dead time counters are clocked with the same frequency as T12. This structure allows symmetrical dead time generation in center-aligned and in edge-aligned PWM mode. A duty cycle of 50% leads to CC6x, COUT6x switched on for: 0.5 * period - dead time. Note: The dead-time counters are not reset by bit T12RES, but by bit DTRES. User’s Manual 4-65 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.8.3 Timer13 - Related Registers The generation of the patterns for a single channel pulse width modulation (PWM) is based on timer T13. The registers related to timer T13 can be concurrently updated (with well-defined conditions) in order to ensure consistency of the PWM signal. T13 can be synchronized to several timer T12 events. Timer T13 only supports compare mode on its compare channel CC63. Register T13 represents the counting value of timer T13. It can only be written while the timer T13 is stopped. Write actions while T13 is running are not taken into account. Register T13 can always be read by SW. Timer T13 only supports edge-aligned mode (counting up). T13L Timer T13 Counter Register, Low Byte 7 6 5 4 T13CV7..0 rwh 3 2 [Reset value: 00H] 1 0 T13H Timer T13 Counter Register, High Byte 7 6 5 4 3 2 [Reset value: 00H] 1 0 T13CV15..8 rwh Field T13CV Bits Typ Description [7:0] of rwh Timer 13 Counter Value T13L, This register represents the 16-bit counter value of [7:0] of Timer13. T13H Note: While timer T13 is stopped, the internal clock divider is reset in order to ensure reproducible timings and delays. User’s Manual 4-66 V 0.4, 2002-01 C868 On-Chip Peripheral Components Register T13PR contains the period value for timer T13. The period value is compared to the actual counter value of T13 and the resulting counter actions depend on the defined counting rules. This register has a shadow register and the shadow transfer is controlled by bit STE13. A read action by SW delivers the value which is currently used for the compare action, whereas the write action targets a shadow register. The shadow register structure allows a concurrent update of all T13-related values. T13PRL Timer T13 Period Register, Low Byte 7 6 5 4 T13PV7..0 rwh 3 2 [Reset value: 00H] 1 0 T13PRH Timer T13 Period Register, High Byte 7 6 5 4 3 2 [Reset value: 00H] 1 0 T13PV15..8 rwh Field T13PV Bits Typ Description [7:0] of rwh T13 Period Value T13L, The value T13PV defines the counter value for T13, [7:0] of which leads to a period-match. When reaching this T13H value, the timer T13 is set to zero. User’s Manual 4-67 V 0.4, 2002-01 C868 On-Chip Peripheral Components Registers CC63R is the actual compare register for T13. The values stored in CC63R is compared to the counter value of T13. The register CC63R can only be read by SW, the modification of the value is done by a shadow register transfer from register CC63SR. The corresponding shadow register CC63SR can be read and written by SW. CC63RL Compare Register for Channel CC63, Low Byte 7 6 5 4 3 2 [Reset value: 00H] 1 0 CC63V7..0 rh CC63RH Compare Register for Channel CC63, High Byte 7 6 5 4 3 2 [Reset value: 00H] 1 0 CC63V15..8 rh Field CC63V Bits Typ Description Channel CC63 Compare Value The bitfield CC63V contains the value, that is compared to the T13 counter value. [7:0] of rh CC63 RL, [7:0] of CC63 RH User’s Manual 4-68 V 0.4, 2002-01 C868 On-Chip Peripheral Components CC63SRL Compare Shadow Register for CC63, Low Byte 7 6 5 4 3 2 [Reset value: 00H] 1 0 CC63S7..0 rw CC63SRH Compare Shadow Register for CC63, High Byte 7 6 5 4 3 2 [Reset value: 00H] 1 0 CC63S15..8 rw Field CC63S Bits Typ Description Shadow Register for Channel CC63 Compare Value The bitfield contents of CC63S is transferred to the bitfield CC63V during a shadow transfer. [7:0] of rw CC63 SRL, [7:0] of CC63 SRH User’s Manual 4-69 V 0.4, 2002-01 C868 On-Chip Peripheral Components Capture/Compare Control Registers The Compare State Register CMPSTAT contains status bits monitoring the current capture and compare state and control bits defining the active/passive state of the compare channels. CMPSTATL Compare State Register,Low Byte 7 r 6 CC63ST rh 5 r 4 r 3 r 2 CC62ST rh [Reset value: 00H] 1 CC61ST rh 0 CC60ST rh Field CC60ST CC61ST CC62ST CC63ST 1) Bits 0 1 2 6 Typ Description rh Capture/Compare State Bits Bits CC6xST monitor the state of the capture/ compare channels. Bits CC6xST (x=0, 1, 2) are related to T12, bit CC63ST is related to T13. 0 In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by SW the last time. 1 In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. reserved; returns ’0’ if read; should be written with ’0’; - [5:3], 7 r 1) These bits are set and reset according to the T12, T13 switching rules CMPSTATH Compare State Register,High Byte 7 T13IM rwh 6 COUT 63PS rwh 5 COUT 62PS rwh 4 CC62PS rwh 3 COUT 61PS rwh 2 CC61PS rwh [Reset value: 00H] 1 COUT 60PS rwh 0 CC60PS rwh User’s Manual 4-70 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field CC60PS CC61PS CC62PS COUT60PS COUT61PS COUT62PS COUT63PS 1) Bits 0 2 4 1 3 5 6 Typ Description rwh Passive State Select for Compare Outputs Bits CC6xPS, COUT6xPS select the state of the corresponding compare channel, which is considered to be the passive state. During the passive state, the passive level (defined in register PSLR) is driven by the output pin. Bits CC6xPS, COUT6xPS (x=0, 1, 2) are related to T12, bit CC63PS is related to T13. 0 The corresponding compare output drives passive level while CC6xST is ’0’. 1 The corresponding compare output drives passive level while CC6xST is ’1’. In capture mode, these bits are not used. rwh T13 Inverted Modulation Bit T13IM inverts the T13 signal for the modulation of the CC6x and COUT6x (x = 0, 1, 2) signals. 0 T13 output is not inverted. 1 T13 output is inverted for further modulation. T13IM2) 7 1) These bits have shadow bits and are updated in parallel to the capture/compare registers of T12, T13 respectively. A read action targets the actually used values, whereas a write action targets the shadow bits. 2) This bit has a shadow bit and is updated in parallel to the compare and period registers of T13. A read action targets the actually used values, whereas a write action targets the shadow bit. User’s Manual 4-71 V 0.4, 2002-01 C868 On-Chip Peripheral Components The Compare Status Modification Register contains control bits allowing for modification by SW of the Capture/Compare state bits. CMPMODIFL Compare State Modification Register,Low Byte 7 r 6 MCC63S w 5 r 4 r 3 r 2 MCC62S w [Reset value: 00H] 1 MCC61S w 0 MCC60S w Field MCC60S MCC61S MCC62S MCC63S Bits 0 1 2 7 Typ Description w Capture/Compare Status Modification Bits These bits are used to set (MCC6xR) the corresponding bits CC6xST by SW. This feature allows the user to individually change the status of the output lines by SW, e.g. when the corresponding compare timer is stopped. This allows a bit manipulation of CC6xST-bits by a single data write action. The following functionality of a write access to bits concerning the same capture/compare state bit is provided: MCC6xR(CMPMODIFH), MCC6xS = 0,0 Bit CC6xST is not changed. 0,1 Bit CC6xST is set. 1,0 Bit CC6xST is reset. 1,1 reserved (toggle) reserved; returns ’0’ if read; should be written with ’0’; - [5:3], 7 r CMPMODIFH Compare State Modification Register,High Byte 7 r 6 MCC63R w 5 r 4 r 3 r 2 MCC62R w [Reset value: 00H] 1 MCC61R w 0 MCC60R w User’s Manual 4-72 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field MCC60R MCC61R MCC62R MCC63R Bits 0 1 2 7 Typ Description w Capture/Compare Status Modification Bits These bits are used to reset (MCC6xR) the corresponding bits CC6xST by SW. This feature allows the user to individually change the status of the output lines by SW, e.g. when the corresponding compare timer is stopped. This allows a bit manipulation of CC6xST-bits by a single data write action. The following functionality of a write access to bits concerning the same capture/compare state bit is provided: MCC6xR, MCC6xS(CMPMODIFL) = 0,0 Bit CC6xST is not changed. 0,1 Bit CC6xST is set. 1,0 Bit CC6xST is reset. 1,1 reserved (toggle) reserved; returns ’0’ if read; should be written with ’0’; - [5:3], 7 r User’s Manual 4-73 V 0.4, 2002-01 C868 On-Chip Peripheral Components Register TCTR0 controls the basic functionality of both timers T12 and T13. TCTR0L Timer Control Register 0,Low Byte 7 CTM rw 6 CDIR rh 5 STE12 rh 4 T12R rh 3 T12PRE rw 2 [Reset value: 00H] 1 T12CLK rw 0 Field T12CLK Bits [2:0] Type Description rw Timer T12 Input Clock Select Selects the input clock for timer T12 which is derived from the peripheral clock according to the equation fT12 = fper / 2. 000 fT12 = fper 001 fT12 = fper / 2 010 fT12 = fper / 4 011 fT12 = fper / 8 100 fT12 = fper / 16 101 fT12 = fper / 32 110 fT12 = fper / 64 111 fT12 = fper / 128 Timer T12 Prescaler Bit In order to support higher clock frequencies, an additional prescaler factor of 1/256 can be enabled for the prescaler for T12. 0 The additional prescaler for T12 is disabled. 1 The additional prescaler for T12 is enabled. Timer T12 Run Bit T12R starts and stops timer T12. It is set/reset by SW by setting bits T12RR orT12RS or it is reset by HW according to the function defined by bitfield T12SSC. 0 Timer T12 is stopped. 1 Timer T12 is running. T12PRE 3 rw T12R1) 4 rh User’s Manual 4-74 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field STE12 Bits 5 Type Description rh Timer T12 Shadow Transfer Enable Bit STE12 enables or disables the shadow transfer of the T12 period value, the compare values and passive state select bits and levels from their shadow registers to the actual registers if a T12 shadow transfer event is detected. Bit STE12 is cleared by hardware after the shadow transfer. A T12 shadow transfer event is a period-match while counting up or a one-match while counting down. 0 The shadow register transfer is disabled. 1 The shadow register transfer is enabled. Count Direction of Timer T12 This bit is set/reset according to the counting rules of T12. 0 T12 counts up. 1 T12 counts down. T12 Operating Mode 0 Edge-aligned Mode: T12 always counts up and continues counting from zero after reaching the period value. 1 Center-aligned Mode: T12 counts down after detecting a period-match and counts up after detecting a one-match. CDIR 6 rh CTM 7 rw 1) A concurrent set/reset action on T12R (from T12SSC, T12RR or T12RS) will have no effect. The bit T12R will remain unchanged. Note: A write action to the bit fields T12CLK or T12PRE is only taken into account while the timer T12 is not running (T12R=0). User’s Manual 4-75 V 0.4, 2002-01 C868 On-Chip Peripheral Components TCTR0H Timer Control Register 0,High Byte 7 r 6 r 5 STE13 rh 4 T13R rh 3 T13PRE rw 2 [Reset value: 00H] 1 T13CLK rw 0 Field T13CLK Bits [2:0] Type Description rw Timer T13 Input Clock Select Selects the input clock for timer T13 which is derived from the peripheral clock according to the equation fT13 = fper / 2. 000 fT13 = fper 001 fT13 = fper / 2 010 fT13 = fper / 4 011 fT13 = fper / 8 100 fT13 = fper / 16 101 fT13 = fper / 32 110 fT13 = fper / 64 111 fT13 = fper / 128 Timer T13 Prescaler Bit In order to support higher clock frequencies, an additional prescaler factor of 1/256 can be enabled for the prescaler for T13. 0 The additional prescaler for T13 is disabled. 1 The additional prescaler for T13 is enabled. Timer T13 Run Bit T13R starts and stops timer T13. It is set/reset by SW by setting bits T13RR orT13RS or it is set/reset by HW according to the function defined by bitfields T13SSC, T13TEC and T13TED. 0 Timer T13 is stopped. 1 Timer T13 is running. T13PRE 3 rw T13R1) 4 rh User’s Manual 4-76 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field STE13 Bits 5 Type Description rh Timer T13 Shadow Transfer Enable Bit STE13 enables or disables the shadow transfer of the T13 period value, the compare value and passive state select bit and level from their shadow registers to the actual registers if a T13 shadow transfer event is detected. Bit STE13 is cleared by hardware after the shadow transfer. A T13 shadow transfer event is a period-match. 0 The shadow register transfer is disabled. 1 The shadow register transfer is enabled. reserved; returns ’0’ if read; should be written with ’0’; - [7: 6] r 1) A concurrent set/reset action on T13R (from T13SSC, T13TEC, T13RR or T13RS) will have no effect. The bit T12R will remain unchanged. Note: A write action to the bit fields T13CLK or T13PRE is only taken into account while the timer T13 is not running (T13R=0). User’s Manual 4-77 V 0.4, 2002-01 C868 On-Chip Peripheral Components Register TCTR2 controls the single-shot and the synchronization functionality of both timers T12 and T13. Both timers can run in single-shot mode. In this mode they stop their counting sequence automatically after one counting period with a count value of zero. The single-shot mode and the synchronization feature of T13 to T12 allows the generation of events with a programmable delay after well-defined PWM actions of T12. For example, this feature can be used to trigger AD conversions after a specified delay (to avoid problems due to switching noise) synchronously to a PWM event. TCTR2L Timer Control Register 2 7 r 6 T13TED rw 5 4 3 T13TEC rw 2 [Reset value: 00H] 1 T13SSC rw 0 T12SSC rw Field T12SSC Bits 0 Type Description rw Timer T12 Single Shot Control This bit controls the single shot-mode of T12. 0 The single-shot mode is disabled, no HW action on T12R. 1 The single shot mode is enabled, the bit T12R is reset by HW if - T12 reaches its period value in edge-aligned mode - T12 reaches the value 1 while down counting in center-aligned mode. In parallel to the reset action of bit T12R, the bits CC6xST (x=0, 1, 2) are reset. Timer T13 Single Shot Control This bit controls the single shot-mode of T13. 0 No HW action on T13R 1 The single-shot mode is enabled, the bit T13R is reset by HW if T13 reaches its period value. In parallel to the reset action of bit T13R, the bit CC63ST is reset. T13SSC 1 rw User’s Manual 4-78 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field T13TEC Bits [4:2] Type Description rw T13 Trigger Event Control Bitfield T13TEC selects the trigger event to start T13 (automatic set of T13R for synchronization to T12 compare signals) according to following combinations: 000 no action 001 set T13R on a T12 compare event on channel 0 010 set T13R on a T12 compare event on channel 1 011 set T13R on a T12 compare event on channel 2 100 set T13R on any T12 compare event (ch. 0, 1, 2) 101 set T13R upon a period-match of T12 110 set T13R upon a zero-match of T12 (while counting up) 111 set T13R on any hall state change Timer T13 Trigger Event Direction Bitfield T13TED delivers additional information to control the automatic set of bit T13R in the case that the trigger action defined by T13TEC is detected. 00 reserved, no action 01 while T12 is counting up 10 while T12 is counting down 11 independent on the count direction of T12 reserved; returns ’0’ if read; should be written with ’0’; T13TED1) [6:5] rw 0 7 r 1) Example: If the timer T13 is intended to start at any compare event on T12 (T13TEC=’100’) the trigger event direction can be programmed to - counting up >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting up - counting down >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting down - independent from bit CDIR >> each T12 channel 0, 1, 2 compare match triggers T13R The timer count direction is taken from the value of bit CDIR. As a result, if T12 is running in edge-aligned mode (counting up only), T13 can only be started automatically if bitfield T13TED=’01’ or ’11’. User’s Manual 4-79 V 0.4, 2002-01 C868 On-Chip Peripheral Components Register TCTR4 allows the SW control of the run bits T12R and T13R by independent set and reset conditions. Furthermore, the timers can be reset (while running) and the bits STE12 and STE13 can be controlled by SW. TCTR4L Timer Control Register 4,Low Byte 7 T12STD w 6 T12STR w 5 r 4 r 3 DTRES w 2 T12RES w [Reset value: 00H] 1 T12RS w 0 T12RR w Field T12RR Bits 0 Type Description w Timer T12 Run Reset Setting this bit resets the T12R bit. 0 T12R is not influenced. 1 T12R is cleared, T12 stops counting. Timer T12 Run Set Setting this bit sets the T12R bit. 0 T12R is not influenced. 1 T12R is set, T12 starts counting. Timer T12 Reset 0 No effect on T12. 1 The T12 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T12RES has no impact on bit T12R. Dead-Time Counter Reset 0 No effect on the dead-time counters. 1 The three dead-time counter channels are reset to zero. Timer T12 Shadow Transfer Request 0 No action 1 STE12 is set, enabling the shadow transfer. Timer T12 Shadow Transfer Disable 0 No action 1 STE12 is reset without triggering the shadow transfer. reserved; returns ’0’ if read; should be written with ’0’; T12RS 1 w T12RES 2 w DTRES 3 w T12STR 6 w T12STD 7 w - [5:4] r User’s Manual 4-80 V 0.4, 2002-01 C868 On-Chip Peripheral Components Note: A simultaneous write of a ’1’ to bits which set and reset the same bit will trigger no action. The corresponding bit will remain unchanged. TCTR4H Timer Control Register 4,High Byte 7 T13STD w 6 T13STR w 5 r 4 r 3 r 2 T13RES w [Reset value: 00H] 1 T13RS w 0 T13RR w Field T13RR Bits 0 Type Description w Timer T13 Run Reset Setting this bit resets the T13R bit. 0 T13R is not influenced. 1 T13R is cleared, T13 stops counting. Timer T13 Run Set Setting this bit sets the T13R bit. 0 T13R is not influenced. 1 T13R is set, T13 starts counting. Timer T13 Reset 0 No effect on T13. 1 The T13 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T13RES has no impact on bit T13R. Timer T13 Shadow Transfer Request 0 No action 1 STE13 is set, enabling the shadow transfer. Timer T13 Shadow Transfer Disable 0 No action 1 STE13 is reset without triggering the shadow transfer. reserved; returns ’0’ if read; should be written with ’0’; T13RS 1 w T13RES 2 w T13STR 6 w T13STD 7 w - [5:3] r Note: A simultaneous write of a ’1’ to bits which set and reset the same bit will trigger no action. The corresponding bit will remain unchanged. User’s Manual 4-81 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.8.4 4.8.4.1 Modulation Control Registers Global Module Control Register MODCTR contains control bits enabling the modulation of the corresponding output signal by PWM pattern generated by the timers T12 and T13. Furthermore, the multi-channel mode can be enabled as additional modulation source for the output signals. MODCTRL Modulation Control Register ,Low Byte 7 MCMEN rw 6 r 5 4 3 2 [Reset value: 00H] 1 0 T12MODEN rw Field T12MODEN Bits [5:0] Type Description rw T12 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by timer T12. The bit positions are corresponding to the following output signals: bit 0 modulation of CC60 bit 1 modulation of COUT60 bit 2 modulation of CC61 bit 3 modulation of COUT61 bit 4 modulation of CC62 bit 5 modulation of COUT62 The enable feature of the modulation is defined as follows: 0 The modulation of the corresponding output signal by a T12 PWM pattern is disabled. 1 The modulation of the corresponding output signal by a T12 PWM pattern is enabled. Multi-Channel Mode Enable 0 The modulation of the corresponding output signal by a multi-channel pattern according to bitfield MCMOUT is disabled. 1 The modulation of the corresponding output signal by a multi-channel pattern according to bitfield MCMOUT is enabled. 4-82 V 0.4, 2002-01 MCMEN 7 rw User’s Manual C868 On-Chip Peripheral Components Field Bits 6 Type Description r reserved; returns ’0’ if read; should be written with ’0’; MODCTRH Modulation Control Register ,High Byte 7 ECT13O rw 6 r 5 4 3 2 [Reset value: 00H] 1 0 T13MODEN rw Field T13MODEN Bits [5:0] Type Description rw T13 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by timer T13. The bit positions are corresponding to the following output signals: bit 0 modulation of CC60 bit 1 modulation of COUT60 bit 2 modulation of CC61 bit 3 modulation of COUT61 bit 4 modulation of CC62 bit 5 modulation of COUT62 The enable feature of the modulation is defined as follows: 0 The modulation of the corresponding output signal by a T13 PWM pattern is disabled. 1 The modulation of the corresponding output signal by a T13 PWM pattern is enabled. Enable Compare Timer T13 Output 0 The alternate output function COUT63 is disabled. 1 The alternate output function COUT63 is enabled for the PWM signal generated by T13. reserved; returns ’0’ if read; should be written with ’0’; ECT13O 7 rw - 14 r User’s Manual 4-83 V 0.4, 2002-01 C868 On-Chip Peripheral Components The register TRPCTR controls the trap functionality. It contains independent enable bits for each output signal and control bits to select the behavior in case of a trap condition. The trap condition is a low level on the CTRAP input pin, which is monitored (inverted level) by bit TRPF (in register IS). While TRPF=’1’ (trap input active), the trap state bit TRPS (in register IS) is set to ’1’. TRPCTRL Trap Control Register ,Low Byte 7 r 6 r 5 r 4 r 3 r 2 TRPM2 rw [Reset value: 00H] 1 TRPM1 rw 0 TRPM0 rw Field TRPM1, TRPM0 Bits [1:0] Type Description rw Trap Mode Control Bits 1, 0 These two bits define the behavior of the selected outputs when leaving the trap state after the trap condition has become inactive again. A synchronization to the timer driving the PWM pattern permits to avoid unintended short pulses when leaving the trap state. The combination (TRPM1, TRPM0) leads to: 00 The trap state is left (return to normal operation according to TRPM2) when a zeromatch of T12 (while counting up) is detected (synchronization to T12). 01 The trap state is left (return to normal operation according to TRPM2) when a zeromatch of T13 is detected (synchronization to T13). 10 reserved 11 The trap state is left (return to normal operation according to TRPM2) immediately without any synchronization to T12 or T13. User’s Manual 4-84 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field TRPM2 Bits 2 Type Description rw Trap Mode Control Bit 2 0 The trap state can be left (return to normal operation = bit TRPS=’0’) as soon as the input CTRAP becomes inactive. Bit TRPF is automatically cleared by HW if the input pin CTRAP becomes ’1’. Bit TRPS is automatically cleared by HW if bit TRPF is ’0’ and if the synchronization condition (according to TRPM0,1) is detected. 1 The trap state can be left (return to normal operation = bit TRPS=’0’) as soon as bit TRPF is reset by SW after the input CTRAP becomes inactive (TRPF is not cleared by HW). Bit TRPS is automatically cleared by HW if bit TRPF=’0’ and if the synchronization condition (according to TRPM0,1) is detected. reserved; returns ’0’ if read; should be written with ’0’; - [7:3] r User’s Manual 4-85 V 0.4, 2002-01 C868 On-Chip Peripheral Components TRPCTRH Trap Control Register ,High Byte 7 TRPPEN rw 6 TRPEN13 rw 5 4 3 TRPEN rw 2 [Reset value: 00H] 1 0 Field TRPEN Bits [5:0] Type Description rw Trap Enable Control Setting these bits enables the trap functionality for the following corresponding output signals: bit 0 trap functionality of CC60 bit 1 trap functionality of COUT60 bit 2 trap functionality of CC61 bit 3 trap functionality of COUT61 bit 4 trap functionality of CC62 bit 5 trap functionality of COUT62 The enable feature of the trap functionality is defined as follows: 0 The trap functionality of the corresponding output signal is disabled. The output state is independent from bit TRPS. 1 The trap functionality of the corresponding output signal is enabled. The output is set to the passive state while TRPS=’1’. Trap Enable Control for Timer T13 0 The trap functionality for T13 is disabled. Timer T13 (if selected and enabled) provides PWM functionality even while TRPS=’1’. 1 The trap functionality for T13 is enabled. The timer T13 PWM output signal is set to the passive state while TRPS=’1’. Trap Pin Enable 0 The trap functionality based on the input pin CTRAP is disabled. A trap can only be generated by SW by setting bit TRPF. 1 The trap functionality based on the input pin CTRAP is enabled. A trap can be generated by SW by setting bit TRPF or by CTRAP=’0’. 4-86 V 0.4, 2002-01 TRPEN13 6 rw TRPPEN 7 rw User’s Manual C868 On-Chip Peripheral Components Register PSLR defines the passive state level driven by the output pins of the module. The passive state level is the value that is driven by the port pin during the passive state of the output. During the active state, the corresponding output pin drives the active state level, which is the inverted passive state level. The passive state level permits to adapt the driven output levels to the driver polarity (inverted, not inverted) of the connected power stage. PSLRL Passive State Level Register ,High Byte 7 PSL63 rwh 6 r 5 4 3 PSL rwh 2 [Reset value: 00H] 1 0 Field PSL1) Bits [5:0] Type Description rwh Compare Outputs Passive State Level The bits of this bitfield define the passive level driven by the module outputs during the passive state. The bit positions are: bit 0 passive level for output CC60 bit 1 passive level for output COUT60 bit 2 passive level for output CC61 bit 3 passive level for output COUT61 bit 4 passive level for output CC62 bit 5 passive level for output COUT62 The value of each bit position is defined as: 0 The passive level is ’0’. 1 The passive level is ’1’. Passive State Level of Output COUT63 This bitfield defines the passive level of the output pin COUT63. 0 The passive level is ’0’. 1 The passive level is ’1’. reserved; returns ’0’ if read; should be written with ’0’; PSL632) 7 rwh - 6 r 1) Bitfield PSL has a shadow registers to allow for updates without undesired pulses on the output lines. The bits are updated with the T12 shadow transfer. A read action targets the actually used values, whereas a write action targets the shadow bits. User’s Manual 4-87 V 0.4, 2002-01 C868 On-Chip Peripheral Components 2) Bit PSL63 has a shadow register to allow for updates without undesired pulses on the output line. The bit is updated with the T13 shadow transfer. A read action targets the actually used values, whereas a write action targets the shadow bits. 4.8.4.2 Multi-Channel Control Register MCMOUTS contains bits controlling the output states for multi-channel mode. Furthermore, the appropriate signals for the block commutation by Hall sensors can be selected. This register is a shadow register (that can be written) for register MCMOUT, which indicates the currently active signals. MCMOUTSL Multi-Channel Mode Output Shadow Register ,Low Byte 7 STRMCM w 6 r 5 4 3 MCMPS rw 2 [Reset value: 00H] 1 0 Field MCMPS Bits [5:0] Type Description rw Multi-Channel PWM Pattern Shadow Bitfield MCMPS is the shadow bitfield for bitfield MCMP. The multi-channel shadow transfer is triggered according to the transfer conditions defined by register MCMCTR. Shadow Transfer Request for MCMPS Setting this bits during a write action leads to an immediate update of bitfield MCMP by the value written to bitfield MCMPS. This functionality permits an update triggered by SW. When read, this bit always delivers ’0’. 0 Bitfield MCMP is updated according to the defined HW action. The write access to bitfield MCMPS doesn’t modify bitfield MCMP. 1 Bitfield MCMP is updated by the value written to bitfield MCMPS. reserved; returns ’0’ if read; should be written with ’0’; STRMCM 7 w - 6 r User’s Manual 4-88 V 0.4, 2002-01 C868 On-Chip Peripheral Components MCMOUTSH Multi-Channel Mode Output Shadow Register ,High Byte 7 STRHP w 6 r 5 4 CURHS rw 3 2 [Reset value: 00H] 1 EXPHS rw 0 Field EXPHS Bits [2:0] Type Description rw Expected Hall Pattern Shadow Bitfield EXPHS is the shadow bitfield for bitfield EXPH. The bitfield is transferred to bitfield EXPH if an edge on the hall input pins CCPOSx (x=0, 1, 2) is detected. Current Hall Pattern Shadow Bitfield CURHS is the shadow bitfield for bitfield CURH. The bitfield is transferred to bitfield CURH if an edge on the hall input pins CCPOSx (x=0, 1, 2) is detected. Shadow Transfer Request for the Hall Pattern Setting this bits during a write action leads to an immediate update of bitfields CURH and EXPH by the value written to bitfields CURHS and EXPH. This functionality permits an update triggered by SW. When read, this bit always delivers ’0’. 0 The bitfields CURH and EXPH are updated according to the defined HW action. The write access to bitfields CURHS and EXPH doesn’t modify the bitfields CURH and EXPH. 1 The bitfields CURH and EXPH are updated by the value written to the bitfields CURHS and EXPHS. reserved; returns ’0’ if read; should be written with ’0’; CURHS [5:3] rw STRHP 7 w - 6 r User’s Manual 4-89 V 0.4, 2002-01 C868 On-Chip Peripheral Components Register MCMOUT shows the multi-channel control bits, that are currently used. Register MCMOUT is defined as follows: MCMOUTL Multi-Channel Mode Output Register ,Low Byte 7 r 6 R rh 5 4 3 MCMP rh 2 [Reset value: 00H] 1 0 Field MCMP1) Bits [5:0] Type Description rh Multi-Channel PWM Pattern Bitfield MCMP is written by a shadow transfer from bitfield MCMPS. It contains the output pattern for the multi-channel mode. If this mode is enabled by bit MCMEN in register MODCTR, the output state of the following output signal can be modified: bit 0 multi-channel state for output CC60 bit 1 multi-channel state for output COUT60 bit 2 multi-channel state for output CC61 bit 3 multi-channel state for output COUT61 bit 4 multi-channel state for output CC62 bit 5 multi-channel state for output COUT62 The multi-channel patterns can set the related output to the passive state. 0 The output is set to the passive state. The PWM generated by T12 or T13 are not taken into account. 1 The output can deliver the PWM generated by T12 or T13 (according to register MODCTR). User’s Manual 4-90 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field R Bits 6 Type Description rh Reminder Flag This reminder flag indicates that the shadow transfer from bitfield MCMPS to MCMP has been requested by the selected trigger source. This bit is cleared when the shadow transfer takes place and while MCMEN=’0’. 0 Currently, no shadow transfer from MCMPS to MCMP is requested. 1 A shadow transfer from MCMPS to MCMP has been requested by the selected trigger source, but it has not yet been executed, because the selected synchronization condition has not yet occurred. reserved; returns ’0’ if read; should be written with ’0’; - 7 r 1) While IDLE=’1’, bit field MCMP is cleared. User’s Manual 4-91 V 0.4, 2002-01 C868 On-Chip Peripheral Components MCMOUTH Multi-Channel Mode Output Register ,High Byte 7 r 6 r 5 4 CURH rw 3 2 [Reset value: 00H] 1 EXPH rw 0 Field EXPH 1) Bits [2:0] Type Description rh Expected Hall Pattern Bitfield EXPH is written by a shadow transfer from bitfield EXPHS. The contents is compared after every detected edge at the hall input pins with the pattern at the hall input pins in order to detect the occurrence of the next desired (=expected) hall pattern or a wrong pattern. If the current hall pattern at the hall input pins is equal to the bitfield EXPH, bit CHE (correct hall event) is set and an interrupt request is generated (if enabled by bit ENCHE). If the current hall pattern at the hall input pins is not equal to the bitfields CURH or EXPH, bit WHE (wrong hall event) is set and an interrupt request is generated (if enabled by bit ENWHE). Current Hall Pattern Bitfield CURH is written by a shadow transfer from bitfield CURHS.The contents is compared after every detected edge at the hall input pins with the pattern at the hall input pins in order to detect the occurrence of the next desired (=expected) hall pattern or a wrong pattern. If the current hall input pattern is equal to bitfield CURH, the detected edge at the hall input pins has been an invalid transition (e.g. a spike). reserved; returns ’0’ if read; should be written with ’0’; CURH [5:3] rh - [7:6] r 1) The bits in the bit fields EXPH and CURH correspond to the hall patterns at the input pins CCPOSx (x=0, 1, 2) in the order (EXPH.2, EXPH.1, EXPH.0), (CURH.2, CURH.1, CURH.0), (CCPOS2, CCPOS.1, CCPOS0). User’s Manual 4-92 V 0.4, 2002-01 C868 On-Chip Peripheral Components Register MCMCTR contains control bits for the multi-channel functionality. MCMCTRLL Multi-Channel Mode Control Register 7 r 6 r 5 SWSYN rw 4 3 r 2 [Reset value: 00H] 1 SWSEL rw 0 Field SWSEL Bits [2:0] Type Description rw Switching Selection Bitfield SWSEL selects one of the following trigger request sources (next multi-channel event) for the shadow transfer from MCMPS to MCMP. The trigger request is stored in the reminder flag R until the shadow transfer is done and flag R is cleared automatically with the shadow transfer. The shadow transfer takes place synchronously with an event selected in bitfield SWSYN. 000 no trigger request will be generated 001 correct hall pattern on CCPOSx detected 010 T13 period-match detected (while counting up) 011 T12 one-match (while counting down) 100 T12 channel 1 compare-match detected (phase delay function) 101 T12 period match detected (while counting up) else reserved, no trigger request will be generated Switching Synchronization Bitfield SWSYN triggers the shadow transfer between MCMPS and MCMP if it has been requested before (flag R set by an event selected by SWSEL). This feature permits the synchronization of the outputs to the PWM source, that is used for modulation (T12 or T13). 00 direct; the trigger event directly causes the shadow transfer 01 T13 zero-match triggers the shadow transfer 10 a T12 zero-match (while counting up) triggers the shadow transfer 11 reserved; no action SWSYN [5:4] rw User’s Manual 4-93 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field Bits 3, [7:6] Type Description r reserved; returns ’0’ if read; should be written with ’0’; Note: The generation of the shadow transfer request by HW is only enabled if bit MCMEN=’1’. User’s Manual 4-94 V 0.4, 2002-01 C868 On-Chip Peripheral Components Register T12MSEL contains control bits to select the capture/compare functionality of the three channels of timer T12. T12MSELL T12 Capture/Compare Mode Select Register, Low Byte 7 6 MSEL61 rw 5 4 3 2 MSEL60 rw [Reset value: 00H] 1 0 Field MSEL60, MSEL61 Bits [3:0], [7:4] Type Description rw Capture/Compare Mode Selection These bitfields select the operating mode of the three timer T12 capture/compare channels. Each channel (n=0, 1, 2) can be programmed individually either for compare or capture operation according to: 0000 Compare outputs disabled, pins CC6n and COUT6n can be used for IO. No capture action. 0001 Compare output on pin CC6n, pin COUT6n can be used for IO. No capture action. 0010 Compare output on pin COUT6n, pin CC6n can be used for IO. No capture action. 0011 Compare output on pins COUT6n and CC6n. 01XX Double-Register Capture modes, see Table 4-4. 1000 Hall Sensor mode, see Table 4-5. In order to enable the hall edge detection, all three MSEL6x have to be programmed to Hall Sensor mode. 1001 Hysteresis-like mode, see Table 4-5. 101X Multi-Input Capture modes, see Table 4-6. 11XX Multi-Input Capture modes, see Table 4-6. Note: In the capture modes, all edges at the CC6x inputs are leading to the setting of the corresponding interrupt status flags in register IS. In order to monitor the selected capture events at the CCPOSx inputs in the multi-input capture modes, the CC6xST bits of the corresponding channel are set when detecting the selected event. The interrupt status bits and the CC6xST bits have to be reset by SW. User’s Manual 4-95 V 0.4, 2002-01 C868 On-Chip Peripheral Components T12MSELH T12 Capture/Compare Mode Select Register, High Byte 7 r 6 r 5 r 4 r 3 2 [Reset value: 00H] 1 MSEL62 rw 0 Field MSEL62 Bits [3:0] Type Description rw Capture/Compare Mode Selection These bitfields select the operating mode of the three timer T12 capture/compare channels. Each channel (n=0, 1, 2) can be programmed individually either for compare or capture operation according to: 0000 Compare outputs disabled, pins CC6n and COUT6n can be used for IO. No capture action. 0001 Compare output on pin CC6n, pin COUT6n can be used for IO. No capture action. 0010 Compare output on pin COUT6n, pin CC6n can be used for IO. No capture action. 0011 Compare output on pins COUT6n and CC6n. 01XX Double-Register Capture modes, see Table 4-4. 1000 Hall Sensor mode, see Table 4-5. In order to enable the hall edge detection, all three MSEL6x have to be programmed to Hall Sensor mode. 1001 Hysteresis-like mode, see Table 4-5. 101X Multi-Input Capture modes, see Table 4-6. 11XX Multi-Input Capture modes, see Table 4-6. reserved; returns ’0’ if read; should be written with ’0’; - [7:4] r Note: In the capture modes, all edges at the CC6x inputs are leading to the setting of the corresponding interrupt status flags in register IS. In order to monitor the selected capture events at the CCPOSx inputs in the multi-input capture modes, the CC6xST bits of the corresponding channel are set when detecting the selected event. The interrupt status bits and the CC6xST bits have to be reset by SW. User’s Manual 4-96 V 0.4, 2002-01 C868 On-Chip Peripheral Components Table 4-4 Description Double-Register Capture modes 0100The contents of T12 is stored in CC6nR after a rising edge and in CC6nSR after a falling edge on the input pin CC6n. 0101The value stored in CC6nSR is copied to CC6nR after a rising edge on the input pin CC6n. The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR. This feature is useful for time measurements between consecutive rising edges on pins CC6n. COUT6n is IO. 0110The value stored in CC6nSR is copied to CC6nR after a falling edge on the input pin CC6n. The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR. This feature is useful for time measurements between consecutive falling edges on pins CC6n. COUT6n is IO. 0111The value stored in CC6nSR is copied to CC6nR after any edge on the input pin CC6n. The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR. This feature is useful for time measurements between consecutive edges on pins CC6n. COUT6n is IO. Table 4-5 Description Combined-T12 modes 1000Hall Sensor mode: Capture mode for channel 0, compare mode for channels 1 and 2. The contents of T12 is captured into CC60 at a valid hall event (which is a reference to the actual speed). CC61 can be used for a phase delay function between hall event and output switching. CC62 can act as a time-out trigger if the expected hall event comes too late. The value ’1000’ has to be programmed to MSEL0, MSEL1 and MSEL2 if the hall signals are used. In this mode, the contents of timer T12 is captured in CC60 and T12 is reset after the detection of a valid hall event. In order to avoid noise effects, the dead-time counter channel 0 is started after an edge has been detected at the hall inputs. When reaching the value of ’000001’, the hall inputs are sampled and the pattern comparison is done. 1001Hysteresis-like control mode with dead time generation: The negative edge of the CCPOSx input signal is used to reset bit CC6nST. As a result, the output signals can be switched to passive state immediately and switch back to active state (with dead time) if the CCPOSx is high and the bit CC6nST is set by a compare event. Description of the Combined-T12 modes. Description of the Double-Register Capture modes. User’s Manual 4-97 V 0.4, 2002-01 C868 On-Chip Peripheral Components Table 4-6 Description Multi-Input Capture modes 1010The timer value of T12 is stored in CC6nR after a rising edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx. 1011The timer value of T12 is stored in CC6nR after a falling edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx. 1100The timer value of T12 is stored in CC6nR after a rising edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx. 1101The timer value of T12 is stored in CC6nR after a falling edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx. 1110The timer value of T12 is stored in CC6nR after any edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after any edge at the input pin CCPOSx. 1111reserved (no capture or compare action) Description of the Multi-Input Capture modes. User’s Manual 4-98 V 0.4, 2002-01 C868 On-Chip Peripheral Components PMCON1 Peripheral Management Control Register 7 r 6 r 5 r 4 r 3 r [Reset value: XXXXX000B] 2 CCUDIS rw 1 T2DIS rw 0 ADCDIS rw The functions of the shaded bits are not described here Field CCUDIS Bits 2 Typ Description rw CCU6 Disable Request. 0 : CCU6 will continue normal operation. (default) 1 : Request to disable the CCU6 is active. PMCON2 Peripheral Management Status Register 7 r 6 r 5 r 4 r 3 r [Reset value: XXXXX000B] 2 CCUST rh 1 T2ST rh 0 ADCST rh The functions of the shaded bits are not described here Field CCUST Bits 2 Typ Description rh CCU6 Disable Status 0 : CCU6 is not disabled. (default) 1 : CCU6 is disabled, clock is gated off. User’s Manual 4-99 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.9 Serial Interface The serial port of the C868 is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 3 asynchronous modes. The baud rate clock for the serial port is derived from the oscillator frequency (mode 2) or generated either by timer 1 or by a dedicated baud rate generator (mode 1, 3). Mode 0 is reserved. Mode 1, 8-Bit UART, Variable Baud Rate: In mode 1, ten bits are transmitted (through TxD) or received (through RxD). They are a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in special function register SCON. The baud rate is variable. (See section 4.9.2 for more detailed information) Mode 2, 9-Bit UART, Fixed Baud Rate: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in SCON) can be assigned to the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in special function register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. (See section 4.9.3 for more detailed information) Mode 3, 9-Bit UART, Variable Baud Rate: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, mode 3 is the same as mode 2 in all respects except the baud rate. The baud rate in mode 3 is variable. (See section 4.9.3 for more detailed information) In all modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in the modes by the incomming start bit if REN = 1. The serial interface also provides interrupt requests when transmission or reception of a frames have been completed. The corresponding interrupt request flags are TI or RI, resp. See chapter 7 of this user manual for more details about the interrupt structure. The interrupt request flags TI and RI can also be used for polling the serial interface, if the serial interrupt is not to be used (i.e. serial interrupt not enabled). User’s Manual 4-100 V 0.4, 2002-01 C868 On-Chip Peripheral Components Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren’t being addressed leave their SM2s set and go on about their business, ignoring the incoming data bytes. SM2 can be used in mode 1 to check the validity of the stop bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. Serial Port Registers The serial port control and status register is the special function register SCON. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). SBUF is the receive and transmit buffer of serial interface. Writing to SBUF loads the transmit register and initiates transmission. Reading out SBUF accesses a physically separate receive register. SBUF Serial Data Buffer Register 7 6 5 4 SBUF rw 3 2 [Reset value: 00H] 1 0 Field SBUF Bits [7:0] Typ Description rw Serial Interface Buffer Register User’s Manual 4-101 V 0.4, 2002-01 C868 On-Chip Peripheral Components SCON Serial Channel Control Register 9FH SM0 rw 9EH SM1 rw 9DH SM2 rw 9CH REN rw 9BH TB8 rw 9AH RB8 rw [Reset value: 00H] 99H TI rw 98H RI rw Field RI Bits 0 Typ Description rw Serial port receiver interrupt flag RI is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (exception see SM2). RI must be cleared by software. Serial port transmitter interrupt flag TI is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. TI must be cleared by software. Serial port receiver bit 9 In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Serial port transmitter bit 9 TB8 is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired. Enable receiver of serial port Enables serial reception. Set by software to enable serial reception. Cleared by software to disable serial reception. Enable serial port multiprocessor communication in modes 2 and 3 In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. TI 1 rw RB8 2 rw TB8 3 rw REN 4 rw SM2 5 rw User’s Manual 4-102 V 0.4, 2002-01 C868 On-Chip Peripheral Components Field SM0 SM1 Bits [7:6] Typ Description rw Serial port 0 operating mode selection bits Table 1 : SM0 0 0 1 SM1 0 1 0 Selected operating mode mode 0 :reserved mode 1 :8-bit UART, variable baud rate mode 2 :9-bit UART, fixed baud rate (fsys/32 or fsys/64) Mode 3 :9-bit UART, variable baud rate 1 1 4.9.1 Baud Rate Generation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating. For clarification, some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators have to provide a "baud rate clock" to the serial interface which - there divided by 16 results in the actual "baud rate". However, all formulas given in the following section already include the factor and calculate the final baud rate. Further, the abrevation fSYS refers to the system frequency. User’s Manual 4-103 V 0.4, 2002-01 C868 On-Chip Peripheral Components The baud rate of the serial port is controlled by a bit which are located in the special function registers as shown below. PCON Power Control Register 7 SMOD rw 6 r 5 r 4 SD rw 3 GF1 rw [Reset value: 0XXX0000B] 2 GF0 rw 1 PDE rw 0 IDLE rw The functions of the shaded bits are not described here Field SMOD Bits 7 Typ Description rw Double baud rate When set, the baud rate of serial interface in modes 1, 2, 3 is doubled. After reset this bit is cleared. Depending on the programmed operating mode different paths are selected for the baud rate clock generation. 4.9.1.1 Baud Rate in Mode 2 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON. If SMOD = 0 (which is the value after reset), the baud rate is 1/64 of the system frequency. If SMOD = 1, the baud rate is 1/32 of the system frequency. Mode 2 baud rate = 2 SMOD 64 x system frequency 4.9.1.2 Baud Rate in Mode 1 and 3 In these modes the baud rate is variable and can be generated alternatively by a baud rate generator or by timer 1. Using the Timer 2 as Baud Rate Generator In modes 1 and 3, the C868 can use timer 2 as the baud rate generator for the serial port. To enable the baud generator for transmit, bit TCLK (bit 4 of special function register User’s Manual 4-104 V 0.4, 2002-01 C868 On-Chip Peripheral Components T2CON) must be set. To enable the baud generator for receive, bit RCLK (bit 5 of special function register T2CON) must be set. With the timer 2 as clock source for the serial port in mode 1 and 3, the baud rate can be determined as follows: Mode 1, 3 baud rate = 2SMOD 32 x (timer 2 overflow rate) Timer 2 overflow rate = 2x(216 – RC2) / system frequency with RC2 = RC2H.7..0, RC2L.7..0 and timer2 count direction is set to up. Using Timer 2 to Generate Baud Rates In modes 1 and 3 of the serial interface timer 1 can also be used for generating baud rates. Then the baud rate is determined by the timer 1 overflow rate and the value of SMOD as follows: 2SMOD 32 Mode 1, 3 baud rate = x (timer 1 overflow rate) The timer 1 interrupt is usually disabled in this application. Timer 1 itself can be configured for either "timer" or "counter" operation, and in any of its operating modes. In most typical applications, it is configured for "timer" operation in the auto-reload mode (high nibble of TMOD = 0010B). In this case the baud rate is given by the formula: 2SMOD x Mode 1, 3 baud rate = 32 x 12 x (256 – (TH1)) system frequency Very low baud rates can be achieved with timer 1 if leaving the timer 1 interrupt enabled, configuring the timer to run as 16-bit timer (high nibble of TMOD = 0001B), and using the timer 1 interrupt for a 16-bit software reload. User’s Manual 4-105 V 0.4, 2002-01 C868 On-Chip Peripheral Components 4.9.2 Details about Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB8 in SCON. The baud rate is determined either by the timer 1 overflow rate or by the internal baud rate generator. Figure 4-37 shows a simplified functional diagram of the serial port in mode 1. The associated timings for transmit/receive are illustrated in Figure 4-38. Transmission is initiated by an instruction that uses SBUF as a destination register. The "Write-to-SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested. Transmission starts at the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "Write-to-SBUF" signal). The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeroes are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeroes. This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after "Write-toSBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register, and reception of the rest of the frame will proceed. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for the noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection or false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register, (which in mode 1 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1)RI = 0,and 2)either SM2 = 0, or the received stop bit = 1 User’s Manual 4-106 V 0.4, 2002-01 C868 On-Chip Peripheral Components If one of these two condtions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bit goes into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. User’s Manual 4-107 V 0.4, 2002-01 C868 On-Chip Peripheral Components Internal Bus 1 Write to SBUF S D CLK Zero Detector Q SBUF & _