TVS Diodes
Transient Voltage Suppressor Diodes
E S D3 V3U 4 U L C
Ultra Low Capacitance ESD Array
ESD3V3U4ULC
Data Sheet
Revision 0.9, 2010-10-14 Preliminary
Industrial and Multi-Market
Edition 2010-10-14 Published by Infineon Technologies AG 81726 Munich, Germany © 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
ESD3V3U4ULC
Revision History Page or Item Subjects (major changes since previous revision) Revision 0.9, 2010-10-14
Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™, CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™, PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™, SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-06-09
Preliminary Data Sheet
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ESD3V3U4ULC
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 1.1 1.2 2 3 3.1 3.2 4 5 6 6.1 Ultra Low Capacitance ESD Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics at TA = 25 °C, unless otherwise specified . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Performance characteristics at TA = 25 °C, unless otherwise specified . . . . . . . . . . . . . . . . 10 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PG-TSLP-9-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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ESD3V3U4ULC
List of Figures
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 a) Pin Configuration and b) Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Definitions of electrical characteristics[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Line capacitance CL = f(VR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reverse current IR = f(TA), VR = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Forward characteristic, IF = f(VF), current forced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reverse characteristic, IR = (VR), voltage forced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reverse TLP characteristicNote: [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Forward TLP characteristicNote: [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 USB3.0 structure with ESD protection devices [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PG-TSLP-9-1: Package Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PG-TSLP-9-1: Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PG-TSLP-9-1: Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PG-TSLP-9-1: Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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ESD3V3U4ULC
List of Tables
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Rating at TA = 25 °C, unless otherwise specified. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC characteristics at TA = 25 °C, unless otherwise specified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF characteristics at TA = 25 °C, unless otherwise specified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD characteristics at TA = 25 °C, unless otherwise specified . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 8 9 9
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Ultra Low Capacitance ESD Array
1
Ultra Low Capacitance ESD Array
1.1
•
Features
• • • • • • • • •
ESD / Transient protection of high speed data lines exceeding : • IEC61000-4-2 (ESD) : ±20 kV (air/contact) • IEC61000-4-4 (EFT) : 2.5 kV (5/50ns) • IEC61000-4-5 (Surge) : 3 A (8/20ns) Maximum working voltage: VRWM = 3.3 V Very low reverse current: IR = 1 nA (typical) Extremely low capacitance CL = 0.4 pF I/O to GND (typical) Very low reverse clamping voltage: VCL= 9 V at IPP = 16 A (typical) Very low forward clamping voltage: VFC= 6 V at IPP = 16 A (typical) Very low reverse dynamic resistance: Rdyn,rev = 0.2 Ω (typical) TSLP-9-1 package with pad pitch 0.5 mm Optimized pad design to simplify PCB layout Pb-free and Halogen-Free package (RoHS compliant)
1.2
• • •
Application Examples
USB 3.0, 10/100/1000 Ethernet, Firewire DVI, HDMI, S-ATA, DisplayPort, Mobile communication, LCD displays, Camera Consumer products (STB, MP3, DVD, DSC, ...) Notebooks and desktop computers, peripherals
2
Product Description
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5 Pin 1
I/O
Pin 2
I/O
Pin 4
I/O
Pin 5
I/O
GND
Pin 9
Pin 8
Pin 7
Pin 6
Pin 3 b) Schematic diagram
a) Pin configuration
Figure 1 Table 1 Type ESD3V3U4ULC a) Pin Configuration and b) Schematic Diagram Ordering information Package PG-TSLP-9-1 Configuration 4 lines, uni-directional
Marking code Z2
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ESD3V3U4ULC
Characteristics
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Characteristics
Table 2 Parameter
Maximum Rating at TA = 25 °C, unless otherwise specified Symbol Min.
1) 2)
Values Typ.
– – – –
Unit Max.
20 3 125 150 kV A °C °C
ESD contact discharge Operating temperature Storage temperage
VESD IPP TOP Tstg
-20 -3 -40 -65
Peak pulse current (tp = 8/20 µs)
1)VESD according to IEC61000-4-2 2)IPP according to IEC61000-4-5
3.1
Electrical Characteristics at TA = 25 °C, unless otherwise specified
VF Forward voltage I F Forward current VR Reverse voltage I R Reverse current VR I PP
IF
Rdiff, rev Differential reverse series resistance Rdiff , fwd Differential forward series resistance VTrig Triggering reverse voltage Rdiff, fwd VCL Clamping voltage VHold Holding reverse voltage
VTrig VR
VHold VCL
VRWM IRWM ITrig IHold VF VFC VF
VRWM Reverse working voltage maximum VFC Forward clamping voltage I Trig Triggering reverse current IHold Holding reverse current I PP Peak pulse current IRWM Reverse working current maximum
Diode _Characteristic_Curve_with_snapback.vsd
Rdiff, rev -IPP IR
Figure 2 Table 3 Parameter
Definitions of electrical characteristics[1] DC characteristics at TA = 25 °C, unless otherwise specified Symbol Min.
– – – 1
Values Typ. Max.
3.3 50
Unit
V nA
Note / Test Condition
I/O to GND
Reverse working voltage VRWM Reverse current
IR
VR = 3.3 V, I/O to GND
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ESD3V3U4ULC
Characteristics
Table 4 Parameter
RF characteristics at TA = 25 °C, unless otherwise specified Symbol Min. Values Typ.
0.4 0.2
Unit Max.
0.65 0.35 pF pF
Note / Test Condition
Line capacitance
CL
– –
VR = 0 V, f = 1 MHz, I/O to GND VR = 0V, f = 1 MHz,
I/O to I/O
Table 5 Parameter
ESD characteristics at TA = 25 °C, unless otherwise specified Symbol Min. Values Typ.
9 12 6 10 0.2 0.25
Unit Max.
– – – – – – V V V V
Note / Test Condition
Reverse clamping voltage1) [2] Forward clamping voltage1) [2] Reverse dynamic resistance1) [2] Forward dynamic resistance 1)[2]
VCL VFC Rdyn, rev Rdyn, fwd
– – – – – –
IPP = 16 A IPP = 30 A IPP = 16 A IPP = 30 A
Ω Ω
1) Please refer to Application Note AN210. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between IPP1 = 10 A and IPP2 = 40 A.
Preliminary Data Sheet
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ESD3V3U4ULC
Characteristics
3.2
Typical Performance characteristics at TA = 25 °C, unless otherwise specified
1.5
1 CL (pF) 0.5 0 0 1 2 VR (V) 3
Figure 3
10
-6
Line capacitance CL = f(VR)
10-7
IR (A)
10
-8
10
-9
10-10 -50
-25
0
25
50 75 TA (°C)
100 125 150
Figure 4
Reverse current IR = f(TA), VR = 3.3 V
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ESD3V3U4ULC
Characteristics
10
-1
10-2 10-3 10
-4
IF (A)
10-5 10-6 10 10
-7
-8
0.3
0.4
0.5
0.6 VF (V)
0.7
0.8
0.9
Figure 5
10
-2
Forward characteristic, IF = f(VF), current forced
10-3 10 10 10 IR (A)
-4 -5 -6
10-7 10 10 10
-8 -9
-10
10-11 10-12 0 1 2 3 4 VR (V) 5 6 7
Figure 6
Reverse characteristic, IR = (VR), voltage forced
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Characteristics
70 60 50 TLP Current (A) 40 30 Rdyn=0.2Ω 20 10 0 0 5 ESD3V3U4ULC Rdyn 10 15 20 25 TLP Voltage (V)
35 30 25 20 15 10 5 0 Equivalent VIEC [kV] Equivalent VIEC [kV]
Figure 7
0 -10 -20 TLP Current (A) -30 -40
Reverse TLP characteristicNote: [2]
0 -5 -10 -15 -20 Rdyn=0.25Ω -25 -30 ESD3V3U4ULC Rdyn -20 -15 -10 -5 0 TLP Voltage (V) -35
-50 -60 -70 -25
Figure 8
Forward TLP characteristicNote: [2]
Note: TLP parameter: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between IPP1 = 10 A and IPP2 = 40 A. The equivalent stress level VIEC according IEC 61000-4-2 (R = 330 Ω , C = 150 pF) is calculated at the broad peak of the IEC waveform at t = 30 ns with 2 A / kV
Preliminary Data Sheet 12 Revision 0.9, 2010-10-14
ESD3V3U4ULC
Application Information
4
Application Information
To design USB3.0 link for best system level ESD performance and error free Signal Integrity is mandatory. To bring both requirements together, the ESD protection devices has to provide excellent ESD and a very low device capacitance. The Infineon ESD3V3U4ULC in “array” configuration, combined with a clear and straight forward “full through” layout fulfills these requirements in the best way.
TVS ESD diodes
TX+ SuperSpeed Data IN + TXUSB3.0: SS-Hub e.g. PC TXmated connector RX+ SuperSpeed Data OUT + RX+ RXUSB3.0 cable SS transmission channel TXmated connector RX+ TXRXRXUSB3.0: SS-Device e.g. storage TX+ TX+ RX+ RX+ SuperSpeed Data OUT
TX+ + SuperSpeed Data IN
TVS ESD diodes
Figure 9
USB3.0 structure with ESD protection devices [3]
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ESD3V3U4ULC
Ordering information scheme
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Ordering information scheme
ESD
0P1
RF
- XX YY
Package XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP For R adio Frequency Applications Line Capacitance C L in pF: (i.e.: 0P1 = 0.1pF)
ESD 5V3 U n U - XX YY
Package or Application XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP S = SOT363 U = SC74 XX = Application family: LC = Low Clamp HDMI
U ni- / B i-directional or R ail to Rail protection N umber of protected lines (i.e.: 1 = 1 line; 4 = 4 lines) Capacitance: Standard (>10pF), Low (