IPSH6N03LAG

IPDH6N03LA G IPSH6N03LA G IPFH6N03LA G IPUH6N03LA G OptiMOS®2 Power-Transistor Features • Ideal for high-frequency dc/dc converters • Qualified according to JEDEC1) for target application • N-channel, logic level • Excellent gate charge x R DS(on) product (FOM) • Superior thermal resistance • 175 °C operating temperature • Pb-free lead plating; RoHS compliant Product Summary V DS R DS(on),max (SMD version) ID 25 6 50 V mΩ A Type IPDH6N03LA G IPFH6N03LA G IPSH6N03LA G IPUH6N03LA G Package Marking PG-TO252-3-11 H6N03LA PG-TO252-3-23 H6N03LA PG-TO251-3-11 H6N03LA PG-TO251-3-1 H6N03LA Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID T C=25 °C2) T C=100 °C Pulsed drain current Avalanche energy, single pulse Reverse diode d v /dt Gate source voltage4) Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 I D,pulse E AS dv /dt V GS P tot T j, T stg T C=25 °C T C=25 °C3) I D=50 A, R GS=25 Ω I D=50 A, V DS=20 V, di /dt =200 A/µs, T j,max=175 °C Value 50 50 350 150 6 ±20 71 -55 ... 175 55/175/56 mJ kV/µs V W °C Unit A Rev. 1.5 page 1 2008-04-14 IPDH6N03LA G IPSH6N03LA G Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area5) Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=30 µA V DS=25 V, V GS=0 V, T j=25 °C V DS=25 V, V GS=0 V, T j=125 °C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=30 A V GS=4.5 V, I D=30 A, IPD version V GS=10 V, I D=50 A V GS=10 V, I D=50 A, IPD version Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=50 A 25 1.2 1.6 0.1 Values typ. IPFH6N03LA G IPUH6N03LA G Unit max. 2.1 75 50 K/W 2 1 V µA 35 10 10 8.2 8 5.2 5 1.3 69 100 100 10.2 10 6.2 6 Ω S nA mΩ 1) J-STD20 and JESD22 Current is limited by bondwire; with an R thJC=2.1 K/W the chip is able to carry 80 A. See figure 3 T j,max=150 °C and duty cycle D