IPSH6N03LB

Type IPUH6N03LB IPSH6N03LB OptiMOS®2 Power-Transistor Package Marking • Qualified according to JEDEC1) for target applications • N-channel - Logic level • Excellent gate charge x R DS(on) product (FOM) • Superior thermal resistance • 175 °C operating temperature • Pb-free lead plating; RoHS compliant Product Summary V DS R DS(on),max ID 30 6.3 50 V mΩ A Type IPUH6N03LB IPSH6N03LB Package Marking PG-TO251-3 H6N03LB PG-TO251-3-11 H6N03LB Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Value Unit Continuous drain current ID T C=25 °C2) T C=100 °C 50 50 200 160 6 ±20 A Pulsed drain current Avalanche energy, single pulse Reverse diode d v /dt Gate source voltage4) Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 1) I D,pulse E AS dv /dt V GS P tot T j, T stg T C=25 °C3) I D=50 A, R GS=25 Ω I D=50 A, V DS=20 V, di /dt =200 A/µs, T j,max=175 °C mJ kV/µs V W °C T C=25 °C 83 -55 ... 175 55/175/56 J-STD20 and JESD22 Rev. 0.3 page 1 2006-05-15 IPUH6N03LB Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area5) Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=40 µA V DS=30 V, V GS=0 V, T j=25 °C V DS=30 V, V GS=0 V, T j=125 °C Gate-source leakage current I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=30 A V GS=10 V, I D=50 A Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=50 A 30 1.2 1.6 0.1 Values typ. IPSH6N03LB Unit max. 1.8 62 40 K/W 2 1 V µA 39 10 10 7.4 5.2 1.2 78 100 100 9.3 6.3 Ω S nA mΩ 2) Current is limited by bondwire; with an R thJC=1.8 K/W the chip is able to carry 86 A. See figure 3 T j,max=150 °C and duty cycle D