KSZ8895FMQ

KSZ8895MQ/RQ/FMQ Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface Rev. 1.2 General Description The KSZ8895MQ/RQ/FMQ is a highly-integrated Layer 2 managed five-port switch with optimized design and plentiful features. It is designed for cost-sensitive 10/100Mbps five-port switch systems with lowest power consumption, on-chip termination and internal core power controller. These features will save more system cost. It supports high-performance memory bandwidth, shared memory based switch fabric with non-blocking configuration. It also provides an extensive feature set such as power management, programmable rate limit and priority ratio, tag/port-based VLAN, packets filtering, four queues QoS prioritization, management interfaces and MIB counters. KSZ8895 family provides multiple CPU data interfaces to effectively address both current and emerging fast Ethernet applications when port 5 is configured to separate MAC5 with SW5-MII/RMII and PHY5 with P5-MII/RMII interfaces. The configurations provided by the KSZ8895 family enables the flexibility to meet different requirements: • • • KSZ8895MQ: Five 10/100Base-T/TX transceivers, one SW5-MII and one P5-MII interface KSZ8895RQ: Five 10/100Base-T/TX transceivers, one SW5-RMII and one P5-RMII interface KSZ8895FMQ: Three 10/100Base-T/TX transceiver on Ports 1, 2, 5 and two 100Base-FX transceivers on Ports 3, 4, one SW5-MII and one P5-MII interface All registers of MACs and PHYs units can be managed by the SPI or the SMI interface. MIIM registers can be accessed through the MDC/MDIO interface. EEPROM can set all control registers for the unmanaged mode. Functional Diagram Note: SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com January 2011 M9999-012011-1.2 Micrel, Inc. KSZ8895MQ/RQ/FMQ • Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC address lookup table and a store-and-forward architecture. On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table). Full duplex IEEE 802.3x flow control (PAUSE) with force mode option. Half-duplex back pressure flow control. HP Auto MDI/MDI-X and IEEE Auto crossover support. SW-MII interface supports both MAC mode and PHY mode. 7-wire serial network interface (SNI) support for legacy MAC. Per port LED Indicators for link, activity, and 10/100 speed. Register port status support for link, activity, full/half duplex and 10/100 speed. On-chip terminations and internal biasing technology for cost down and lowest power consumption. Features Advanced Switch Features • IEEE 802.1q VLAN support for up to 128 VLAN groups (full-range 4096 of VLAN IDs). • Static MAC table supports up to 32 entries. • VLAN ID tag/untag options, per port basis • IEEE 802.1p/q tag insertion or removal on a per port basis based on ingress port (egress). • Programmable rate limiting at the ingress and egress on a per port basis. • Jitter-free per packet based rate limiting support. • Broadcast storm protection with percentage control (global and per port basis). • IEEE 802.1d rapid spanning tree protocol RSTP support. • Tail tag mode (1 byte added before FCS) support at Port 5 to inform the processor which ingress port receives the packet. • 2.8Gbps high-performance memory bandwidth and shared memory based switch fabric with fully nonblocking configuration. • Dual MII with MAC5 and PHY5 on port 5, SW5MII/RMII for MAC 5 and P5-MII/RMII for PHY 5. • Enable/Disable option for huge frame size up to 2000 Bytes per frame. • IGMP v1/v2 snooping (Ipv4) support for multicast packet filtering. • IPv4/IPv6 QoS support. • Support unknown unicast/multicast address and unknown VID packet filtering. • Self-address filtering. Comprehensive Configuration Register Access • Serial management interface (MDC/MDIO) to all PHYs registers and SMI interface (MDC/MDIO) to all registers. • High speed SPI (up to 25MHz) and I2C master Interface to all internal registers. • I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode. • Control registers configurable on the fly (port-priority, 802.1p/d/q, AN). • • • • • • • • • Switch Monitoring Features • Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII. • MIB counters for fully compliant statistics gathering 34 MIB counters per port. • Loop-back support for MAC, PHY and remote diagnostic of failure. • Interrupt for the link change on any ports. Low Power Dissipation • Full-chip hardware power-down. • Full-chip software power-down and per port software power down. • Energy-detect mode support < 100mW full chip-power consumption when all ports have no activity. • Very-low full chip power consumption (