SPA12N50C3

SPP12N50C3 SPI12N50C3, SPA12N50C3 Cool MOS™ Power Transistor Feature • New revolutionary high voltage technology • Ultra low gate charge • Periodic avalanche rated • Extreme dv/dt rated • Ultra low effective capacitances • Improved transconductance P-TO220-3-31 1 2 3 VDS @ Tjmax RDS(on) ID FP PG-TO220-3-31 PG-TO262- 560 0.38 11.6 PG-TO220 2 V Ω A 1 23 P-TO220-3-1 • PG-TO-220-3-31;-3-111: Fully isolated package (2500 VAC; 1 minute) Type Package Ordering Code SPP12N50C3 PG-TO220 Q67040-S4579 Marking 12N50C3 12N50C3 12N50C3 SPI12N50C3 PG-TO262 Q67040-S4578 SPA12N50C3 Maximum Ratings Parameter PG-TO220FP SP000216322 Symbol Value Unit SPP_I SPA Continuous drain current TC = 25 °C TC = 100 °C ID A 11.6 7 ID puls 11.6 1) 71) Pulsed drain current, tp limited by Tjmax Avalanche energy, single pulse ID=5.5A, VDD =50V 34.8 34.8 A EAS 340 340 mJ Avalanche energy, repetitive tAR limited by Tjmax2) ID=11.6A, VDD=50V EAR 0.6 0.6 Avalanche current, repetitive tAR limited by Tjmax Gate source voltage IAR 11.6 11.6 A VGS ±20 ±30 ±20 ±30 V Gate source voltage AC (f >1Hz) Power dissipation, TC = 25°C VGS Ptot 125 33 W Operating and storage temperature Reverse diode dv/dt 7) T j , Tstg dv/dt -55...+150 15 °C V/ns Rev. 3.0 Page 1 2007-08-30 SPP12N50C3 SPI12N50C3, SPA12N50C3 Maximum Ratings Parameter Symbol Value Unit Drain Source voltage slope V DS = 400 V, ID = 11.6 A, Tj = 125 °C dv/dt 50 V/ns Thermal Characteristics Parameter Symbol min. RthJC RthJC_FP RthJA RthJA_FP RthJA Values typ. max. Unit Thermal resistance, junction - case Thermal resistance, junction - case, FullPAK Thermal resistance, junction - ambient, leaded Thermal resistance, junction - ambient, FullPAK SMD version, device on PCB: @ min. footprint @ 6 cm 2 cooling area 3) Soldering temperature, wavesoldering 1.6 mm (0.063 in.) from case for 10s 4) - 35 - 1 3.8 62 80 62 260 K/W Tsold - °C Electrical Characteristics, at T j=25°C unless otherwise specified Parameter Symbol Conditions min. Drain-source breakdown voltage V(BR)DSS VGS=0V, ID=0.25mA Drain-Source avalanche V(BR)DS VGS=0V, ID=11.6A breakdown voltage Gate threshold voltage Zero gate voltage drain current VGS(th) I DSS ID=500µA, VGS=VDS VDS=500V, VGS=0V, Tj=25°C Tj=150°C Values typ. 600 3 0.1 0.34 0.92 1.4 max. 3.9 500 2.1 - Unit V µA 1 100 100 0.38 nA Ω Gate-source leakage current I GSS VGS=20V, VDS=0V VGS=10V, ID=7A Tj=25°C Tj=150°C Drain-source on-state resistance RDS(on) Gate input resistance RG f=1MHz, open drain Rev. 3.0 Page 2 2007-08-30 SPP12N50C3 SPI12N50C3, SPA12N50C3 Electrical Characteristics, at Tj = 25 °C, unless otherwise specified Parameter Characteristics Transconductance Input capacitance Output capacitance Reverse transfer capacitance Symbol Conditions min. Values typ. 8 1200 400 30 45 92 10 8 45 8 max. - Unit g fs Ciss Coss Crss V DS≥2*I D*RDS(on)max, ID=7A V GS=0V, V DS=25V, f=1MHz - S pF Effective output capacitance,5) Co(er) energy related Effective output capacitance,6) Co(tr) time related Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics Gate to source charge Gate to drain charge Gate charge total Gate plateau voltage Qgs Qgd Qg V GS=0V, V DS=0V to 400V td(on) tr td(off) tf V DD=380V, V GS=0/10V, ID=11.6A, R G=6.8Ω - ns VDD=400V, ID=11.6A - 5 26 49 5 - nC VDD=400V, ID=11.6A, VGS=0 to 10V V(plateau) VDD=400V, ID=11.6A V 1Limited only by maximum temperature 2Repetitve avalanche causes additional power losses that can be calculated as PAV=EAR*f. 3Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain connection. PCB is vertical without blown air. 4Soldering temperature for TO-263: 220°C, reflow 5C o(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 80% V DSS. 6C o(tr) is a fixed capacitance that gives the same charging time as Coss while V DS is rising from 0 to 80% V DSS. 7I