SPD08N50C3_08

SPD08N50C3 Cool MOS™ Power Transistor Feature • New revolutionary high voltage technology • Worldwide best RDS(on) in TO-252 • Ultra low gate charge • Periodic avalanche rated • Extreme dv/dt rated • Ultra low effective capacitances • Improved transconductance VDS @ Tjmax RDS(on) ID 560 0.6 7.6 PG-TO252 V Ω A Type SPD08N50C3 Package PG-TO252 Ordering Code Q67040-S4569 Marking 08N50C3 Maximum Ratings, at TC = 25°C, unless otherwise specified Parameter Symbol ID Value Unit Continuous drain current TC = 25 °C TC = 100 °C A 7.6 4.6 Pulsed drain current, t p limited by Tjmax Avalanche energy, single pulse ID=5.5A, VDD=50V ID puls EAS EAR IAR VGS VGS Ptot Tj , Tstg dv/dt 22.8 230 0.5 7.6 ±20 ±30 mJ Avalanche energy, repetitive tAR limited by Tjmax1) ID=7.6A, VDD=50V Avalanche current, repetitive tAR limited by Tjmax Gate source voltage A V W °C V/ns Gate source voltage AC (f >1Hz) Power dissipation, TC = 25°C 83 -55... +150 15 Operating and storage temperature Reverse diode dv/dt 6) Rev. 2.5 Page 1 2008-04-11 SPD08N50C3 Maximum Ratings Parameter Drain Source voltage slope VDS = 400 V, ID = 7.6 A, Tj = 125 °C Symbol dv/dt Value 50 Unit V/ns Thermal Characteristics Parameter Thermal resistance, junction - case Thermal resistance, junction - ambient, leaded SMD version, device on PCB: @ min. footprint @ 6 cm2 cooling area 2) Soldering temperature, reflow soldering, MSL3 1.6 mm (0.063 in.) from case for 10s 3) Electrical Characteristics Parameter Symbol Conditions min. Drain-source breakdown voltage V(BR)DSS VGS=0V, ID=0.25mA Drain-Source avalanche breakdown voltage Gate threshold voltage Zero gate voltage drain current VGS(th) I DSS ID=350µΑ, VGS=V DS VDS=500V, V GS=0V, Tj=25°C, Tj=150°C Symbol min. RthJC RthJA Values typ. max. 1.5 75 75 50 260 - Unit K/W RthJA Tsold - °C Values typ. 600 3 0.5 0.5 1.5 1.2 max. 3.9 500 2.1 - Unit V V(BR)DS VGS=0V, ID=7.6A µA 1 100 100 0.6 nA Ω Gate-source leakage current I GSS VGS=20V, V DS=0V VGS=10V, ID =4.6A, Tj=25°C Tj=150°C Drain-source on-state resistance RDS(on) Gate input resistance RG f=1MHz, open Drain Rev. 2.5 Page 2 2008-04-11 SPD08N50C3 Electrical Characteristics , at Tj = 25 °C, unless otherwise specified Parameter Transconductance Input capacitance Output capacitance Reverse transfer capacitance Symbol gfs Ciss Coss Crss Conditions min. VDS≥2*ID*R DS(on)max, ID=4.6A VGS=0V, VDS=25V, f=1MHz Values typ. 6 750 350 12 56 30 6 5 60 7 max. - Unit S pF Effective output capacitance,4) Co(er) energy related Effective output capacitance,5) Co(tr) time related Turn-on delay time Rise time Turn-off delay time Fall time td(on) tr td(off) tf VGS=0V, VDS=0V to 400V pF VDD=400V, VGS=0/10V, ID=7.6A, RG =12Ω - ns Gate Charge Characteristics Gate to source charge Qgs Gate to drain charge Gate charge total Gate plateau voltage Qgd Qg V DD=400V, ID=7.6A - 3 17 32 5 - nC V DD=400V, ID=7.6A, V GS=0 to 10V V(plateau) VDD=400V, ID=7.6A V 1Repetitve avalanche causes additional power losses that can be calculated as P =EAR*f. AV 2Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain connection. PCB is vertical without blown air. 3Soldering temperature for TO-263: 220°C, reflow 4C 5C o(er) o(tr) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 6I