SPD50N03S2L-06 G OptiMOS® Power-Transistor
Feature
• N-Channel
Product Summary VDS R DS(on) ID 30 6.4 50
PG- TO252 -3
V mΩ A
• Enhancement mode • Logic Level • High Current Rating • Excellent Gate Charge x R DS(on) product (FOM)
• Superior thermal resistance
• 175°C operating temperature • Avalanche rated • dv/dt rated
° Pb-free lead plating; RoHS compliant
Package SPD50N03S2L-06 G PG- TO252 -3
Type
Marking PN03L06
Maximum Ratings, at Tj = 25 °C, unless otherwise specified Parameter Continuous drain current1)
TC=25°C
Symbol ID
Value 50 50
Unit A
Pulsed drain current
TC=25°C
ID puls EAS EAR dv/dt VGS Ptot T j , Tstg
200 250 13 6 ±20 136 -55... +175 55/175/56 kV/µs V W °C mJ
Avalanche energy, single pulse
ID=50 A , V DD=25V, RGS=25Ω
Repetitive avalanche energy, limited by Tjmax 2) Reverse diode d v/dt
IS=50A, VDS=24V, di/dt=200A/µs, T jmax=175°C
Gate source voltage Power dissipation
TC=25°C
Operating and storage temperature IEC climatic category; DIN IEC 68-1
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SPD50N03S2L-06 G
Thermal Characteristics Parameter Characteristics Thermal resistance, junction - case Thermal resistance, junction - ambient, leaded SMD version, device on PCB:
@ min. footprint @ 6 cm2 cooling area
3)
Symbol min. RthJC RthJA RthJA -
Values typ. 0.7 max. 1.1 100 75 50
Unit
K/W
Electrical Characteristics, at Tj = 25 °C, unless otherwise specified Parameter Static Characteristics Drain-source breakdown voltage
V GS=0V, ID=1mA
Symbol min. V(BR)DSS VGS(th) IDSS IGSS RDS(on) RDS(on) 30 1.2
Values typ. 1.6 max. 2
Unit
V
Gate threshold voltage, VGS = V DS
ID = 85 µA
Zero gate voltage drain current
V DS=30V, VGS=0V, Tj=25°C V DS=30V, VGS=0V, Tj=125°C
µA 0.01 10 1 6.8 4.7 1 100 100 9.2 6.4 nA mΩ
Gate-source leakage current
V GS=20V, VDS=0V
Drain-source on-state resistance
V GS=4.5V, I D=50A
Drain-source on-state resistance
V GS=10V, I D=50A
1Current limited by bondwire ; with an RthJC = 1.1K/W the chip is able to carry ID= 113A at 25°C, for detailed information see app.-note ANPS071E available at www.infineon.com/optimos 2Defined by design. Not subject to production test. 3Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain connection. PCB is vertical without blown air. Page 2
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SPD50N03S2L-06 G
Electrical Characteristics Parameter Dynamic Characteristics Transconductance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time
Gate Charge Characteristics Gate to source charge Gate to drain charge Gate charge total Gate plateau voltage Qgs Qgd Qg
VDD =24V, ID =50A, VGS =0 to 10V VDD =24V, ID =50A
Symbol
Conditions min.
Values typ. 72 1900 740 180 8 19 35 24 max. -
Unit
gfs Ciss Coss Crss td(on) tr td(off) tf
VDS ≥2*ID *RDS(on)max, ID =50A VGS =0V, VDS =25V, f=1MHz
36 -
S
2530 pF 990 270 12 29 53 36 ns
VDD =15V, VGS =10V, ID =50A, RG =3.6Ω
-
6 17.8 52 3.2
8 26.7 68 -
nC
V(plateau) VDD =24V, ID =50A
V
Reverse Diode Inverse diode continuous forward current Inv. diode direct current, pulsed Inverse diode forward voltage Reverse recovery time Reverse recovery charge ISM VSD trr Qrr
V GS=0V, IF=50A V R=15V, I F=lS, diF/dt=100A/µs
IS
TC=25°C
-
0.9 41 46
50 200 1.3 51 58
A
V ns nC
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SPD50N03S2L-06 G
1 Power dissipation Ptot = f (TC) parameter: VGS≥ 4 V
SPD50N03S2L-06
2 Drain current ID = f (T C) parameter: VGS≥ 10 V
55
SPD50N03S2L-06
150
W
A
45 40
120 110
P tot
100 90 80 70 60
ID
100 120 140 160 °C 190
35 30 25 20
50 40 30 20 10 0 0 20 40 60 80 5 0 0 20 40 60 80 15 10
100 120 140 160 °C 190
TC
TC
3 Safe operating area ID = f ( VDS ) parameter : D = 0 , TC = 25 °C
10
3 SPD50N03S2L-06
4 Max. transient thermal impedance Z thJC = f (t p) parameter : D = t p/T
10
1 SPD50N03S2L-06
K/W A
/I
D
t = 7.6µs p 10 µs
10
0
V
DS
10
DS (on )
ID
=
2
Z thJC
100 µs
R
10
-1
D = 0.50 10 10
1 1 ms -2
0.20 0.10 0.05
10
-3
single pulse
0.02 0.01
10
0
10
-1
10
0
10
1
V
10
2
10
-4
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
s
10
0
VDS
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SPD50N03S2L-06 G
5 Typ. output characteristic ID = f (V DS); T j=25°C parameter: tp = 80 µs
120
SPD50N03S2L-06
6 Typ. drain-source on resistance RDS(on) = f (I D) parameter: VGS=10V
21
SPD50N03S2L-06
Ptot = 136W
i h
V [V] GS a b
A
100 90 80
2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.5 10.0
Ω
18 16 14 12 10 8
d
e
f
g
c d e
70 60 50 40 30 20 10
g
f g
fh
i
e
R DS(on)
ID
h
6
d i
4
c b a
2 0 5 0
VGS [V] =
d 3.2 e 3.4 f 3.6 g 3.8 h i 4.5 10.0
0 0 0.5 1 1.5 2 2.5 3 3.5 4
V
10
20
30
40
50
60
70 A
85
VDS
ID
7 Typ. transfer characteristics ID= f ( V GS ); V DS≥ 2 x ID x RDS(on)max parameter: tp = 80 µs
60
8 Typ. forward transconductance g fs = f(I D); T j=25°C parameter: g fs
90
A
50
S
70 45 40 35 30 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 10 0 0 20 40 60 80 100 40 30 20 60 50
V 4 VGS
g fs
ID
A 130 ID
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SPD50N03S2L-06 G
9 Drain-source on-state resistance RDS(on) = f (Tj) parameter : ID = 50 A, VGS = 10 V
SPD50N03S2L-06
10 Typ. gate threshold voltage VGS(th) = f (T j) parameter: VGS = VDS
2.5
Ω
15
V
12
R DS(on)
11 10 9 8 7 6 5 4 3 2 1 0 -60 -20 20 60 100 140 °C 200 typ 98%
V GS(th)
0.415 mA
1.5
83 µA
1
0.5
0 -60
-20
20
60
100
Tj
°C 160 Tj
11 Typ. capacitances C = f (V DS) parameter: VGS=0V, f=1 MHz
10
4
12 Forward character. of reverse diode IF = f (V SD) parameter: T j , tp = 80 µs
10
3 SPD50N03S2L-06
A
pF Ciss
10
2
10
3
Coss
IF
10
1
C
T j = 25 °C typ
Crss
T j = 175 °C typ T j = 25 °C (98%) T j = 175 °C (98%)
10
2
10 5 10 15 20
0
0
V
30
0
0.4
0.8
1.2
1.6
2
2.4 V
3
V DS
VSD
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SPD50N03S2L-06 G
13 Typ. avalanche energy E AS = f (T j) par.: I D = 50 A , V DD = 25 V, R GS = 25 Ω
260
14 Typ. gate charge VGS = f (QGate) parameter: ID = 50 A pulsed
16
SPD50N03S2L-06
mJ
V
220 200 12
E AS
VGS
180 160 140
10
0,2 VDS max
0,8 VDS max
8 120 100 80 60 40 20 0 25 45 65 85 105 125 145 4 6
2
°C 185 Tj
0 0 10 20 30 40 50 60
nC
80
QGate
15 Drain-source breakdown voltage V(BR)DSS = f (Tj) parameter: ID=10 mA
36
SPD50N03S2L-06
V
V(BR)DSS
34 33 32 31 30 29 28 27 -60
-20
20
60
100
140 °C
200
Tj
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SPD50N03S2L-06 G
Package outline: PG-TO252-3
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