SPD50P03LG

SPD50P03L G OptiMOS®-P Power-Transistor Features • P-Channel • Enhancement mode • Logic level • 175°C operating temperature • Avalanche rated • dv /dt rated • High current rating • Pb-free lead-plating, RoHS compliant Product Summary V DS R DS(on),max ID -30 7 -50 V mΩ A PG-TO252-5 Type SPD50P03L G Package PG-TO252-5 Marking 50P03L Tape and reel information 1000 pcs / reel Lead Free Yes Packing Non dry Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID T C=25 °C1) T C=100 °C1) Pulsed drain current Avalanche energy, single pulse Reverse diode d v /dt Gate source voltage Power dissipation Operating and storage temperature ESD class HBM Soldering temperature Value -50 -50 -200 256 -6 ±20 Unit A I D,pulse E AS dv /dt V GS P tot T j, T stg T C=25 °C I D=-50 A, R GS=25 Ω I D=-50 A, V DS=24 V, di /dt =-200 A/µs, T j,max=175 °C mJ kV/µs V W °C T C=25 °C 150 -55…+175 1C 260 55/175/56 IEC climatic category; DIN IEC 68-1 Rev. 1.8 page 1 2008-07-10 SPD50P03L G Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case Thermal resistance, junction - ambient R thJC R thJA minimal footprint 6 cm2 cooling area2) 1 75 50 K/W Values typ. max. Unit Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage V (BR)DSS V GS=0 V, I D=-250 µA V GS(th) V DS=V GS, I D=-250 µA V DS=-30 V, V GS=0 V, T j=25 °C V DS=-30 V, V GS=0 V, T j=175 °C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=-20 V, V DS=0 V V GS=-4.5 V, I D=-30 A V GS=-10 V, I D=-50 A |V DS|>2|I D|R DS(on)max, I D=-50 A -30 -1 -1.5 -2 V Zero gate voltage drain current I DSS - -0.1 -1 µA - -10 -10 8.5 -100 -100 12.5 nA mΩ Drain-source on-state resistance R DS(on) - 5.7 7.0 Transconductance 1) g fs 47 94 - S Current is limited by bondwire; with an R thJC=1 K/W the chip is able to carry 123 A. 2 Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) Rev. 1.8 page 2 2008-07-10 SPD50P03L G Parameter Symbol Conditions min. Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics 3) Gate to source charge Gate to drain charge Gate charge total Gate plateau voltage Reverse Diode Diode continous forward current Diode pulse current Diode forward voltage IS I S,pulse V SD T C=25 °C V GS=0 V, I F=50 A, T j=25 °C V R=-15 V, I F=|I S|, di F/dt =100 A/µs -1 -50 -200 -1.65 V A Q gs Q gd Qg V plateau V DD=-24 V, I D=-50 A VDD=-24 V, ID=-50 A, VGS=0 to -10 V VDD=-24 V, ID=-50 A -14 -35 -95 -3.0 -19 -53 -126 V nC C iss C oss C rss t d(on) tr t d(off) tf V DD=-15 V, V GS=-10 V, I D=-1 A, R G=6 Ω V GS=0 V, V DS=-25 V, f =1 MHz 4590 1220 1000 14.8 21.7 139 104 6880 1830 1500 22 32 208 156 ns pF Values typ. max. Unit Reverse recovery time t rr - 38 47 ns Reverse recovery charge Q rr - 46 57 nC 3) See figure 16 for gate charge parameter definition Rev. 1.8 page 3 2008-07-10 SPD50P03L G 1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); |V GS|≥10 V 160 55 50 45 140 120 40 35 100 P tot [W] 80 -I D [A] 0 40 80 120 160 200 30 25 20 15 10 60 40 20 5 0 0 40 80 120 160 200 0 T C [°C] T C [°C] 3 Safe operating area I D=f(V DS); T C=25 °C; D =0 parameter: t p 103 limited by on-state resistance 1 µs 10 µs 4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T 101 10 2 10 ms 100 µs 100 DC 1 ms Z thJC [K/W] -I D [A] 0.5 101 10-1 0.2 0.1 0.05 0.02 0.01 single pulse 100 10 -1 10-2 10 0 10 1 10 2 10-5 10-4 10-3 10-2 10-1 -V DS [V] t p [s] Rev. 1.8 page 4 2008-07-10 SPD50P03L G 5 Typ. output characteristics I D=f(V DS); T j=25 °C parameter: V GS 200 -10 V -5 V 6 Typ. drain-source on resistance R DS(on)=f(I D); T j=25 °C parameter: V GS 15 180 -4.5 V 160 140 120 -4 V 10 -4.5 V R DS(on) [mΩ ] -I D [A] -5.5 V 100 80 60 40 20 0 0 2 4 -3.5 V 5 -3 V V 6-6.5 V -7 V -10 V -2.5 V 0 6 8 10 0 40 80 120 160 200 -V DS [V] -I D [A] 7 Typ. transfer characteristics I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j 80 C °25 8 Typ. forward transconductance g fs=f(I D); T j=25 °C 70 100 60 C °175 80 50 -I D [A] 40 30 g fs [S] 0 1 2 3 4 60 40 20 20 10 0 0 0 20 40 60 -V GS [V] -I D [A] Rev. 1.8 page 5 2008-07-10 SPD50P03L SPD50P03L G 9 Drain-source on-state resistance R DS(on)=f(T j); I D=-50 A; V GS=-10 V 10 Typ. gate threshold voltage V GS(th)=f(T j); V GS=V DS; I D=-250 µA 11 2.5 2 9 98%. R DS(on) [mΩ ] 7 typ. -V GS(th) [V] 98 % 1.5 typ. 1 2% 5 0.5 3 -60 -20 20 60 100 140 180 0 -60 -20 20 60 100 140 180 T j [°C] T j [°C] 11 Typ. capacitances C =f(V DS); V GS=0 V; f =1 MHz 12 Forward characteristics of reverse diode I F=f(V SD) parameter: T j 104 10000 1000 Ciss Coss 100 C [pF] 103 1000 Crss I F [A] 10 25 °C, typ 175 °C, typ 25 °C, 98% 175 °C, 98% 102 100 1 5 10 15 20 25 0 0.5 1 1.5 2 2.5 0 -V DS [V] -V SD [V] Rev. 1.8 page 6 2008-07-10 SPD50P03L G 13 Avalanche characteristics I AS=f(t AV); R GS=25 Ω parameter: T j(start) 100 14 Typ. gate charge V GS=f(Q gate); I D=-50 A pulsed parameter: V DD 12 C °25 V 6- V 15- V 24- 10 C °100 8 C °150 10 -V GS [V] 1 10 100 1000 -I AV [A] 6 4 2 1 0 0 20 40 60 80 100 120 t AV [µs] -Q gate [nC] 15 Drain-source breakdown voltage V BR(DSS)=f(T j); I D=-250 µA 16 Gate charge waveforms 36 V GS 35 34 33 Qg -V BR(DSS) [V] 32 31 30 29 28 27 -60 -20 20 60 100 140 180 V g s(th) Q g(th) Q sw Q gs Q g ate Q gd T j [°C] Rev. 1.8 page 7 2008-07-10 SPD50P03L G Package Outline PG-TO252-5: Outline Footprint Packaging Tape Dimensions in mm Rev. 1.8 page 8 2008-07-10 SPD50P03L G Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.8 page 9 2008-07-10