TC1766

32-Bit T C1766 32-Bit Single-Chip Microcontroller Bare Die Delivery D ata Sheet V1.10 2010-04 Microcontrollers Edition 2010-04 Published by Infineon Technologies AG 81726 Munich, Germany © 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 32-Bit T C1766 32-Bit Single-Chip Microcontroller Bare Die Delivery D ata Sheet V1.10 2010-04 Microcontrollers TC1766 Bare Die Delivery TC1766 Data Sheet Revision History: V1.10, 2010-04 Previous Version: V1.8 Page 24 3, 4, 19, 26, 27 Subjects ( changes since V1.8) Die placement on surf tape is updated, pad 1 of the die is located at the bottom of the surf tape. Information for carrier tape packing are included at these sections - features, ordering information, storage conditions, die placement and dimension. Trademarks TriCore® is a trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.10, 2010-04 TC1766 Bare Die Delivery Table of Contents Table of Contents Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 We Listen to Your Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 2 2.1 2.2 2.3 2.4 3 3.1 3.1.1 3.1.2 3.1.3 3.2 3.2.1 3.3 4 4.1 4.2 4.3 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . Storage Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wafer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Surf Tape Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carrier Tape Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 6 7 8 18 18 18 19 20 21 21 22 23 23 24 26 Data Sheet 1 V1.9D4, 2009-07 32-Bit Single-Chip Microcontroller TC1766 Bare Die Delivery 1 Summary of Features • High-performance 32-bit super-scaler TriCore v1.3 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 80 MHz operation at full temperature range • Peripheral Control Processor with single cycle instruction (PCP2) – 8 KByte Parameter Memory (PRAM) – 12 KByte Code Memory (CMEM) • Multiple on-chip memories – 56 KByte Local Data Memory (SRAM) – 8 KByte Overlay Memory – 16 KByte Scratch-Pad RAM (SPRAM) – 8 KByte Instruction Cache (ICACHE) – 1504 Kbyte Program Flash (for instruction code and constant data) – 32 Kbyte Data Flash (e.g. 4 Kbyte EEPROM emulation) – 16 KByte Boot ROM • 8-channel DMA Controller • Fast-response interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 • High-performance on-chip bus structure – 64-Bit Local Memory Bus (LMB) to Flash memory – System Peripheral Bus (SPB) for interconnections of functional units • Versatile on-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASCs) with baudrate generator, parity, framing and overrun error detection – Two High Speed Synchronous Serial Channels (SSCs) with programmable data length and shift direction – One Micro Second Bus (MSC) interface for serial port expansion to external power devices – Two high-speed Micro Link Interfaces (MLIs) for serial inter-processor communication – One MultiCAN Module with two CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer Data Sheet 2 V1.10, 2010-04 TC1766 Bare Die Delivery Summary of Features – One General Purpose Timer Array Module (GPTA) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – One 16-channel Analog-to-Digital Converter unit (ADC) with selectable 8-bit, 10-bit, or 12-bit, supporting 32 input channels – One 2-channel Fast Analog-to-Digital Converter unit (FADC) with concatenated comb filters for hardware data reduction: supporting 10-bit resolution, with minimum conversion time of 262.5ns 32 analog input lines for ADC and FADC 81 digital general purpose I/O lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 and 2 (CPU, PCP, DMA) Dedicated Emulation Device chip for multi-core debugging, tracing, and calibration via USB V1.1 interface available (TC1766ED) Power Management System Clock Generation Unit with PLL Core supply voltage of 1.5V I/O voltage of 3.3 V Die temperature under operating condition: -40° to +150°C Packaging: bare dies mounted on surf tape1) • • • • • • • • • • • 1) Surf Tape packing will be replaced by Carrier Tape packing in the second quarter of 2010. Data Sheet 3 V1.10, 2010-04 TC1766 Bare Die Delivery Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • The derivative itself, i.e. its function set, the temperature range, and the supply voltage • The package and the type of delivery For the available ordering codes for the TC1766 bare die, please refer to the “Product Catalog Microcontrollers” that summarizes all available microcontroller variants. This document describes the derivatives of the device. Table 1 enumerates the derivative. Table 1 Derivative SAL-TC1766-192F80U TC1766 Derivative Synopsis Package Bare die mounted on surf tape1) Notes/Conditions TD = -40oC to +150oC; fSYS = 80 MHz; 8 Kbyte OVRAM TC1766 Bare Die Data Sheet mainly covers bare die related parameters and specification issues. All other TC1766 characteristics and parameters are defined in the TC1766 package Data Sheet. Note: All references of this document are based on V1.0 or higher of the TC1766 package Data Sheet. Data Sheet 4 V1.10, 2010-04 TC1766 Bare Die Delivery General Device Information 2 2.1 General Device Information Block Diagram FPU TriCore (TC1.3M) CPS PMI 1 6 KB SPRAM 8 KB ICACHE DMI 56 KB LDRAM Local Memory Bus (LMB) PMU 16 KB BROM 1504 KB Pflash 32 KB DFlash 8 KB OVRAM Overl ay Me chan ism LBCU LFI Bridge Abbreviations: ICACHE: SPRAM: LDRAM: OVRAM: BROM: PFlash: DFlash: PRAM: CMEM: Shaded: Instruction Cache Scratch-Pad RAM Local Data RAM Overlay RAM Boot ROM Program Flash Data Flash Parameter Memory in PCP Code Memory in PCP Only available in TC1766ED Emulation Memory Interface 8 KB PRAM Interru pts OCDS Debug Interface/JTAG System Peri phe ral Bus (SPB) FPI-Bus Interface PCP2 Core STM ASC0 ASC1 SCU PLL PLL f FPI f CPU Ports DMA Bus 12 KB CMEM SBCU SSC0 SSC1 8 ch. SMIF FADC 2 ch. Ext. Request Unit Multi CAN (2 Nodes, 64 Buffer) MSC0 Mem Check MLI1 MLI0 MCB06056_bd Figure 1 TC1766 Block Diagram Data Sheet 5 V1.10, 2010-04 Ana log Inp ut Assi gnme nt GPTA DMA BI0 BI1 ADC0 32 ch. TC1766 Bare Die Delivery General Device Information 2.2 Pad Configuration Alternate Functions PORST HDRST General Control NMI BYPASS TESTMODE FCLP0A FCLN0 SOP0A SON0 AN[35:0] Port 0 16-Bit Port 1 15-Bit Port 2 14-Bit Port 3 16-Bit Port 4 4-Bit Port 5 16-Bit TRST TCK TDI TDO TMS BRKIN BRKOUT TRCLK XTAL1 XTAL2 VDDOSC3 GPTA, SCU GPTA, SSC1, ADC SSC0/1, MLI0, GPTA, MSC0 ASC0/1, SSC0/1, SCU, CAN GPTA, SCU GPTA, OCDS L2, MLI0/1 MSC0 Control ADC Analog Inputs VDDM VSSM VDDMF ADC/FADC Analog Power Supply TC1766 VSSMF VDDAF VSSAF VAREF0 VAGND0 VFAREF VFAGND VDDFL3 VDD VDDP VSS OCDS / JTAG Control 7 8 9 Digital Circuitry Power Supply VSSOSC3 VDDOSC VSSOSC Oscillator MCB06066 Figure 2 TC1766 Pad Configuration Data Sheet 6 V1.10, 2010-04 TC1766 Bare Die Delivery General Device Information 2.3 Pad Configuration Note: There are four pad pairs which are converted to giant pads in BF-step, these are pad pairs numbered 25 and 26, 65 and 66, 169 and 170, 190 and 191. For more details, please refer to footnotes 2 to 5 in Table 2. 179 180 116 115 y 231 55 1 0.0 x Pad_Config_c 54 0.0 Figure 3 TC1766 Pad Configuration (top view) Data Sheet 7 V1.10, 2010-04 TC1766 Bare Die Delivery General Device Information 2.4 Table 2 Pad Definitions and Functions Pad Definitions and Functions In / Out I I I I I I – – – – I I I I I I I I I I I I I – – – – Position [mm] Function x 321 446 571 696 821 946 1071 1196 1321 1446 1571 1696 1821 1946 2071 2196 2321 2446 2571 2696 2821 2946 3071 3335 3415 3495 3575 y 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 Core and Logic and SRAM memory power supply (1.5V) 8 V1.10, 2010-04 Pad Pad Name Num (Symbol) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 AN19 AN18 AN17 AN16 AN15 AN14 Analog input 19 Analog input 18 Analog input 17 Analog input 16 Analog input 15 Analog input 14 ADC reference ground ADC reference voltage ADC analog part ground ADC analog part power supply (3.3 V) Analog input 13 Analog input 12 Analog input 11 Analog input 10 Analog input 9 Analog input 8 Analog input 6 Analog input 5 Analog input 4 Analog input 3 Analog input 2 Analog input 1 Analog input 0 Core and Logic and SRAM memory power supply (1.5V) Ground VAGND VAREF VSSM VDDM AN13 AN12 AN11 AN10 AN9 AN8 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VDD VSS1)2) VSS1)2) VDD Data Sheet TC1766 Bare Die Delivery General Device Information Table 2 Pad Definitions and Functions (cont’d) In / Out – – – – – I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O – – – – – – – – I/O I/O I/O Position [mm] Function x 3665 3755 3845 3925 4015 4117 4206 4296 4385 4474 4564 4653 4743 4832 4922 5011 5113 5203 5293 5383 5463 5553 5633 5723 5825 5914 6003 y 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 9 Pad Pad Name Num (Symbol) 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 VDDP VDDP IO power supply (3.3V) IO power supply (3.3V) Ground Core and Logic and SRAM memory power supply (1.5V) Ground Port 1 line 14 Port 1 line 13 Port 1 line 12 Port 2 line 0 Port 2 line 1 Port 2 line 2 Port 2 line 3 Port 2 line 4 Port 2 line 5 Port 2 line 6 Port 2 line 7 Ground Ground IO power supply (3.3 V) Core and Logic and SRAM memory power supply (1.5V) Ground Core and Logic and SRAM memory power supply (1.5V) Ground Ground Port 4 line 0 Port 4 line 1 Port 4 line 2 V1.10, 2010-04 VSS VDD1) VSS P1.14 P1.13 P1.12 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 VSS VSS VDDP VDD VSS1) VDD VSS VSS P4.0 P4.1 P4.2 Data Sheet TC1766 Bare Die Delivery General Device Information Table 2 Pad Definitions and Functions (cont’d) In / Out I/O I/O I/O I/O I/O I/O I/O I/O I/O – – – – – – – – – I O – – – – – – Position [mm] Function x 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 y 325 492 658 824 991 1157 1324 1490 1656 1750 1830 1920 2000 2090 2180 2270 2350 2440 2686 2766 2861 2951 3031 3111 3191 3281 Core and Logic and SRAM memory power supply (1.5V) IO power supply (3.3 V) IO power supply (3.3 V) Ground Core and Logic and SRAM memory power supply (1.5V) Ground Oscillator/PLL/Clock generator input Oscillator/PLL/Clock generator output Main oscillator ground Main oscillator ground Main oscillator power supply (1.5 V) Core and Logic and SRAM memory power supply (1.5V) Ground Oscillator power supply (3.3 V) Port 4 line 3 Port 1 line 0 Port 1 line 1 Port 1 line 2 Port 1 line 8 Port 1 line 9 Port 1 line 10 Port 1 line 11 Port 1 line 3 Core and Logic and SRAM memory power supply (1.5 V) Ground Pad Pad Name Num (Symbol) 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P4.3 P1.0 P1.1 P1.2 P1.8 P1.9 P1.10 P1.11 P1.3 VDD VSS1)3) VSS1)3) VDD VDDP VDDP VSS VDD1) VSS XTAL1 XTAL2 VSSOSC VSSOSC VDDOSC VDD1) VSS1) VDDOSC3 Data Sheet 10 V1.10, 2010-04 TC1766 Bare Die Delivery General Device Information Table 2 Pad Definitions and Functions (cont’d) In / Out – – I/O 1) Pad Pad Name Num (Symbol) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Position [mm] Function x 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 6286 y 3416 3506 3620 3743 3867 3979 4090 4202 4348 4494 4641 4787 4946 5026 5106 5265 5424 5504 5663 5822 5902 5992 6072 6162 6252 6342 IO power supply (3.3 V) Ground Port 1 line 4 IO power supply (3.3 V) Port 1 line 5 Port 1 line 6 Port 1 line 7 JTAG module serial data input JTAG module state machine control input JTAG module serial data output JTAG module reset/enable input JTAG module clock input OCDS break output OCDS break input Test mode select input PLL bypass control input Non-maskable interrupt input Power-on reset input Hardware reset input / Reset indication output Core and Logic and SRAM memory power supply (1.5 V) Ground Ground Core and Logic and SRAM memory power supply (1.5V) IO power supply (3.3 V) IO power supply (3.3 V) Ground VDDP VSS1) P1.4 VDDP P1.5 P1.6 P1.7 TDI TMS TDO – I/O I/O I/O I I O I I O I I I I I/O – – – – – – – TRST TCK BRKOUT BRKIN BYPASS NMI PORST HDRST TESTMODE I VDD VSS1) VSS1) VDD VDDP VDDP VSS Data Sheet 11 V1.10, 2010-04 TC1766 Bare Die Delivery General Device Information Table 2 Pad Definitions and Functions (cont’d) In / Out – – I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O – – – – – – – – – – – – Position [mm] Function x 6286 6286 6286 6286 6286 6286 6286 6286 6286 6007 5925 5844 5763 5681 5600 5506 5426 5302 5222 5142 5062 4982 4902 4822 4742 4617 4537 y 6422 6512 6670 6817 6963 7110 7256 7402 7549 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 12 Pad Pad Name Num (Symbol) 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 VDD1) Core and Logic and SRAM memory power supply (1.5V) Ground Port 3 line 5 Port 3 line 6 Port 3 line 8 Port 3 line 2 Port 3 line 3 Port 3 line 7 Port 3 line 4 Port 3 line 15 Port 3 line 14 Port 3 line 1 Port 3 line 0 Port 3 line 10 Port 3 line 9 Ground IO power supply (3.3 V) IO power supply (3.3 V) Ground Core and Logic and SRAM memory power supply (1.5V) Ground Ground Core and Logic and SRAM memory power supply (1.5V) FLASH memory power supply (3.3 V) FLASH memory power supply (3.3 V) Ground IO power supply (3.3 V) V1.10, 2010-04 VSS P3.5 P3.6 P3.8 P3.2 P3.3 P3.7 P3.4 P3.15 P3.14 P3.1 P3.0 P3.10 P3.9 V VDDP VDDP VSS 1) SS VDD1) VSS VSS1) VDD1) VDDP VDDP1) VSS1) VDDP Data Sheet TC1766 Bare Die Delivery General Device Information Table 2 Pad Definitions and Functions (cont’d) In / Out I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O – – – – – – – – O O O O – Position [mm] Function x 4443 4362 4281 4199 4118 4036 3955 3874 3792 3711 3629 3536 3456 3376 3296 3216 3136 3056 2976 2886 2766 2666 2546 2296 y 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 13 Pad Pad Name Num (Symbol) 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 P3.13 P3.12 P3.11 P0.0 P0.1 P0.2 P0.3 P0.8 P0.9 P0.10 P0.11 VDD Port 3 line 13 Port 3 line 12 Port 3 line 11 Port 0 line 0 Port 0 line 1 Port 0 line 2 Port 0 line 3 Port 0 line 8 Port 0 line 9 Port 0 line 10 Port 0 line 11 Core and Logic and SRAM memory power supply (1.5V) Ground Ground Core and Logic and SRAM memory power supply (1.5V) FLASH memory power supply (3.3 V) Ground Core and Logic and SRAM memory power supply (1.5V) Ground MSC0 Differential Driver Clock Output Negative MSC0 Differential Driver Clock Output Positive A MSC0 Differential Driver Serial Data Output Negative A MSC0 Differential Driver Serial Data Output Positive A LVDS Reference V1.10, 2010-04 VSS1) VSS1) VDD VDDP VSS VDD1) VSS FCLN0 FCLP0A SON0A SOP0A NC1) Data Sheet TC1766 Bare Die Delivery General Device Information Table 2 Pad Definitions and Functions (cont’d) In / Out I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O – – – – – – – – I/O I/O I/O I/O I/O I/O I/O I/O I/O Position [mm] Function x 2042 1960 1879 1797 1716 1635 1553 1472 1390 1309 1215 1135 1055 975 895 815 735 655 561 480 398 317 40 40 40 40 40 y 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7852 7553 7376 7200 7023 6847 14 Pad Pad Name Num (Symbol) 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 P2.9 P2.10 P2.11 P2.12 P2.8 P2.13 P0.4 P0.5 P0.12 P0.13 VDD Port 2 line 9 Port 2 line 10 Port 2 line 11 Port 2 line 12 Port 2 line 8 Port 2 line 13 Port 0 line 4 Port 0 line 5 Port 0 line 12 Port 0 line 13 Core and Logic and SRAM memory power supply (1.5V) Ground Core and Logic and SRAM memory power supply (1.5V) IO power supply (3.3 V) Ground Core and Logic and SRAM memory power supply (1.5V) Ground Port 0 line 6 Port 0 line 7 Port 0 line 14 Port 0 line 15 Port 5 line 0 Port 5 line 1 Port 5 line 2 Port 5 line 3 Port 5 line 4 V1.10, 2010-04 VSS1)4) VSS1)4) VDD VDDP VSS VDD1) VSS P0.6 P0.7 P0.14 P0.15 P5.0 P5.1 P5.2 P5.3 P5.4 Data Sheet TC1766 Bare Die Delivery General Device Information Table 2 Pad Definitions and Functions (cont’d) In / Out I/O I/O I/O O – – – – – – – – – I/O I/O I/O I/O I/O I/O I/O I/O – – – – – Position [mm] Function x 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 y 6671 6494 6318 6129 5928 5848 5758 5678 5588 5498 5408 5328 5238 5049 4872 4696 4520 4343 4167 3990 3814 3690 3610 3336 3256 3131 15 Pad Pad Name Num (Symbol) 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 P5.5 P5.6 P5.7 TRCLK Port 5 line 5 Port 5 line 6 Port 5 line 7 OCDS L2 trace clock Core and Logic and SRAM memory power supply (1.5 V) Ground Core and Logic and SRAM memory power supply (1.5 V) IO power supply (3.3 V) IO power supply (3.3 V) Ground Core and Logic and SRAM memory power supply (1.5 V) Ground Port 5 line 8 Port 5 line 9 Port 5 line 10 Port 5 line 11 Port 5 line 12 Port 5 line 13 Port 5 line 14 Port 5 line 15 Core and Logic and SRAM memory power supply (1.5 V) Ground FADC Ground FADC analog part logic power supply (1.5V) Not Connected V1.10, 2010-04 VDD VSS1)5) VSS1)5) VDD VDDP VDDP VSS VDD1) VSS P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 VDD1) VSS1) VSSAF VDDAF NC Data Sheet TC1766 Bare Die Delivery General Device Information Table 2 Pad Definitions and Functions (cont’d) In / Out – – – – I I I I I I I I I I I I I I I I I Position [mm] Function x 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 y 2946 2821 2696 2571 2446 2321 2196 2071 1821 1696 1571 1446 1321 1196 1071 946 821 696 571 446 321 FADC analog power supply (3.3V) FADC Ground ADC reference voltage ADC reference ground FADC[1] negative analog input 35 FADC[1] positive analog input 34 FADC[0] negative analog input 33 FADC[0] positive analog input 32 Analog input 31 Analog input 30 Analog input 29 Analog input 28 Analog input 7 Analog input 27 Analog input 26 Analog input 25 Analog input 24 Analog input 23 Analog input 22 Analog input 21 Analog input 20 Pad Pad Name Num (Symbol) 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 VDDMF VSSMF VFAREF VFAGND AN35 AN34 AN33 AN32 AN31 AN30 AN29 AN28 AN7 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 1) This pad is not bonded in TC1766 package devices 2) Giant pad 1 with the dimension of 162µm x 253.22µm 3) Giant pad 2 with the dimension of 162µm x 253.22µm 4) Giant pad 3 with the dimension of 152µm x 253.22µm 5) Giant pad 4 with the dimension of 152µm x 253.22µm Note: Although not all pads are bonded in TC1766 package, it is recommended to bond as many supply pads as possible in system. Note: All VSS pads must be externally connected together. VDD pads of the same type (e.g. all VDDP lines) should be externally connected together. Data Sheet 16 V1.10, 2010-04 TC1766 Bare Die Delivery General Device Information Note: All dimensions refer to the corner of the die (0,0) within the chip sealing ring. Appropriate adjustment must be made to include sawing tolerances. Data Sheet 17 V1.10, 2010-04 TC1766 Bare Die Delivery Electrical Parameters 3 3.1 3.1.1 Electrical Parameters General Parameters Pad Driver and Pad Classes Summary Please refer to the TC1766 package Data Sheet for the overview of the different pad driver classes and its basic characteristics, DC parameters and Absolute Maximum Ratings. Table 3 shows the assignments of all digital I/O pads to pad classes and to VDD power supply pads. Table 3 Pads Assignments of Digital Pads to Pad Classes and Power Supply Pads Pad Classes Power Supply Port 0, Port 1 [7:0], Port 1 [14:12], Port Class A1 2 line 4, Port 2 [7:6], Port 2 line 13, (3.3 V) Port 3 [11:10], Port 4 [1:0], TDI, BYPASS Port 1 [11:8], Port 2 [3:0], Port 2 line 5, Class A2 Port 2 [12:8], Port 3 [9:0], Port 3 (3.3 V) [15:12], Port 4 [3:2], Port 5, TRST, TCK, TDO, TMS, NMI,PORST, HDRST BRKIN, BRKOUT TRCLK FCLP0A, FCLN0, SOP0A, SON0 AN31 to AN0 Class A3 (3.3 V) Class A4 (3.3 V) Class C (nominal 3.3 V) Class D (nominal 3.3 V) Class D (nominal 3.3 V) (nominal 3.3 V) VDDP VSS VDDP VDDP VDDP VDDP VDDM VDDMF, VDDAF VDDOSC3 VDDOSC VDDFL3 VSSM VSSMF VSSAF VSSOSC VSS VAREF0, VAGND0 AN35 to AN32 VFAREF, VFAGND XTAL1, XTAL2 no functional pads assigned for Flash (nominal 3.3 V) module Data Sheet 18 V1.10, 2010-04 TC1766 Bare Die Delivery Electrical Parameters 3.1.2 Storage Conditions TC1766 dies may be stored for a certain time under the conditions described below. Table 4 Bare Die Storage Conditions and Duration Ambient Storage Condition Atmosphere Atmosphere: >99% Nitrogen or inert gas Temperature: 17°C – 25°C Humidity: 7-25% RH Pressure: slightly above ambient atmospheric pressure Storage Time max. 6 months Storage Type Bare dies mounted Air on surf tape1) with Nitto film. Reels with SurfTape inclusive of desiccant sealed in Moisture Barrier Bag Bare dies mounted on carrier tape, protected with cover tape. Reels with CarrierTape inclusive of desiccant sealed in Moisture Barrier Bag max. 12 months 1) Surf Tape packing will be replaced by Carrier Tape packing in the second quarter of 2010. The dies shall be processed before end of maximum storage time is expired. Processing beyond expiring date is on user’s risk. The storage time starts with the product date code. Data Sheet 19 V1.10, 2010-04 TC1766 Bare Die Delivery Electrical Parameters 3.1.3 Operating Conditions Please refer to the TC1766 package Data Sheet for the details of the Operating Condition Parameters. This section documents the operating condition parameters that are not specified in the TC1766 package Data Sheet. Table 5 Parameter Operating Condition Parameters Symbol Limit Values Min. Max. Digital supply voltage 1) Unit Notes Conditions – – 3) Temperature of the bottom side of the die Overload current VDDSRAM TD IOV SR SR 1.42 -40 – 1.582) V +150 0 °C mA 1) Digital supply voltages applied to the TC1766 must be static regulated voltages which allow a typical voltage swing of ±5%. 2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 µs and the cumulated summary of the pulses does not exceed 1 h. 3) An overload condition is not intended to be a normal operating condition. Data Sheet 20 V1.10, 2010-04 TC1766 Bare Die Delivery Electrical Parameters 3.2 3.2.1 DC Parameters Input/Output Pins Table 6 provides the characteristics of the input/output pins which are specific for the TC1766 Bare Die. Please refer to the TC1766 package Data Sheet for the common Input/Output DC Characteristics. Table 6 Parameter Input/Output DC Characteristics (Operating Conditions apply) Symbol Limit Values Min. Max. Class A Pads (3.3V-5% ≤ VDDP ≤ 3.3V-3%) Output high voltage1) Unit Notes Conditions VOHA CC 2.4 – V IOH = -1.3 mA for medium driver mode, A1/A2 pads IOH = -1 mA for medium driver mode, A1/A2 pads IOH = -280 µA for weak driver mode, A1/A2 pads - 0.6 VDDP – V Class A Pads (3.3V-3% < VDDP ≤ 3.3V+5%) Note: Please refer to TC1766 package Data Sheet. 1) IOH and VOHA are based on TD = 150°C. Data Sheet 21 V1.10, 2010-04 TC1766 Bare Die Delivery Electrical Parameters 3.3 Table 7 Item Wafer Characteristics Wafer Characteristics Characteristic 7 1st metallisation: Cu 2nd metallisation: Cu 3rd metallisation: Cu 4th metallisation: Cu 5th metallisation: Cu 6th metallisation: Cu 7th metallisation (BD-step): AlCu 7th metallisation (BF-step): AlCu, NiP, Pd, Au Met1: 0.29 µm Met2: 0.32 µm Met3: 0.33 µm Met4: 0.32 µm Met5: 0.55 µm Met6: 0.55 µm Met7(BD-step): 1.2 µm Met7(BF-step): 4.53 µm Oxide/Nitride/Imide (subject to change) 0.45 / 0.4 / 5 µm none (silicon), must be connected to VSS Metallization layers Metallization material Metallization thickness Topside passivation Backside metallization Data Sheet 22 V1.10, 2010-04 TC1766 Bare Die Delivery Packaging 4 4.1 Packaging Chip Outline 300 179 180 ................ ...... 116 115 ................... ................... ...................... d3 d2 y Pad 231 Pad 1 65 x 80 65 d1 Typical dimensions in µm 6326 55 54 Pad 54 Chip_outline Figure 4 Data Sheet Chip Outline (top view) 23 V1.10, 2010-04 7892 TC1766 Bare Die Delivery Packaging Table 8 Parameter Distance between pads Distance from border of die to border of chip, x-axis Distance from border of die to border of chip, y-axis Dimensions of Pads Layout Symbol min. d1 d2 d3 80 0 0 Limit Values typ. 125 57 104 max. 274 114 208 µm µm µm Unit 4.2 Surf Tape Characteristics Note: Surf Tape packing will be replaced by Carrier Tape packing in the second quarter of 2010. Sprocket Holes Pad 231 Pad 1 Sticky Tape SurfTape _Config Figure 5 Die Placement on Surf Tape (top View) Data Sheet 24 V1.10, 2010-04 TC1766 Bare Die Delivery Packaging Figure 6 Surf Tape Dimensions Data Sheet 25 V1.10, 2010-04 TC1766 Bare Die Delivery Packaging 4.3 Carrier Tape Characteristics Sprocket Holes Pad 231 Pad 1 CarrierTape _Config Figure 7 Die Placement on Carrier Tape (top View) Data Sheet 26 V1.10, 2010-04 TC1766 Bare Die Delivery Packaging Figure 8 Carrier Tape Dimensions Data Sheet 27 V1.10, 2010-04 www.infineon.com Published by Infineon Technologies AG