TC1767

32-Bit T C1767 32-Bit Single-Chip Microcontroller D ata Sheet V1.3 2009-09 Microcontrollers Edition 2009-09 Published by Infineon Technologies AG 81726 Munich, Germany © 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 32-Bit T C1767 32-Bit Single-Chip Microcontroller D ata Sheet V1.3 2009-09 Microcontrollers TC1767 TC1767 Data Sheet Revision History: V1.3, 2009-09 Previous Version: V1.2 Page 98 104 118 Subjects (major changes since last revision) IDD at 80MHz for Infineon Power Loop and text for test condition are updated. Footnotes for application reset boot time, tB are enhanced. The method used for the specified thermal resistance values is included. Trademarks TriCore® is a trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.3, 2009-09 TC1767 Table of Contents Table of Contents 1 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.2 2.2.1 2.2.2 2.2.3 2.2.3.1 2.2.3.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.4.1 2.3.4.2 2.3.4.3 2.3.4.4 2.3.4.5 2.3.5 2.3.6 2.3.6.1 2.3.6.2 2.3.6.3 2.3.6.4 2.3.6.5 2.3.7 2.3.8 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Related Documentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Reserved, Undefined, and Unimplemented Terminology . . . . . . . . . . . . 9 Register Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 System Architecture of the TC1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TC1767 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System Features of the TC1767 device . . . . . . . . . . . . . . . . . . . . . . . . 15 On Chip CPU Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 High-performance 32-bit CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 High-performance 32-bit Peripheral Control Processor . . . . . . . . . . . 17 On Chip System Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Flexible Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Die Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 General Purpose I/O Ports and Peripheral I/O Lines . . . . . . . . . . . . . . . 22 Program Memory Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Overlay RAM and Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Emulation Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Tuning Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program and Data Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Access Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TC1767 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 On-Chip Peripheral Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Asynchronous/Synchronous Serial Interfaces . . . . . . . . . . . . . . . . . . . . 29 High-Speed Synchronous Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . 31 Micro Second Channel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MultiCAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Micro Link Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 General Purpose Timer Array (GPTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Data Sheet 1 V1.3, 2009-09 TC1767 Table of Contents 2.4.6.1 2.4.7 2.4.7.1 2.4.7.2 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 3 3.1 3.1.1 3.1.2 4 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.8.1 5.3.8.2 5.3.8.3 Functionality of GPTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FADC Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tool Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Test Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAR Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TC1767 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . TC1767 Pin Configuration: PG-LQFP-176-5 . . . . . . . . . . . . . . . . . . . . . Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 45 45 47 49 49 50 50 51 51 51 52 52 53 75 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 79 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Analog to Digital Converters (ADC0/ADC1) . . . . . . . . . . . . . . . . . . . . . 88 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . . . 93 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 115 SSC Master / Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2 V1.3, 2009-09 Data Sheet TC1767 Table of Contents 5.4 5.4.1 5.4.2 5.4.3 5.4.4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 118 119 120 121 Data Sheet 3 V1.3, 2009-09 TC1767 Summary of Features 1 • Summary of Features High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 133 MHz operation at full temperature range 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 8 Kbyte Parameter Memory (PRAM) – 16 Kbyte Code Memory (CMEM) – 133 MHz operation at full temperature range Multiple on-chip memories – 72 Kbyte Data Memory (LDRAM) – 24 Kbyte Code Scratchpad Memory (SPRAM) – 2 Mbyte Program Flash Memory (PFlash) – 64 Kbyte Data Flash Memory (DFlash, represents 16 Kbyte EEPROM) – Instruction Cache: up to 8 Kbyte (ICACHE, configurable) – Data Cache: up to 4 Kbyte (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM) 8-Channel DMA Controller Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge) Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Two High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 2 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer – One General Purpose Timer Array Modules (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management 32 analog input lines for ADC 4 V1.3, 2009-09 • • • • • • • Data Sheet TC1767 Summary of Features – 2 independent kernels (ADC0, ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply) – Performance for 12 bit resolution (@fADCI = 10 MHz) 4 different FADC input channels Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz) – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) 88 digital general purpose I/O lines (GPIO), 4 input lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus) Dedicated Emulation Device chip available (TC1767ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface Power Management System Clock Generation Unit with PLL Core supply voltage of 1.5 V I/O voltage of 3.3 V Full automotive temperature range: -40° to +125°C Package variant: PG-LQFP-176-5 • • • • • • • • • • • • Data Sheet 5 V1.3, 2009-09 TC1767 Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • • The derivative itself, i.e. its function set, the temperature range, and the supply voltage The package and the type of delivery. For the available ordering codes for the TC1767 please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants. This document describes the derivatives of the device.The Table 1 enumerates these derivatives and summarizes the differences. Table 1 Derivative SAK-TC1767-256F133HL SAK-TC1767-256F80HL TC1767 Derivative Synopsis Ambient Temperature Range TA = -40oC to +125oC TA = -40 C to +125 C o o CPU frequency 133 MHz 80 MHz Data Sheet 6 V1.3, 2009-09 TC1767 Introduction 2 Introduction This Data Sheet describes the Infineon TC1767, a 32-bit microcontroller DSP, based on the Infineon TriCore Architecture. 2.1 About this Document This document is designed to be read primarily by design engineers and software engineers who need a detailed description of the interactions of the TC1767 functional units, registers, instructions, and exceptions. This TC1767 Data Sheet describes the features of the TC1767 with respect to the TriCore Architecture. Where the TC1767 directly implements TriCore architectural functions, this manual simply refers to those functions as features of the TC1767. In all cases where this manual describes a TC1767 feature without referring to the TriCore Architecture, this means that the TC1767 is a direct implementation of the TriCore Architecture. Where the TC1767 implements a subset of TriCore architectural features, this manual describes the TC1767 implementation, and then describes how it differs from the TriCore Architecture. Such differences between the TC1767 and the TriCore Architecture are documented in the section covering each such subject. 2.1.1 Related Documentations A complete description of the TriCore architecture is found in the document entitled “TriCore Architecture Manual”. The architecture of the TC1767 is described separately this way because of the configurable nature of the TriCore specification: Different versions of the architecture may contain a different mix of systems components. The TriCore architecture, however, remains constant across all derivative designs in order to preserve compatibility. This Data Sheets together with the “TriCore Architecture Manual” are required to understand the complete TC1767 micro controller functionality. 2.1.2 Text Conventions This document uses the following text conventions for named components of the TC1767: • • • Functional units of the TC1767 are given in plain UPPER CASE. For example: “The SSC supports full-duplex and half-duplex synchronous communication”. Pins using negative logic are indicated by an overline. For example: “The external reset pin, ESR0, has a dual function.”. Bit fields and bits in registers are in general referenced as “Module_Register name.Bit field” or “Module_Register name.Bit”. For example: “The Current CPU Priority Number bit field CPU_ICR.CCPN is cleared”. Most of the 7 V1.3, 2009-09 Data Sheet TC1767 Introduction register names contain a module name prefix, separated by an underscore character “_” from the actual register name (for example, “ASC0_CON”, where “ASC0” is the module name prefix, and “CON” is the kernel register name). In chapters describing the kernels of the peripheral modules, the registers are mainly referenced with their kernel register names. The peripheral module implementation sections mainly refer to the actual register names with module prefixes. Variables used to describe sets of processing units or registers appear in mixed upper and lower cases. For example, register name “MSGCFGn” refers to multiple “MSGCFG” registers with variable n. The bounds of the variables are always given where the register expression is first used (for example, “n = 0-31”), and are repeated as needed in the rest of the text. The default radix is decimal. Hexadecimal constants are suffixed with a subscript letter “H”, as in 100H. Binary constants are suffixed with a subscript letter “B”, as in: 111B. When the extent of register fields, groups register bits, or groups of pins are collectively named in the body of the document, they are represented as “NAME[A:B]”, which defines a range for the named group from B to A. Individual bits, signals, or pins are given as “NAME[C]” where the range of the variable C is given in the text. For example: CFG[2:0] and SRPN[0]. Units are abbreviated as follows: – MHz = Megahertz – µs = Microseconds – kBaud, kbit = 1000 characters/bits per second – MBaud, Mbit = 1,000,000 characters/bits per second – Kbyte, KB = 1024 bytes of memory – Mbyte, MB = 1048576 bytes of memory In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by 1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The kBaud unit scales the expression preceding it by 1000. The M prefix scales by 1,000,000 or 1048576, and µ scales by .000001. For example, 1 Kbyte is 1024 bytes, 1 Mbyte is 1024 × 1024 bytes, 1 kBaud/kbit are 1000 characters/bits per second, 1 MBaud/Mbit are 1000000 characters/bits per second, and 1 MHz is 1,000,000 Hz. Data format quantities are defined as follows: – Byte = 8-bit quantity – Half-word = 16-bit quantity – Word = 32-bit quantity – Double-word = 64-bit quantity • • • • • Data Sheet 8 V1.3, 2009-09 TC1767 Introduction 2.1.3 Reserved, Undefined, and Unimplemented Terminology In tables where register bit fields are defined, the following conventions are used to indicate undefined and unimplemented function. Furthermore, types of bits and bit fields are defined using the abbreviations as shown in Table 2. Table 2 Bit Function Terminology Description Register bit fields named 0 indicate unimplemented functions with the following behavior. • Reading these bit fields returns 0. • These bit fields should be written with 0 if the bit field is defined as r or rh. • These bit fields have to be written with 0 if the bit field is defined as rw. These bit fields are reserved. The detailed description of these bit fields can be found in the register descriptions. The bit or bit field can be read and written. As rw, but bit or bit field can be also set or reset by hardware. The bit or bit field can only be read (read-only). The bit or bit field can only be written (write-only). A read to this register will always give a default value back. This bit or bit field can be modified by hardware (read-hardware, typical example: status flags). A read of this bit or bit field give the actual status of this bit or bit field back. Writing to this bit or bit field has no effect to the setting of this bit or bit field. Bits with this attribute are “sticky” in one direction. If their reset value is once overwritten by software, they can be switched again into their reset state only by a reset operation. Software cannot switch this type of bit into its reset state by writing the register. This attribute can be combined to “rws” or “rwhs”. Bits with this attribute are readable only when they are accessed by an instruction fetch. Normal data read operations will return other values. Function of Bits Unimplemented, Reserved rw rwh r w rh s f 2.1.4 Register Access Modes Read and write access to registers and memory locations are sometimes restricted. In memory and register access tables, the terms as defined in Table 3 are used. Data Sheet 9 V1.3, 2009-09 TC1767 Introduction Table 3 Symbol U SV R 32 E PW NC BE nBE Access Terms Description Access Mode: Access permitted in User Mode 0 or 1. Reset Value: Value or bit is not changed by a reset operation. Access permitted in Supervisor Mode. Read-only register. Only 32-bit word accesses are permitted to this register/address range. Endinit-protected register/address. Password-protected register/address. No change, indicated register is not changed. Indicates that an access to this address range generates a Bus Error. Indicates that no Bus Error is generated when accessing this address range, even though it is either an access to an undefined address or the access does not follow the given rules. Indicates that no Error is generated when accessing this address or address range, even though the access is to an undefined address or address range. True for CPU accesses (MTCR/MFCR) to undefined addresses in the CSFR range. nE 2.1.5 Abbreviations and Acronyms The following acronyms and terms are used in this document: ADC AGPR ALU ASC BCU BROM CAN CMEM CISC CPS CPU Analog-to-Digital Converter Address General Purpose Register Arithmetic and Logic Unit Asynchronous/Synchronous Serial Controller Bus Control Unit Boot ROM & Test ROM Controller Area Network PCP Code Memory Complex Instruction Set Computing CPU Slave Interface Central Processing Unit Data Sheet 10 V1.3, 2009-09 TC1767 Introduction CSA CSFR DAP DAS DCACHE DFLASH DGPR DMA DMI ERU EMI FADC FAM FCS FIM FPI FPU GPIO GPR GPTA ICACHE I/O JTAG LBCU LDRAM LFI LMB LTC MLI MMU MSB MSC Context Save Area Core Special Function Register Device Access Port Device Access Server Data Cache Data Flash Memory Data General Purpose Register Direct Memory Access Data Memory Interface External Request Unit Electro-Magnetic Interference Fast Analog-to-Digital Converter Flash Array Module Flash Command State Machine Flash Interface and Control Module Flexible Peripheral Interconnect (Bus) Floating Point Unit General Purpose Input/Output General Purpose Register General Purpose Timer Array Instruction Cache Input / Output Joint Test Action Group = IEEE1149.1 Local Memory Bus Control Unit Local Data RAM Local Memory-to-FPI Bus Interface Local Memory Bus Local Timer Cell Micro Link Interface Memory Management Unit Most Significant Bit Micro Second Channel Data Sheet 11 V1.3, 2009-09 TC1767 Introduction NC NMI OCDS OVRAM PCP PMU PLL PFLASH PMI PMU PRAM RAM RISC SBCU SCU SFR SPB SPRAM SRAM SRN SSC STM WDT Non Connect Non-Maskable Interrupt On-Chip Debug Support Overlay Memory Peripheral Control Processor Program Memory Unit Phase Locked Loop Program Flash Memory Program Memory Interface Program Memory Unit PCP Parameter RAM Random Access Memory Reduced Instruction Set Computing System Peripheral Bus Control Unit System Control Unit Special Function Register System Peripheral Bus Scratch-Pad RAM Static Data Memory Service Request Node Synchronous Serial Controller System Timer Watchdog Timer Data Sheet 12 V1.3, 2009-09 TC1767 Introduction 2.2 System Architecture of the TC1767 The TC1767 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications: • • • Reduced Instruction Set Computing (RISC) processor architecture Digital Signal Processing (DSP) operations and addressing modes On-chip memories and peripherals DSP operations and addressing modes provide the computational power necessary to efficiently analyze complex real-world signals. The RISC load/store architecture provides high computational bandwidth with low system cost. On-chip memory and peripherals are designed to support even the most demanding high-bandwidth real-time embedded control-systems tasks. Additional high-level features of the TC1767 include: • • • • • • • • • • • • Program Memory Unit – instruction memory and instruction cache Serial communication interfaces – flexible synchronous and asynchronous modes Peripheral Control Processor – standalone data operations and interrupt servicing DMA Controller – DMA operations and interrupt servicing General-purpose timers High-performance on-chip buses On-chip debugging and emulation facilities Flexible interconnections to external components Flexible power-management Maximum CPU clock frequency: 133 MHz1) Maximum PCP clock frequency: 133 MHz2) Maximum SPB frequency: 80 MHz3) TC1767 clock frequencies: The TC1767 is a high-performance microcontroller with TriCore CPU, program and data memories, buses, bus arbitration, an interrupt controller, a peripheral control processor, a DMA controller and several on-chip peripherals. The TC1767 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price/performance, real-time responsiveness, computational power, data bandwidth, and power consumption are key design elements. The TC1767 offers several versatile on-chip peripheral units such as serial controllers, timer units, and Analog-to-Digital converters. Within the TC1767, all these peripheral units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect (FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1767 ports are reserved for these peripheral units to communicate with the external world. 1) For CPU frequencies > 80 MHz, 2:1 mode has to be enabled. CPU 2:1 mode means: fSPB = 0.5 * fCPU 2) For PCP frequencies > 80 MHz, 2:1 mode has to be enabled. PCP 2:1 mode means: fSPB = 0.5 * fPCP 3) CPU 1:1 Mode means: fSPB = fCPU . PCP 1:1 mode means: fSPB = fPCP Data Sheet 13 V1.3, 2009-09 TC1767 Introduction 2.2.1 TC1767 Block Diagram Figure 1 shows the block diagram of the TC1767. Abbreviations: ICACHE: DCACHE SPRAM : LDRAM: OVRAM: BROM: PFlash : DFlash: PRAM: CMEM: LBCU Local Memory Bus(LMB) PMU 2 MB PFlash 64 KB DFlash 8 KB OVRAM 16 KB BROM LFI Bridge M PMI 16 KB SPRAM 8 KB ICACHE (Configurable ) FPU TriCore CPU CPS DMI 68 KB LDRAM 4 KB DCACHE (Configurable) Instruction Cache Data Cache Scratch-Pad RAM Local Data RAM Overlay RAM Boot ROM Program Flash Data Flash Parameter RAM in PCP Code RAM in PCP 1,5V, 3.3V Ext. supply S MI F DMA ( 8 Channels) M/ S OCDS Debug Interface/ JTAG MLI 0 8 KB PRAM FPI-Bus Interface Interrupt System Interrupts STM Memcheck P CP2 Core SCU 5V Ext. ADC supply ASC0 System Peripheral Bus (SPB) Ports 16 KB CMEM ADC0 16 Channels ASC1 28 (5V max) SBCU PLL fPLL SSC0 ADC1 16 Channels GTPA0 4 SSC1 FADC (3.3V) 4 diff ch . (3.3V max) 4 LTCA2 Ext. Request Unit Multi CAN (2 Nodes, 64 B uffer) MSC0 (LV DS) BlockDiagram TC 1767 LQFP -176 Figure 1 TC1767 Block Diagram Data Sheet 14 V1.3, 2009-09 TC1767 Introduction 2.2.2 System Features of the TC1767 device The TC1767 has the following features: Packages • PG-LQFP-176-5 package, 0.5 mm pitch Clock Frequencies • • • Maximum CPU clock frequency: 133 MHz1) Maximum PCP clock frequency: 133 MHz2) Maximum SPB clock frequency: 80 MHz3) 1) For CPU frequencies > 80 MHz, 2:1 mode has to be enabled. CPU 2:1 mode means: fSPB = 0.5 * fCPU 2) For PCP frequencies > 80 MHz, 2:1 mode has to be enabled. PCP 2:1 mode means: fSPB = 0.5 * fPCP 3) CPU 1:1 Mode means: fSPB = fCPU . PCP 1:1 mode means: fSPB = fPCP Data Sheet 15 V1.3, 2009-09 TC1767 Introduction 2.2.3 . On Chip CPU Cores The TC1767 includes a high Performance CPU and a Peripheral Control Processor. 2.2.3.1 High-performance 32-bit CPU This chapter gives an overview about the TriCore 1 architecture. TriCore (TC1.3.1) Architectural Highlights • • • • • • • • • • • • • Unified RISC MCU/DSP 32-bit architecture with 4 Gbytes unified data, program, and input/output address space Fast automatic context-switching Multiply-accumulate unit Floating point unit Saturating integer arithmetic High-performance on-chip peripheral bus (FPI Bus) Register based design with multiple variable register banks Bit handling Packed data operations Zero overhead loop Precise exceptions Flexible power management High-efficiency TriCore Instruction Set • • 16/32-bit instructions for reduced code size Data types include: Boolean, array of bits, character, signed and unsigned integer, integer with saturation, signed fraction, double-word integers, and IEEE-754 singleprecision floating point Data formats include: Bit, 8-bit byte, 16-bit half-word, 32-bit word, and 64-bit doubleword data formats Powerful instruction set Flexible and efficient addressing mode for high code density • • • Integrated CPU related On-Chip Memories • Instruction memory: 24 KB total. After reset, configured into:1) – 24 Kbyte Scratch-Pad RAM (SPRAM) – 0 Kbyte Instruction Cache (ICACHE) Data memory: 72 KB total. After reset, configured into:1) • 1) Software configurable. Available options are described in the CPU chapter. Data Sheet 16 V1.3, 2009-09 TC1767 Introduction – 72 Kbyte Local Data RAM (LDRAM) – 0 Kbyte Data Cache (DACHE) On-chip SRAMs with parity error detection High-performance 32-bit Peripheral Control Processor • 2.2.3.2 The PCP is a flexible Peripheral Control Processor optimized for interrupt handling and thus unloading the CPU. Features • • • • • • • • • • • Data move between any two memory or I/O locations Data move with predefined limit supported Read-Modify-Write capabilities Full computation capabilities including basic MUL/DIV Read/move data and accumulate it to previously read data Read two data values and perform arithmetic or logical operation and store result Bit-handling capabilities (testing, setting, clearing) Flow control instructions (conditional/unconditional jumps, breakpoint) Dedicated Interrupt System PCP SRAMs with parity error detection PCP/FPI clock mode 1:1 and 2:1 available Integrated PCP related On-Chip Memories • • 16 Kbyte Code Memory (CMEM) 8 Kbyte Parameter Memory (PRAM) 2.3 On Chip System Units The TC1767 micro controller offers several versatile on-chip system peripheral units such as DMA controller, embedded Flash module, interrupt system and ports. 2.3.1 Flexible Interrupt System The TC1767 includes a programmable interrupt system with the following features: Features • • • • Fast interrupt response Hardware arbitration Independent interrupt systems for CPU and PCP Programmable service request nodes (SRNs) 17 V1.3, 2009-09 Data Sheet TC1767 Introduction • • Each SRN can be mapped to the CPU or PCP interrupt system Flexible interrupt-prioritizing scheme with 255 interrupt priority levels per SRN to choose from Direct Memory Access Controller 2.3.2 The TC1767 includes a fast and flexible DMA controller with independant DMA channels ( DMA Move engine). Features • independent DMA channels – Up to 16 selectable request inputs per DMA channel – 2-level programmable priority of DMA channels within the DMA Sub-Block – Software and hardware DMA request – Hardware requests by selected on-chip peripherals and external inputs 3-level programmable priority of the DMA Sub-Block at the on chip bus interfaces Buffer capability for move actions on the buses (at least 1 move per bus is buffered) Individually programmable operation modes for each DMA channel – Single Mode: stops and disables DMA channel after a predefined number of DMA transfers – Continuous Mode: DMA channel remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated – Programmable address modification – Two shadow register modes (with / w/o automatic re-set and direct write access). Full 32-bit addressing capability of each DMA channel – 4 Gbyte address range – Data block move supports > 32 Kbyte moves per DMA transaction – Circular buffer addressing mode with flexible circular buffer sizes Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit Register set for each DMA channel – Source and destination address register – Channel control and status register – Transfer count register Flexible interrupt generation (the service request node logic for the MLI channel is also implemented in the DMA module) DMA module is working on SPB frequency, LMB interface on LMB frequency. Dependant on the target/destination address, Read/write requests from the Move Engine are directed to the SPB, LMB, MLI or to the the Cerberus. • • • • • • • • • Data Sheet 18 V1.3, 2009-09 TC1767 Introduction 2.3.3 System Timer The TC1767’s STM is designed for global system timing applications requiring both high precision and long range. Features • • • • • • • • Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Flexible interrupt generation based on compare match with partial STM content Driven by maximum 80 MHz (= fSYS, default after reset = fSYS/2) Counting starts automatically after a reset operation STM registers are reset by an application reset if bit ARSTDIS.STMDIS is cleared. If bit ARSTDIS.STMDIS is set, the STM is not reset. STM can be halted in debug/suspend mode Special STM register semantics provide synchronous views of the entire 56-bit counter, or 32-bit subsets at different levels of resolution. The maximum clock period is 256 × fSTM. At fSTM = 80 MHz, for example, the STM counts 28.56 years before overflowing. Thus, it is capable of continuously timing the entire expected product life time of a system without overflowing. In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After one of these reset conditions, the STM is enabled and immediately starts counting up. It is not possible to affect the content of the timer during normal operation of the TC1767. The timer registers can only be read but not written to. The STM can be optionally disabled for power-saving purposes, or suspended for debugging purposes via its clock control register. In suspend mode of the TC1767 (initiated by writing an appropriate value to STM_CLC register), the STM clock is stopped but all registers are still readable. Due to the 56-bit width of the STM, it is not possible to read its entire content with one instruction. It needs to be read with two load instructions. Since the timer would continue to count between the two load operations, there is a chance that the two values read are not consistent (due to possible overflow from the low part of the timer to the high part between the two read operations). To enable a synchronous and consistent reading of the STM content, a capture register (STM_CAP) is implemented. It latches the content of the high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5 is read. Thus, STM_CAP holds the upper value of the timer at exactly the same time when the lower part is read. The second read operation would then read the content of the STM_CAP to get the complete timer value. The content of the 56-bit System Timer can be compared against the content of two compare values stored in the STM_CMP0 and STM_CMP1 registers. Interrupts can be Data Sheet 19 V1.3, 2009-09 TC1767 Introduction generated on a compare match of the STM with the STM_CMP0 or STM_CMP1 registers. Figure 2 provides an overview on the STM module. It shows the options for reading parts of STM content. STM Module 31 23 15 7 0 to DMA etc. STM_CMP0 Compare Register 0 31 23 15 7 0 STM IRQ0 Interrupt Control STM IRQ1 Enable / Disable Clock Control 55 STM_CMP1 47 39 31 Compare Register1 23 15 7 0 56-bit System Timer 00 H 00 H STM_TIM5 STM_CAP STM_TIM6 fSTM Address Decoder STM_TIM4 STM_TIM3 PORST STM_TIM2 STM_TIM1 STM_TIM0 MCB06185_mod Figure 2 General Block Diagram of the STM Module Registers Data Sheet 20 V1.3, 2009-09 TC1767 Introduction 2.3.4 System Control Unit The following SCU introduction gives an overview about the TC1767 System Control Unit (SCU). 2.3.4.1 Clock Generation Unit The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1767. During user program execution the frequency can be programmed for an optimal ratio between performance and power consumption. 2.3.4.2 • • • • • • • • • Features of the Watchdog Timer The main features of the WDT are summarized here. 16-bit Watchdog counter Selectable input frequency: fFPI/256 or fFPI/16384 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes Incorporation of the ENDINIT bit and monitoring of its modifications Sophisticated Password Access mechanism with fixed and user-definable password fields Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1767 is held in reset until a system / class 0 reset occurs. 2.3.4.3 • • • • • • • Reset Operation The following reset request triggers are available: 1 External power-on hardware reset request trigger; PORST, (cold reset) 2 External System Request reset triggers; ESR0 and ESR1 (warm reset) Watchdog Timer (WDT) reset request trigger, (warm reset) Software reset (SW), (warm reset) Debug (OCDS) reset request trigger, (warm reset) JTAG reset (special reset) Resets via the JTAG interface Note: The JTAG and OCDS resets are described in the OCDS chapter. There are two basic types of reset request triggers: Data Sheet 21 V1.3, 2009-09 TC1767 Introduction • Trigger sources that do not depend on a clock, such as the PORST. This trigger force the device into an asynchronous reset assertion independently of any clock. The activation of an asynchronous reset is asynchronous to the system clock, whereas its de-assertion is synchronized. Trigger sources that need a clock in order to be asserted, such as the input signals ESR0, and ESR1, the WDT trigger, the parity trigger, or the SW trigger. • 2.3.4.4 External Interface The SCU provides interface pads for system purpose. Various functions are covered by these pins. Due to the different tasks some of the pads can not be shared with other functions but most of them can be shared with other functions. The following functions are covered by the SCU controlled pads: • • • • • Reset request triggers Reset indication Trap request triggers Interrupt request triggers Non SCU module triggers The first three points are covered by the ESR pads and the last two points by the ERU pads. 2.3.4.5 Die Temperature Measurement The Die Temperature Sensor (DTS) generates a measurement result that indicates directly the current temperature. The result of the measurement can be read via an DTS register. 2.3.5 General Purpose I/O Ports and Peripheral I/O Lines The TC1767 includes a flexible Ports structure with the following features: Features • • • • • • • Digital General-Purpose Input/Output (GPIO) port lines Input/output functionality individually programmable for each port line Programmable input characteristics (pull-up, pull-down, no pull device) Programmable output driver strength for EMI minimization (weak, medium, strong) Programmable output characteristics (push-pull, open drain) Programmable alternate output functions Output lines of each port can be updated port-wise or set/reset/toggled bit-wise Data Sheet 22 V1.3, 2009-09 TC1767 Introduction 2.3.6 Program Memory Unit (PMU) The devices of the AudoF family contain at least one Program Memory Unit. This is named “PMU0”. Some devices contain additional PMUs which are named “PMU1”, … In the TC1767, the PMU0 contains the following submodules: • • • • • • • • • The Flash command and fetch control interface for Program Flash and Data Flash. The Overlay RAM interface with Online Data Acquisition (OLDA) support. The Boot ROM interface. The Emulation Memory interface. The Local Memory Bus LMB slave interface. 2 Mbyte of Program Flash memory (PFlash) 64 Kbyte of Data Flash memory (DFlash, represents 16 Kbyte EEPROM) 16 Kbyte of Boot ROM (BROM) 8 Kbyte Overlay RAM (OVRAM) Following memories are controlled by and belong to the PMU0: The following figure shows the block diagram of the PMU0: To/From Local Memory Bus 64 LMB Interface Slave P MU0 Overlay RAM Interface 64 PMU Control 64 64 ROM Control 64 OVRAM 64 Flash Interface Module 64 DFLASH BROM Emulation Memory Interface PFLASH Emulation Memory (ED chip only ) PMU0_BasicBlockDiag _generic Figure 3 PMU0 Basic Block Diagram Data Sheet 23 V1.3, 2009-09 TC1767 Introduction 2.3.6.1 • • Boot ROM The internal 16 Kbyte Boot ROM (BROM) is divided into two parts, used for: firmware (Boot ROM), and factory test routines (Test ROM). The different sections of the firmware in Boot ROM provide startup and boot operations after reset. The TestROM is reserved for special routines, which are used for testing, stressing and qualification of the component. 2.3.6.2 Overlay RAM and Data Acquisition The overlay memory OVRAM is provided in the PMU especially for redirection of data accesses to program memory to the OVRAM by using the data overlay function. The data overlay functionality itself is controlled in the DMI module. For online data acquisition (OLDA) of application or calibration data a virtual 32 KB memory range is provided which can be accessed without error reporting. Accesses to this OLDA range can also be redirected to an overlay memory. 2.3.6.3 Emulation Memory Interface In TC1767 Emulation Device, an Emulation Memory (EMEM) is provided, which can fully be used for calibration via program memory or OLDA overlay. The Emulation Memory interface shown in Figure 3 is a 64-bit wide memory interface that controls the CPUaccesses to the Emulation Memory in the TC1767 Emulation Device. In the TC1767 production device, the EMEM interface is always disabled. 2.3.6.4 Tuning Protection Tuning protection is required by the user to absolutely protect control data (e.g. for engine control), serial number and user software, stored in the Flash, from being manipulated, and to safely detect changed or disturbed data. For the internal Flash, these protection requirements are excellently fulfilled in the TC1767 with • • • Flash read and write protection with user-specific protection levels, and with dedicated HW and firmware, supporting the internal Flash read protection, and with the Alternate Boot Mode. Special tuning protection support is provided for external Flash, which must also be protected. 2.3.6.5 Program and Data Flash The embedded Flash module of PMU0 includes 2 Mbyte of Flash memory for code or constant data (called Program Flash) and additionally 64 Kbyte of Flash memory used for emulation of EEPROM data (called Data Flash). The Program Flash is realized as Data Sheet 24 V1.3, 2009-09 TC1767 Introduction one independent Flash bank, whereas the Data Flash is built of two Flash banks, allowing the following combinations of concurrent Flash operations: • • • Read code or data from Program Flash, while one bank of Data Flash is busy with a program or erase operation. Read data from one bank of Data Flash, while the other bank of Data Flash is busy with a program or erase operation. Program one bank of Data Flash while erasing the other bank of Data Flash, read from Program Flash. Both, the Program Flash and the Data Flash, provide error correction of single-bit errors within a 64-bit read double-word, resulting in an extremely low failure rate. Read accesses to Program Flash are executed in 256-bit width, to Data Flash in 64-bit width (both plus ECC). Single-cycle burst transfers of up to 4 double-words and sequential prefetching with control of prefetch hit are supported for Program Flash. The minimum programming width is the page, including 256 bytes in Program Flash and 128 bytes in Data Flash. Concurrent programming and erasing in Data Flash is performed using an automatic erase suspend and resume function. A basic block diagram of the Flash Module is shown in the following figure. Control Flash Command State Machine FCS Control FSI SFRs FSRAM Microcode Redundancy Control Voltage Control Addr Bus 64 Address 64 WR_DATA 8 Write Bus Page Write Buffers 256 byte and 128 byte Program Flash ECC Block 64 ECC Code 8 64 RD_DATA PF-Read Buffer 256+32 bit and Read Bus DF-Read Buffer 64+8 bit Bank 0 Data Flash Bank 1 Bank 0 Bank 1 Flash Interface&Control Module FIM PMU Flash Array Module FAM Flash FSI & Array Flash_BasicBlockDiagram _generic.vsd Figure 4 Basic Block Diagram of Flash Module All Flash operations are controlled simply by transferring command sequences to the Flash which are based on JEDEC standard. This user interface of the embedded Flash is very comfortable, because all operations are controlled with high level commands, such as “Erase Sector”. State transitions, such as termination of command execution, or errors are reported to the user by maskable interrupts. Command sequences are Data Sheet 25 V1.3, 2009-09 TC1767 Introduction normally written to Flash by the CPU, but may also be issued by the DMA controller (or OCDS). The Flash also features an advanced read/write protection architecture, including a read protection for the whole Flash array (optionally without Data Flash) and separate write protection for all sectors (only Program Flash). Write protected sectors can be made reprogrammable (enabled with passwords), or they can be locked for ever (ROM function). Each sector can be assigned to up to three different users for write protection. The different users are organized hierarchically. Program Flash Features and Functions • • • • • • 2 Mbyte on-chip Program Flash in PMU0. Any use for instruction code or constant data. 256 bit read interface (burst transfer operation). Dynamic correction of single-bit errors during read access. Transfer rate in burst mode: One 64-bit double-word per clock cycle. Sector architecture: – Eight 16 Kbyte, one 128 Kbyte and seven 256 Kbyte sectors. – Each sector separately erasable. – Each sector lockable for protection against erase and program (write protection). One additional configuration sector (not accessible to the user). Optional read protection for whole Flash, with sophisticated read access supervision. Combined with whole Flash write protection — thus supporting protection against Trojan horse programs. Sector specific write protection with support of re-programmability or locked forever. Comfortable password checking for temporary disable of write or read protection. User controlled configuration blocks (UCB) in configuration sector for keywords and for sector-specific lock bits (one block for every user; up to three users). Pad supply voltage (VDDP) also used for program and erase (no VPP pin). Efficient 256 byte page program operation. All Flash operations controlled by CPU per command sequences (unlock sequences) for protection against unintended operation. End-of-busy as well as error reporting with interrupt and bus error trap. Write state machine for automatic program and erase, including verification of operation quality. Support of margin check. Delivery in erased state (read all zeros). Global and sector status information. Overlay support with SRAM for calibration applications. Configurable wait state selection for different CPU frequencies. Endurance = 1000; minimum 1000 program/erase cycles per physical sector; reduced endurance of 100 per 16 KB sector. Operating lifetime (incl. Retention): 20 years with endurance=1000. 26 V1.3, 2009-09 • • • • • • • • • • • • • • • • • Data Sheet TC1767 Introduction • For further operating conditions see data sheet section “Flash Memory Parameters”. Data Flash Features and Functions • • • • • • 64 Kbyte on-chip Flash, configured in two independent Flash banks of equal size. 64 bit read interface. Erase/program one bank while data read access from the other bank. Programming one bank while erasing the other bank using an automatic suspend/resume function. Dynamic correction of single-bit errors during read access. Sector architecture: – Two sectors of equal size. – Each sector separately erasable. 128 byte pages to be written in one step. Operational control per command sequences (unlock sequences, same as those of Program Flash) for protection against unintended operation. End-of-busy as well as error reporting with interrupt and bus error trap. Write state machine for automatic program and erase. Margin check for detection of problematic Flash bits. Endurance = 30000 (can be device dependent); i.e. 30000 program/erase cycles per sector are allowed, with a retention of min. 5 years. Dedicated DFlash status information. Other characteristics: Same as Program Flash. • • • • • • • • 2.3.7 Data Access Overlay The data overlay functionality provides the capability to redirect data accesses by the TriCore to program memory (segments 8H and AH) called “target memory” to a different memory called “overlay memory”. Depending on the device the following overlay memories can be available: • • • Overlay SRAM in the PMU. Emulation Memory1). External memory2). This functionality makes it possible, for example, to modify the application’s test and calibration parameters (which are typically stored in the program memory) during run time of a program. As the address translation is implemented in the DMI, it affects only data accesses (reads and writes) of the TriCore. Instruction fetches by the TriCore or accesses by any other master (including the debug interface) are not redirected. 1) Only available in Emulation Device “ED”. 2) Only available in Emulation Device with EBU. Data Sheet 27 V1.3, 2009-09 TC1767 Introduction Summary of Features and Functions • • • • • • • 16 overlay ranges (“blocks”) configurable. Support of 8 Kbyte embedded Overlay SRAM (OVRAM) in PMU. Support of up to 256 Kbyte overlay/calibration memory (EMEM)1). Support of up to 2 MB overlay memory in external memory (EBU space)2). Support of Online Data Acquisition into range of up to 32 KB and of its overlay. Support of different overlay memory selections for every enabled overlay block. Sizes of overlay blocks selectable depending on the overlay memory: – OVRAM: from 16 byte to 2 Kbyte. – EMEM1) and external memory2): 1 Kbyte to 128 Kbyte. All configured overlay ranges can be enabled with only one register write access. Programmable flush (invalidate) control for data cache in DMI. TC1767 Development Support • • 2.3.8 Overview about the TC1767 development environment: Complete Development Support A variety of software and hardware development tools for the 32-bit microcontroller TC1767 are available from experienced international tool suppliers. The development environment for the Infineon 32-bit microcontroller includes the following tools: • • • • Embedded Development Environment for TriCore Products The TC1767 On-chip Debug Support (OCDS) provides a JTAG port for communication between external hardware and the system The System Timer (STM) with high-precision, long-range timing capabilities The TC1767 includes a power management system, a watchdog timer as well as reset logic Data Sheet 28 V1.3, 2009-09 TC1767 Introduction 2.4 On-Chip Peripheral Units The TC1767 micro controller offers several versatile on-chip peripheral units such as serial controllers, timer units, and Analog-to-Digital converters. Several I/O lines on the TC1767 ports are reserved for these peripheral units to communicate with the external world. On-Chip Peripheral Units • • • • • • Two Asynchronous/Synchronous Serial Channels (ASC) with baud-rate generator, parity, framing and overrun error detection Two Synchronous Serial Channels (SSC) with programmable data length and shift direction One Micro Second Bus Interface (MSC) for serial communication One CAN Module (MultiCAN) for high-efficiency data handling via FIFO buffering and gateway data transfer One Micro Link Serial Bus Interfaces (MLI) for serial multiprocessor communication One General Purpose Timer Array (GPTA) with a powerful set of digital signal filtering and timer functionality to accomplish autonomous and complex Input/Output management Two Analog-to-Digital Converter Units (ADC0, ADC1) with 8-bit, 10-bit, or 12-bit resolution. One fast Analog-to-Digital Converter Unit (FADC) • • 2.4.1 Asynchronous/Synchronous Serial Interfaces The TC1767 includes two Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1. Both ASC modules have the same functionality. Figure 5 shows a global view of the Asynchronous/Synchronous Serial Interface (ASC). Data Sheet 29 V1.3, 2009-09 TC1767 Introduction Clock Control fASC Address Decoder EIR TBIR TIR RIR RXD ASC Module (Kernel) TXD Port Control RXD TXD Interrupt Control To DMA MCB05762_mod Figure 5 General Block Diagram of the ASC Interface TC1767 and other The ASC provides serial communication between the microcontrollers, microprocessors, or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock that is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal, which can be accurately adjusted by a prescaler implemented as fractional divider. Data Sheet 30 V1.3, 2009-09 TC1767 Introduction Features • Full-duplex asynchronous operating modes – 8-bit or 9-bit data frames, LSB first – Parity-bit generation/checking – One or two stop bits – Baud rate from 5.0 Mbit/s to 1.19 bit/s (@ 80 MHz module clock) – Multiprocessor mode for automatic address/data byte detection – Loop-back capability Half-duplex 8-bit synchronous operating mode – Baud rate from 10.0 Mbit/s to 813.8 bit/s (@ 80 MHz module clock) Double-buffered transmitter/receiver Interrupt generation – On a transmit buffer empty condition – On a transmit last bit of a frame condition – On a receive buffer full condition – On an error condition (frame, parity, overrun error) Implementation features – Connections to DMA Controller – Connections of receiver input to GPTA (LTC) for baud rate detection and LIN break signal measuring • • • • 2.4.2 High-Speed Synchronous Serial Interfaces The TC1767 includes two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1. Both SSC modules have the same functionality. Figure 6 shows a global view of the Synchronous Serial interface (SSC). Data Sheet 31 V1.3, 2009-09 TC1767 Introduction fSSC Clock Control Master MRSTA MRSTB MTSR MTSRA MTSRB MRST SCLKA SCLKB SCLK SLSI[7:1] SLSO[7:0] SLSOANDO[7:0] SLSOANDI[7:0] Enable M/S Select Port Control fCLC Slave MTSR Address Decoder RIR Interrupt Control TIR EIR MRST S SC Module (Kernel) Slave Master Slave Master SCLK SLSI[7:1] SLSO[7:0] SLSOANDO[7:0] DMA Requests MCB06058_mod Figure 6 General Block Diagram of the SSC Interface The SSC supports full-duplex and half-duplex serial synchronous communication up to 40 Mbit/s (@ 80 MHz module clock, Master Mode). The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data are double-buffered. A shift clock generator provides the SSC with a separate serial clock signal. One slave select input is available for slave mode operation. Eight programmable slave select outputs (chip selects) are supported in Master Mode. Data Sheet 32 V1.3, 2009-09 TC1767 Introduction Features • Master and Slave Mode operation – Full-duplex or half-duplex operation – Automatic pad control possible Flexible data format – Programmable number of data bits: 2 to 16 bits – Programmable shift direction: LSB or MSB shift first – Programmable clock polarity: Idle low or idle high state for the shift clock – Programmable clock/data phase: Data shift with leading or trailing edge of the shift clock Baud rate generation – Master Mode: 40.0 Mbit/s to 610.36 bit/s (@ 80 MHz module clock) – Slave Mode: 20 Mbit/s to 610.36 bit/s (@ 80 MHz module clock) Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, phase, baud rate, transmit error) Flexible SSC pin configuration Seven slave select inputs SLSI[7:1] in Slave Mode Eight programmable slave select outputs SLSO in Master Mode – Automatic SLSO generation with programmable timing – Programmable active level and enable control • • • • • • Data Sheet 33 V1.3, 2009-09 TC1767 Introduction 2.4.3 Micro Second Channel Interface The Micro Second Channel (MSC) interface provides serial communication links typically used to connect power switches or other peripheral devices. The serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel. Figure 7 shows a global view of the interface signals of the MSC interface. fMSC Clock Control fCLC FCLP FCLN Downstream Channel Address Decoder SOP SON EN0 EN1 EN2 EN3 Interrupt SR[3:0] Control 4 To DMA ALTINL[15:0] ALTINH[15:0] EMGSTOPMSC MSC Module (Kernel) Upstream Channel 16 16 8 SDI[7:0] MCB06059 Figure 7 General Block Diagram of the MSC Interface The downstream and upstream channels of the MSC module communicate with the external world via nine I/O lines. Eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). One out of eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided on the ALTINL/ALTINH input lines. These input lines are typically connected with other on-chip peripheral units (for example with a timer unit such as the GPTA). An emergency stop input signal makes it possible to set bits of the serial data stream to dedicated values in an emergency case. Clock control, address decoding, and interrupt service request control are managed outside the MSC module kernel. Service request outputs are able to trigger an interrupt or a DMA request. Data Sheet 34 V1.3, 2009-09 TC1767 Introduction Features • • Fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses High-speed synchronous serial transmission on downstream channel – Serial output clock frequency: fFCL = fMSC/2 – Fractional clock divider for precise frequency control of serial clock fMSC – Command, data, and passive frame types – Start of serial frame: Software-controlled, timer-controlled, or free-running – Programmable upstream data frame length (16 or 12 bits) – Transmission with or without SEL bit – Flexible chip select generation indicates status during serial frame transmission – Emergency stop without CPU intervention Low-speed asynchronous serial reception on upstream channel – Baud rate: fMSC divided by 4, 8, 16, 32, 64, 128, or 256 – Standard asynchronous serial frames – Parity error checker – 8-to-1 input multiplexer for SDI lines – Built-in spike filter on SDI lines Selectable pin types of downstream channel interface: four LVDS differential output drivers or four digital GPIO pins • • Data Sheet 35 V1.3, 2009-09 TC1767 Introduction 2.4.4 MultiCAN Controller The MultiCAN module provides two independent CAN nodes in the PG-LQFP-176-5 package, representing two serial communication interfaces. The number of available message objects is 64. MultiCAN Module Kernel fC AN Clock Control fC L C Message Object Buffer 64 Objects Address Decoder Linked List Control CAN Node 1 CAN Node 0 TXDC1 RXDC1 TXDC0 RXDC0 Port Control Interrupt Control CAN Control MCA06060_N2 Figure 8 Overview of the MultiCAN Module The MultiCAN module contains two independently operating CAN nodes with Full-CAN functionality that are able to exchange Data and Remote Frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. All two CAN nodes share a common set of message objects. Each message object can be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to set up a FIFO buffer. The message objects are organized in double-chained linked lists, where each CAN node has its own list of message objects. A CAN node stores frames only into message objects that are allocated to the message object list of the CAN node, and it transmits only messages belonging to this message object list. A powerful, command-driven list controller performs all message object list operations. Data Sheet 36 V1.3, 2009-09 TC1767 Introduction The bit timings for the CAN nodes are derived from the module timer clock (fCAN) and are programmable up to a data rate of 1 Mbit/s. External bus transceivers are connected to a CAN node via a pair of receive and transmit pins. Features • • • • • • • Compliant with ISO 11898 CAN functionality according to CAN specification V2.0 B active Dedicated control registers for each CAN node Data transfer rates up to 1 Mbit/s Flexible and powerful message transfer control and error handling capabilities Advanced CAN bus bit timing analysis and baud rate detection for each CAN node via a frame counter Full-CAN functionality: A set of 64 message objects can be individually – Allocated (assigned) to any CAN node – Configured as transmit or receive object – Setup to handle frames with 11-bit or 29-bit identifier – Identified by a timestamp via a frame counter – Configured to remote monitoring mode Advanced Acceptance Filtering – Each message object provides an individual acceptance mask to filter incoming frames. – A message object can be configured to accept standard or extended frames or to accept both standard and extended frames. – Message objects can be grouped into four priority classes for transmission and reception. – The selection of the message to be transmitted first can be based on frame identifier, IDE bit and RTR bit according to CAN arbitration rules, or on its order in the list. Advanced message object functionality – Message objects can be combined to build FIFO message buffers of arbitrary size, limited only by the total number of message objects. – Message objects can be linked to form a gateway that automatically transfers frames between 2 different CAN buses. A single gateway can link any two CAN nodes. An arbitrary number of gateways can be defined. Advanced data management – The message objects are organized in double-chained lists. – List reorganizations can be performed at any time, even during full operation of the CAN nodes. – A powerful, command-driven list controller manages the organization of the list structure and ensures consistency of the list. – Message FIFOs are based on the list structure and can easily be scaled in size during CAN operation. 37 V1.3, 2009-09 • • • Data Sheet TC1767 Introduction – Static allocation commands offer compatibility with MultiCAN applications that are not list-based. Advanced interrupt handling – Up to 16 interrupt output lines are available. Interrupt requests can be routed individually to one of the 16 interrupt output lines. – Message post-processing notifications can be combined flexibly into a dedicated register field of 256 notification bits. • Data Sheet 38 V1.3, 2009-09 TC1767 Introduction 2.4.5 Micro Link Interface This TC1767 contains one Micro Link Interface, MLI0. The Micro Link Interface (MLI) is a fast synchronous serial interface to exchange data between microcontrollers or other devices, such as stand-alone peripheral components. Figure 9 shows how two microcontrollers are typically connected together via their MLI interfaces. Controller 1 CPU Controller 2 CPU Peripheral A Peripheral B Peripheral C Peripheral D Memory System Bus MLI MLI System Bus Memory MCA06061 Figure 9 Features • • • • • • • • • • Typical Micro Link Interface Connection Synchronous serial communication between an MLI transmitter and an MLI receiver Different system clock speeds supported in MLI transmitter and MLI receiver due to full handshake protocol (4 lines between a transmitter and a receiver) Fully transparent read/write access supported (= remote programming) Complete address range of target device available Specific frame protocol to transfer commands, addresses and data Error detection by parity bit 32-bit, 16-bit, or 8-bit data transfers supported Programmable baud rate: fMLI/2 (max. fMLI = fSYS) Address range protection scheme to block unauthorized accesses Multiple receiving devices supported Data Sheet 39 V1.3, 2009-09 TC1767 Introduction Figure 10 shows a general block diagram of the MLI module. TREADY[D:A] 4 TVALID[D:A] 4 fSYS TR[3:0] Fract. Divider MLI Transmitter I/O Control TDATA TCLK fMLI BRKOUT Move Engine MLI Module RCLK[D:A] MLI Receiver I/O Control 4 Port Control RREADY[D:A] 4 SR[7:0] RVALID[D:A] RDATA[D:A] 4 4 MCB06062_mod Figure 10 General Block Diagram of the MLI Modules The MLI transmitter and MLI receiver communicate with other MLI receivers and MLI transmitters via a four-line serial connection each. Several I/O lines of these connections are available outside the MLI module kernel as a four-line output or input vector with index numbering A, B, C and D. The MLI module internal I/O control blocks define which signal of a vector is actually taken into account and also allow polarity inversions (to adapt to different physical interconnection means). Data Sheet 40 V1.3, 2009-09 TC1767 Introduction 2.4.6 General Purpose Timer Array (GPTA) The TC1767 contains the General Purpose Timer Array (GPTA0). Figure 11 shows a global view of the GPTA module. The GPTA provides a set of timer, compare, and capture functionalities that can be flexibly combined to form signal measurement and signal generation units. They are optimized for tasks typical of engine, gearbox, and electrical motor control applications, but can also be used to generate simple and complex signal waveforms required for other industrial applications. GPTA0 Clock Generation Cells FPC0 FPC1 FPC2 FPC3 FPC4 FPC5 PDL1 DCM3 PDL0 DCM1 DCM2 DIGITAL PLL DCM0 fGPTA Clock Distribution Cells Clock Conn . GT0 GT1 GTC00 GTC01 GTC02 GTC03 Global Timer Cell Array GTC30 GTC31 Cl ock Bus Signal Generation Cells LTCA2 LTC00 LTC01 LTC02 LTC03 Local Timer Cell Array LTC62 LTC63 LTC00 LTC01 LTC02 LTC03 Local Timer Cell Array LTC30 LTC31 I/O Line Sharing Block Interrupt Sharing Block MCB05910_TC1767_LTC 32 I/O Line Sharing Block Interrupt Sharing Block Figure 11 General Block Diagram of the GPTA Modules in the TC1767 Data Sheet 41 V1.3, 2009-09 TC1767 Introduction 2.4.6.1 Functionality of GPTA0 The General Purpose Timer Array (GPTA0) provides a set of hardware modules required for high-speed digital signal processing: • • • • • • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system. Duty Cycle Measurement Cells (DCM) provide pulse-width measurement capabilities. A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal’s period. Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated Global Timer Cells. Global Timer Cells (GTC) can be programmed to capture the contents of a Global Timer on an external or internal event. A GTC may also be used to control an external port pin depending on the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform. Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be logically tied together to drive a common external port pin with a complex signal waveform. LTCs – enabled in Timer Mode or Capture Mode – can be clocked or triggered by various external or internal events. On-chip Trigger and Gating Signals (OTGS) can be configured to provide trigger or gating signals to integrated peripherals. • • Input lines can be shared by an LTC and a GTC to trigger their programmed operation simultaneously. The following list summarizes the specific features of the GPTA units. Clock Generation Unit • Filter and Prescaler Cell (FPC) – Six independent units – Three basic operating modes: Prescaler, Delayed Debounce Filter, Immediate Debounce Filter – Selectable input sources: Port lines, GPTA module clock, FPC output of preceding FPC cell – Selectable input clocks: GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or uncompensated PLL clock. – fGPTA/2 maximum input signal frequency in Filter Modes Phase Discriminator Logic (PDL) – Two independent units – Two operating modes (2- and 3- sensor signals) 42 V1.3, 2009-09 • Data Sheet TC1767 Introduction – fGPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input signal frequency in 3-sensor Mode Duty Cycle Measurement (DCM) – Four independent units – 0 - 100% margin and time-out handling – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency Digital Phase Locked Loop (PLL) – One unit – Arbitrary multiplication factor between 1 and 65535 – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency Clock Distribution Unit (CDU) – One unit – Provides nine clock output signals: fGPTA, divided fGPTA clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock • • • Signal Generation Unit • Global Timers (GT) – Two independent units – Two operating modes (Free-Running Timer and Reload Timer) – 24-bit data width – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency Global Timer Cell (GTC) – 32 units related to the Global Timers – Two operating modes (Capture, Compare and Capture after Compare) – 24-bit data width – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency Local Timer Cell (LTC) – 64 independent units – Three basic operating modes (Timer, Capture and Compare) for 63 units – Special compare modes for one unit – 16-bit data width – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency • • Interrupt Sharing Unit • 143 interrupt sources, generating up to 46 service requests Data Sheet 43 V1.3, 2009-09 TC1767 Introduction On-chip Trigger Unit • 16 on-chip trigger signals I/O Sharing Unit • Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface Data Sheet 44 V1.3, 2009-09 TC1767 Introduction 2.4.7 Analog-to-Digital Converters The TC1767 includes two Analog to Digital Converter modules (ADC0, ADC1) and one Fast Analog to Digital Converter (FADC). 2.4.7.1 ADC Block Diagram The analog to digital converter module (ADC) allows the conversion of analog input values into discrete digital values based on the successive approximation method. This module contains 2 independent kernels (ADC0, ADC1) that can operate autonomously or can be synchronized to each other. An ADC kernel is a unit used to convert an analog input signal (done by an analog part) and provides means for triggering conversions, data handling and storage (done by a digital part). analog part kernel 0 analog inputs AD converter conversion control analog part kernel 1 analog inputs AD converter conversion control ... ... digital part kernel 0 data (result) handling request control digital part kernel 1 data (result) handling request control ADC_2_kernels bus interface Figure 12 ADC Module with two ADC Kernels Features of the analog part of each ADC kernel: • • • • • • Input voltage range from 0V to analog supply voltage Analog supply voltage range from 3.3 V to 5 V (single supply) (5V nominal supply voltage, performance degradation accepted for lower voltages) Input multiplexer width of 16 possible analog input channels (not all of them are necessarily available on pins) VAREF and 1 alternative reference input at channel 0 Programmable sample time (in periods of fADCI) Wide range of accepted analog clock frequencies fADCI 45 V1.3, 2009-09 Data Sheet TC1767 Introduction • • • • • • • • • • • • • • Multiplexer test mode (channel 7 input can be connected to ground via a resistor for test purposes during run time by specific control bit) Power saving mechanisms Independent result registers (16 independent registers) 5 conversion request sources (e.g. for external events, auto-scan, programmable sequence, etc.) Synchronization of the ADC kernels for concurrent conversion starts Control an external analog multiplexer, respecting the additional set up time Programmable sampling times for different channels Possibility to cancel running conversions on demand with automatic restart Flexible interrupt generation (possibility of DMA support) Limit checking to reduce interrupt load Programmable data reduction filter by adding conversion results Support of conversion data FIFO Support of suspend and power down modes Individually programmable reference selection for each channel (with exception of dedicated channels always referring to VAREF) Features of the digital part of each ADC kernel: Data Sheet 46 V1.3, 2009-09 TC1767 Introduction 2.4.7.2 • • • • • • • • • • • FADC Short Description General Features Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz) 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) Successive approximation conversion method Each differential input channel can also be used as single-ended input Offset calibration support for each channel Programmable gain of 1, 2, 4, or 8 for each channel Free-running (Channel Timers) or triggered conversion modes Trigger and gating control for external signals Built-in Channel Timers for internal triggering Channel timer request periods independently selectable for each channel Selectable, programmable digital anti-aliasing and data reduction filter block with four independent filter units VFAREF VDDAF VDDMF VDDIF VFAGND VSSAF VSSMF Clock Control fFADC fCLC Data Reduction Unit A/D Control Input Structure Interrupt Control DMA TS[H:A] GS[H:A] SRx A/D Converter Stage SRx FAIN0P FAIN0N FAIN1P FAIN1N FAIN2P FAIN2N FAIN3P FAIN3N input channel input channel input channel input channel 0 1 2 3 Channel Trigger Control Channel Timers MCB06065_m4 Figure 13 Block Diagram of the FADC Module with 4 Input Channels As shown in Figure 13, the main FADC functional blocks are: • An Input Structure containing the differential inputs and impedance control. 47 V1.3, 2009-09 Data Sheet TC1767 Introduction • • • • • An A/D Converter Stage responsible for the analog-to-digital conversion including an input multiplexer to select between the channel amplifiers A Data Reduction Unit containing programmable anti-aliasing and data reduction filters A Channel Trigger Control block determining the trigger and gating conditions for the FADC channels A Channel Timer for each channel to independently trigger the conversions An A/D Control block responsible for the overall FADC functionality FADC Power Supply and References The FADC module is supplied by the following power supply and reference voltage lines: • • VDDMF / VSSMF: FADC Analog Channel Amplifier Power Supply (3.3 V) VDDIF / VSSMF: FADC Analog Input Stage Power Supply (3.3 - 5 V), the VDDIF supply does not appear as supply pin, because it is internally connected to the VDDM supply of the ADC that is sharing the FADC input pins. VDDAF / VSSAF: FADC Analog Part Power Supply (1.5 V), to be fed in externally VFAREF / VFAGND: FADC Reference Voltage (3.3 V max.) and FADC Reference Ground • • Input Structure The input structure of the FADC in the TC1767 contains: • A differential analog input stage for each input channel to select the input impedance (differential or single-ended measurement) and to decouple the FADC input signal from the pins. A channel amplifier for each input channel with a settling time (about 5µs) when changing the characteristics of an input stage (changing between unused, differential, single-ended N, or single-ended P mode). • Data Sheet 48 V1.3, 2009-09 TC1767 Introduction FAIN0P FAIN0N Analog Input Stages Rp Rn Channel Amplifier Stages VDDMF Converter Stage VSSMF FAIN2P FAIN2N Rp Rn VSSMF FAIN1P FAIN1N Rp Rn VSSMF FAIN3P FAIN3N Rp Rn VSSMF VDDIF Figure 14 A/D conversion Control control gain CHNR VDDMF VDDMF A/D VDDAF VSSAF VDDMF VSSMF MCA06432_m4n FADC Input Structure in TC1767 2.5 On-Chip Debug Support (OCDS) The TC1767 contains resources for different kinds of “debugging”, covering needs from software development to real-time-tuning. These resources are either embedded in specific modules (e.g. breakpoint logic of the TriCore) or part of a central peripheral (known as CERBERUS). 2.5.1 On-Chip Debug Support The classic software debug approach (start/stop, single-stepping) is supported by several features labelled “OCDS Level 1”: • • • Run/stop and single-step execution independently for TriCore and PCP. Means to request all kinds of reset without usage of sideband pins. Halt-after-Reset for repeatable debug sessions. 49 V1.3, 2009-09 Data Sheet TC1767 Introduction • • • • • • Different Boot modes to use application software not yet programmed to the Flash. A total of four hardware breakpoints for the TriCore based on instruction address, data address or combination of both. Unlimited number of software breakpoints (DEBUG instruction) for TriCore and PCP. Debug event generated by access to a specific address via the system peripheral bus. Tool access to all SFRs and internal memories independent of the Cores. Two central Break Switches to collect debug events from all modules (TriCore, PCP, DMA, BCU, break input pins) and distribute them selectively to breakable modules (TriCore, PCP, break output pins). Central Suspend Switch to suspend parts of the system (TriCore, PCP, Peripherals) instead if breaking them as reaction to a debug event. Dedicated interrupt resources to handle debug events inside TriCore (breakpoint trap, software interrupt) and Cerberus (can trigger PCP), e.g. for implementing Monitor programs. Access to all OCDS Level 1 resources also for TriCore and PCP themselvesitself for debug tools integrated into the application code. Triggered Transfer of data in response to a debug event; if target is programmed to be a device interface simple variable tracing can be done. • • • • Additionally, in depth performance analysis and profiling support is provided by the Emulation Device through MCDS Event Counters driven by a variety of trigger signals (e.g. cache hit, wait state, interrupt accepted). 2.5.2 Real Time Trace For detailed tracing of the system’s behavior a pin-compatible Emulation Device is available.1) 2.5.3 Calibration Support Two main use cases are catered for by resources in addition the OCDS Level 1 infrastructure: Overlay of non-volatile on-chip memory and non-intrusive signaling: • • • • 8 KB SRAM for Overlay. Can be split into up to 16 blocks which can overlay independent regions of on-chip Data Flash. Changing the configuration is triggered by a single SFR access to maintain consistency. Overlay configuration switch does not require the TriCore to be stopped or suspended. 1) The OCDS L2 interface of AudoNG is not available. Data Sheet 50 V1.3, 2009-09 TC1767 Introduction • • • • • Invalidation of the Data Cache (maintaining write-back data) can be done concurrently with the same SFR. 256 KB additional Overlay RAM on Emulation Device. The 256 KB Trace memory of the Emulation Device can optionally be used for Overlay also. A dedicated trigger SFR with 32 independent status bits is provided to centrally post requests from application code to the host computer. The host is notified automatically when the trigger SFR is updated by the TriCore or PCP. No polling via a system bus is required. 2.5.4 Tool Interfaces Three options exist for the communication channel between Tools (e.g. Debugger, Calibration Tool) and TC1767: • • • • • • • • Two wire DAP (Device Access Port) protocol for long connections or noisy environments. Four (or five) wire JTAG (IEEE 1149.1) for standardized manufacturing tests. CAN (plus software linked into the application code) for low bandwidth deeply embedded purposes. DAP and JTAG are clocked by the tool. Bit clock up to 40 MHz for JTAG, up to 80 MHz for DAP. Hot attach (i.e. physical disconnect/reconnect of the host connection without reset of the TC1767) for all interfaces. Infineon standard DAS (Device Access Server) implementation for seamless, transparent tool access over any supported interface. Lock mechanism to prevent unauthorized tool access to critical application code. 2.5.5 Self-Test Support Some manufacturing tests can be invoked by the application (e.g. after power-on) if needed: • Hardware-accelerated checksum calculation (e.g. for Flash content). 2.5.6 FAR Support To efficiently locate and identify faults after integration of a TC1767 into a system special functions are available: • • Boundary Scan (IEEE 1149.1) via JTAG and DAP. SSCM (Single Scan Chain Mode1)) for structural scan testing of the chip itself. 1) This function requires access to some device pins (e.g. TESTMODE) in addition to those needed for OCDS. Data Sheet 51 V1.3, 2009-09 TC1767 Pinning 3 Pinning 3.1 TC1767 Pin Definition and Functions Figure 15 shows the Logic Symbol of the device. PORST TESTMODE ESR0 ESR1 TRST TCK / DAP0 OCDS / JTAG Control TDI / BRKIN TDO / DAP2 / BRKOUT TMS / DAP1 AN[35:0] VD D M VSSM V D D MF V SSMF V D D AF V AR EF0 VAGN D 0 VFAR EF V FAGN D VD D FL3 Digital Circuitry Power Supply VD D VD D P VSS 9 10 11 TC 1767_LogSym_176 Alternate Functions 16 16 14 16 4 16 TC1767 PG-LQFP176 -x 4 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 GPTA, SCU GPTA, SSC1, ADC0, OCDS GPTA, SSC0/1, MLI 0, MSC0 GPTA, ASC0/1, SSC0/1, SCU, CAN GPTA, SCU GPTA, MLI0 GPTA, MSC0 General Control Analog Inputs Analog Power Supply XTAL1 XTAL2 V D D OSC V D D OSC3 V SSOSC Oscillator Figure 15 TC1767 Logic Symbol for the package variant PG-LQFP-176-5. Data Sheet 52 V1.3, 2009-09 Figure 16 1) OUT40/OUT8/IN40/IN26/P5.0 OUT41/OUT9/IN41/IN27/P5.1 OUT42/OUT10/IN42/IN28/P5.2 OUT43/OUT11/IN43/P5.3 OUT44/OUT12/IN44/IN29/P5.4 OUT45/OUT13/IN45/IN30/P5.5 OUT46/OUT14/IN46/IN31/P5.6 OUT47/OUT15/IN47/P5.7 TCLK0/OUT95/P5.15 VDD VDDP VSS RDATA0B/OUT89/P5.8 RVALID0B/OUT90/P5.9 RREADY0B/OUT91/P5.10 RCLK0B/OUT92/P5.11 TDATA0/SLSO07/OUT93/P5.12 TVALID0B/SLSO16/P5.13 TREADY0B/OUT94/P5.14 VDDP VDD(SB) VSS VDDAF VDDM F VSSM F VFAREF VFAG ND AN35 AN34 AN33 AN32 AN31 AN30 AN29 AN28 AN7 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 3.1.1 Data Sheet TC1767 ED: PG-LQFP-176-6 TC1767 TC1767 Pin Configuration: PG-LQFP-176-5 This chapter shows the pin configuration of the package variant PG-LQFP-176-51). TC1767 Pinning for PG-LQFP-176-5 53 AN19 AN18 AN17 AN16 AN15 AN14 VAG ND 0 VARE F0 VS SM VDD M AN13 AN12 AN11 AN10 AN9 AN8 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VDD VDDP VSS A D0EMUX2/OUT18/ IN18/ P1.14 A D0EMUX1/OUT17/ IN17/ P1.13 A D0EMUX0/OUT16/ IN16/ P1.12 TCLK0/OUT28/OUT32/ IN32/P 2. 0 SLSO13/ SLSO03/ OUT33/TREADY0A/ IN33/P 2. 1 TV ALID0A /OUT29/OUT34/ IN34/P 2. 2 TDAT A0/OUT30/OUT35/ IN35/P 2. 3 OUT31/ OUT36/RCLK0A/ IN36/P 2. 4 RRE ADY 0A/OUT37/OUT110/ IN37/P 2. 5 OUT38/OUT111/RVALI D0A/ IN38/P 2. 6 OUT39/RDA TA0A/ IN39/P 2. 7 VSS VDDP VDD VSS OUT52/OUT28/ IN52/ IN28/P 4. 0 OUT53/OUT29/ IN53/ IN29/P 4. 1 EXTCLK1/OUT54/OUT30/ IN54/ IN30/P 4. 2 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 P0.15/IN15/ RE Q5/ OUT15/ OUT71 P0.14/IN14/ RE Q4/ OUT14/ OUT70 P0.7/I N7/HWCFG7/REQ3/ OUT7/OUT63 P0.6/I N6/HWCFG6/REQ2/ OUT6/OUT62 VSS VDDP VDD P0.13/IN13/ OUT13/OUT69 P0.12/IN12/ OUT12/OUT68 P0.5/I N5/HWCFG5/OUT5/ OUT61 P0.4/I N4/HWCFG4/OUT4/ OUT60 P2.13/IN13/ OUT3/S LS I11/ SDI0 P2.8/SLSO04/SLS O14/E N00 P2.12/IN12/ OUT2/MTS R1A/ SOP0B P2.11/IN11/ OUT1/S CLK1A/ FCLP0B P2.10/IN10/ OUT0/MRST1A P2.9/SLSO05/SLS O15/E N01 P6.3/I N25/OUT7/OUT83/ SOP0A P6.2/I N24/OUT6/OUT82/ SON0 P6.1/I N15/OUT5/OUT81/ FCLP0A P6.0/I N14/OUT4/OUT80/ FCLN0 VSS VDDP VDD P0.11/IN11/ OUT11/OUT67 P0.10/IN10/ OUT10/OUT66 P0.9/I N9/OUT9/ OUT65 P0.8/I N8/OUT8/ OUT64 P0.3/I N3/HWCFG3/OUT3/ OUT59 P0.2/I N2/HWCFG2/OUT2/ OUT58 P0.1/I N1/HWCFG1/OUT1/ OUT57 P0.0/I N0/HWCFG0/OUT0/ OUT56 P3.11/OUT93// REQ1 P3.12/OUT94// RXDCAN0/ RXD0B P3.13/OUT95// TXDCAN0/TXD0 VDDFL 3 VSS VDDP P3.9/OUT91/RXD1A P3.10/OUT92/REQ0 P3.0OUT84//RXD0A P3.1OUT85//TX D0 P3.14/OUT96RX DCAN1/ RX D1B P3.15/OUT97/TXDCAN1/ TXD1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 P3.4/OUT88/MTSR0 P3.7/SLSI01/OUT89//SLSO02/SLSO12 P3.3/OUT87/MRST0 P3.2/OUT86/SCLK0 P3.8/SLSO06/OUT90/TXD1 P3.6/SLSO01/SLSO11/SLSO01&SLSO11 P3.5/SLSO00/SLSO10/SLSO00&SLSO10 VSS VDDP VDD ESR0 PORST ESR1 P1.1/IN17/OUT17/OUT73 TESTMODE P1.15/BRKIN/BRKOUT P1.0/IN16/OUT16/OUT72/BRKIN/BRKOUT TCK/DAP0 TRST TDO/DAP2/BRKIN/BRKOUT TMS/DAP1 TDI/BRKIN/BRKOUT P1.7/IN23/OUT23/OUT79 P1.6/IN22/OUT22/OUT78 P1.5/IN21/OUT21/OUT77 P1.4/IN20/EMGSTOP/OUT20/OUT76 VDDO SC3 VDDO SC VSSO SC XTAL2 XTAL1 VSS VDDP VDD P1.3/IN19/OUT19/OUT75 P1.11/IN27/IN51/SCLK1B/OUT27/OUT51 P1.10/IN26/IN50/OUT26/OUT50/SLSO17 P1.9/IN25/IN49/MRST1B/OUT25/OUT49 P1.8/IN24/IN48/MTSR1B/OUT24/OUT48 P1.2/IN18/OUT18/OUT74 V SS VDDP P4.3/IN31/IN55/OUT31/OUT55/EXTCLK0 VDD MCP06067 V1.3, 2009-09 TC1767 Pinning TC1767 Pinning Table 4 Pin Port 0 145 P0.0 IN0 IN0 HWCFG0 OUT0 OUT56 OUT0 146 P0.1 IN1 IN1 HWCFG1 OUT1 OUT57 OUT1 147 P0.2 IN2 IN2 HWCFG2 OUT2 OUT58 OUT2 148 P0.3 IN3 IN3 HWCFG3 OUT3 OUT59 OUT3 I/O0 I I I O1 O2 O3 I/O0 I I I O1 O2 O3 I/O0 I I I O1 O2 O3 I/O0 I I I O1 O2 O3 A1/ PU A1/ PU A1/ PU A1/ PU Port 0 General Purpose I/O Line 0 GPTA0 Input 0 LTCA2 Input 0 Hardware Configuration Input 0 GPTA0 Output 0 GPTA0 Output 56 LTCA2 Output 0 Port 0 General Purpose I/O Line 1 GPTA0 Input 1 LTCA2 Input 1 Hardware Configuration Input 1 GPTA0 Output 1 GPTA0 Output 57 LTCA2 Output 1 Port 0 General Purpose I/O Line 2 GPTA0 Input 2 LTCA2 Input 2 Hardware Configuration Input 2 GPTA0 Output 2 GPTA0 Output 58 LTCA2 Output 2 Port 0 General Purpose I/O Line 3 GPTA0 Input 3 LTCA2 Input 3 Hardware Configuration Input 3 GPTA0 Output 3 GPTA0 Output 59 LTCA2 Output 3 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) Ctrl. Type Function Symbol Data Sheet 54 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 166 P0.4 IN4 IN4 HWCFG4 OUT4 OUT60 OUT4 167 P0.5 IN5 IN5 HWCFG5 OUT5 OUT61 OUT5 173 P0.6 IN6 IN6 HWCFG6 REQ2 OUT6 OUT62 OUT6 174 P0.7 IN7 IN7 HWCFG7 REQ3 OUT7 OUT63 OUT7 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I I I O1 O2 O3 I/O0 I I I O1 O2 O3 I/O0 I I I I O1 O2 O3 I/O0 I I I I O1 O2 O3 A1/ PU A1/ PU A1/ PU Type Function A1/ PU Port 0 General Purpose I/O Line 4 GPTA0 Input 4 LTCA2 Input 4 Hardware Configuration Input 4 GPTA0 Output 4 GPTA0 Output 60 LTCA2 Output 4 Port 0 General Purpose I/O Line 5 GPTA0 Input 5 LTCA2 Input 5 Hardware Configuration Input 5 GPTA0 Output 5 GPTA0 Output 61 LTCA2 Output 5 Port 0 General Purpose I/O Line 6 GPTA0 Input 6 LTCA2 Input 6 Hardware Configuration Input 6 External Request Input 2 GPTA0 Output 6 GPTA0 Output 62 LTCA2 Output 6 Port 0 General Purpose I/O Line 7 GPTA0 Input 7 LTCA2 Input 7 Hardware Configuration Input 7 External Request Input 3 GPTA0 Output 7 GPTA0 Output 63 LTCA2 Output 7 Symbol Data Sheet 55 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 149 P0.8 IN8 IN8 OUT8 OUT64 OUT8 150 P0.9 IN9 IN9 OUT9 OUT65 OUT9 151 P0.10 IN10 OUT10 OUT66 OUT10 152 P0.11 IN11 OUT11 OUT67 OUT11 168 P0.12 IN12 OUT12 OUT68 OUT12 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 A1/ PU A1/ PU A1/ PU A1/ PU Type Function A1/ PU Port 0 General Purpose I/O Line 8 GPTA0 Input 8 LTCA2 Input 8 GPTA0 Output 8 GPTA0 Output 64 LTCA2 Output 8 Port 0 General Purpose I/O Line 9 GPTA0 Input 9 LTCA2 Input 9 GPTA0 Output 9 GPTA0 Output 65 LTCA2 Output 9 Port 0 General Purpose I/O Line 10 GPTA0 Input 10 GPTA0 Output 10 GPTA0 Output 66 LTCA2 Output 10 Port 0 General Purpose I/O Line 11 GPTA0 Input 11 GPTA0 Output 11 GPTA0 Output 67 LTCA2 Output 11 Port 0 General Purpose I/O Line 12 GPTA0 Input 12 GPTA0 Output 12 GPTA0 Output 68 LTCA2 Output 12 Symbol Data Sheet 56 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 169 P0.13 IN13 OUT13 OUT69 OUT13 175 P0.14 IN14 REQ4 OUT14 OUT70 OUT14 176 P0.15 IN15 REQ5 OUT15 OUT71 OUT15 Port 1 116 P1.0 IN16 BRKIN OUT16 OUT72 OUT16 BRKOUT 119 P1.1 IN17 OUT17 OUT73 OUT17 I/O0 I I O1 O2 O3 O I/O0 I O1 O2 O3 A1/ PU A2/ PU Port 1 General Purpose I/O Line 0 GPTA0 Input 16 Break Input GPTA0 Output 16 GPTA0 Output 72 LTCA2 Output 16 Break Output (controlled by OCDS module) Port 1 General Purpose I/O Line 1 GPTA0 Input 17 GPTA0 Output 17 GPTA0 Output 73 LTCA2 Output 17 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I I O1 O2 O3 A1/ PU A1/ PU Type Function A1/ PU Port 0 General Purpose I/O Line 13 GPTA0 Input 13 GPTA0 Output 13 GPTA0 Output 69 LTCA2 Output 13 Port 0 General Purpose I/O Line 14 GPTA0 Input 14 External Request Input 4 GPTA0 Output 14 GPTA0 Output 70 LTCA2 Output 14 Port 0 General Purpose I/O Line 15 GPTA0 Input 15 External Request Input 5 GPTA0 Output 15 GPTA0 Output 71 LTCA2 Output 15 Symbol Data Sheet 57 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 93 P1.2 IN18 OUT18 OUT74 OUT18 98 P1.3 IN19 IN19 OUT19 OUT75 OUT19 107 P1.4 IN20 IN20 EMGSTOP OUT20 OUT76 OUT20 108 P1.5 IN21 IN21 OUT21 OUT77 OUT21 109 P1.6 IN22 IN22 OUT22 OUT78 OUT22 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I I I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I I O1 O2 O3 A1/ PU A1/ PU A1/ PU A1/ PU Type Function A1/ PU Port 1 General Purpose I/O Line 2 GPTA0 Input 18 GPTA0 Output 18 GPTA0 Output 74 LTCA2 Output 18 Port 1 General Purpose I/O Line 3 GPTA0 Input 19 LTCA2 Input 19 GPTA0 Output 19 GPTA0 Output 75 LTCA2 Output 19 Port 1 General Purpose I/O Line 4 GPTA0 Input 20 LTCA2 Input 20 Emergency Stop Input GPTA0 Output 20 GPTA0 Output 76 LTCA2 Output 20 Port 1 General Purpose I/O Line 35 GPTA0 Input 21 LTCA2 Input 21 GPTA0 Output 21 GPTA0 Output 77 LTCA2 Output 21 Port 1 General Purpose I/O Line 6 GPTA0 Input 22 LTCA2 Input 22 GPTA0 Output 22 GPTA0 Output 78 LTCA2 Output 22 Symbol Data Sheet 58 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 110 P1.7 IN23 IN23 OUT23 OUT79 OUT23 94 P1.8 IN24 IN48 MTSR1B OUT24 OUT48 MTSR1B 95 P1.9 IN25 IN49 MRST1B OUT25 OUT49 MRST1B 96 P1.10 IN26 IN50 OUT26 OUT50 SLSO17 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I I O1 O2 O3 I/O0 I I I O1 O2 O3 I/O0 I I I O1 O2 O3 I/O0 I I O1 O2 O3 A2/ PU A2/ PU A2/ PU Type Function A1/ PU Port 1 General Purpose I/O Line 7 GPTA0 Input 23 LTCA2 Input 23 GPTA0 Output 23 GPTA0 Output 79 LTCA2 Output 23 Port 1 General Purpose I/O Line 8 GPTA0 Input 24 GPTA0 Input 48 SSC1 Slave Receive Input B (Slave Mode) GPTA0 Output 24 GPTA0 Output 48 SSC1 Master Transmit Output B (Master Mode) Port 1 General Purpose I/O Line 9 GPTA0 Input 25 GPTA0 Input 49 SSC1 Master Receive Input B (Master Mode) GPTA0 Output 25 GPTA0 Output 49 SSC1 Slave Transmit Output B (Slave Mode) Port 1 General Purpose I/O Line 10 GPTA0 Input 26 GPTA0 Input 50 GPTA0 Output 26 GPTA0 Output 50 SSC1 Slave Select Output 7 Symbol Data Sheet 59 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 97 P1.11 IN27 IN51 SCLK1B OUT27 OUT51 SCLK1B 73 P1.12 IN16 AD0EMUX0 AD0EMUX0 OUT16 72 P1.13 IN17 AD0EMUX1 AD0EMUX1 OUT17 71 P1.14 IN18 AD0EMUX2 AD0EMUX2 OUT18 117 P1.15 BRKIN Reserved Reserved Reserved BRKOUT Port 2 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I I I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 O A2/ PU A1/ PU A1/ PU A1/ PU Type Function A2/ PU Port 1 General Purpose I/O Line 11 GPTA0 Input 27 GPTA0 Input 51 SSC1 Clock Input B GPTA0 Output 27 GPTA0 Output 51 SSC1 Clock Output B Port 1 General Purpose I/O Line 12 LTCA2 Input 16 ADC0 External Multiplexer Control Output 0 ADC0 External Multiplexer Control Output 0 LTCA2 Output 16 Port 1 General Purpose I/O Line 13 LTCA2 Input 17 ADC0 External Multiplexer Control Output 1 ADC0 External Multiplexer Control Output 1 LTCA2 Output 17 Port 1 General Purpose I/O Line 14 LTCA2 Input 18 ADC0 External Multiplexer Control Output 2 ADC0 External Multiplexer Control Output 2 LTCA2 Output 18 Port 1 General Purpose I/O Line 15 Break Input Break Output (controlled by OCDS module) Symbol Data Sheet 60 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 74 P2.0 IN32 OUT32 TCLK0 OUT28 75 P2.1 IN33 TREADY0A OUT33 SLSO03 SLSO13 76 P2.2 IN34 OUT34 TVALID0 OUT29 77 P2.3 IN35 OUT35 TDATA0 OUT30 78 P2.4 IN36 RCLK0A OUT36 OUT36 OUT31 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I I O1 O2 O3 A2/ PU A2/ PU A2/ PU A2/ PU Type Function A2/ PU Port 2 General Purpose I/O Line 0 GPTA0 Input 32 GPTA0 Output 32 MLI0 Transmitter Clock Output 0 LTCA2 Output 28 Port 2 General Purpose I/O Line 1 GPTA0 Input 33 MLI0 Transmitter Ready Input A GPTA0 Output 33 SSC0 Slave Select Output Line 3 SSC1 Slave Select Output Line 3 Port 2 General Purpose I/O Line 2 GPTA0 Input 34 GPTA0 Output 34 MLI0 Transmitter Valid Output LTCA2 Output 29 Port 2 General Purpose I/O Line 3 GPTA0 Input 35 GPTA0 Output 35 MLI0 Transmitter Data Output LTCA2 Output 30 Port 2 General Purpose I/O Line 4 GPTA0 Input 36 MLI Receiver Clock Input A GPTA0 Output 36 GPTA0 Output 36 LTCA2 Output 31 Symbol Data Sheet 61 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 79 P2.5 IN37 OUT37 RREADY0A OUT110 80 P2.6 IN38 RVALID0A OUT38 OUT38 OUT111 81 P2.7 IN39 RDATA0A OUT39 OUT39 Reserved 164 P2.8 SLSO04 SLSO14 EN00 160 P2.9 SLSO05 SLSO15 EN01 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 O1 O2 O3 I/O0 O1 O2 O3 A2/ PU A2/ PU A2/ PU A2/ PU Type Function A2/ PU Port 2 General Purpose I/O Line 5 GPTA0 Input 37 GPTA0 Output 37 MLI0 Receiver Ready Output A LTCA2 Output 110 Port 2 General Purpose I/O Line 6 GPTA0 Input 38 MLI Receiver Valid Input A GPTA0 Output 38 GPTA0 Output 38 LTCA2 Output 111 Port 2 General Purpose I/O Line 7 GPTA0 Input 39 MLI Receiver Data Input A GPTA0 Output 39 GPTA0 Output 39 Port 2 General Purpose I/O Line 8 SSC0 Slave Select Output 4 SSC1 Slave Select Output 4 MSC0 Enable Output 0 Port 2 General Purpose I/O Line 9 SSC0 Slave Select Output 5 SSC1 Slave Select Output 5 MSC0 Enable Output 1 Symbol Data Sheet 62 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 161 P2.10 MRST1A IN10 MRST1A OUT0 Reserved 162 P2.11 SCLK1A IN11 SCLK1A OUT1 FCLP0B 163 P2.12 MTSR1A IN12 MTSR1A OUT2 SOP0B 165 P2.13 SLSI11 SDI0 IN13 OUT3 Reserved Reserved Port 3 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I I I O1 O2 O3 A1/ PU A2/ PU A2/ PU Type Function A2/ PU Port 2 General Purpose I/O Line 10 SSC1 Master Receive Input A LTCA2 Input 10 SSC1 Slave Transmit Output LTCA2 Output 0 Port 2 General Purpose I/O Line 11 SSC1 Clock Input A LTCA2 Input 11 SSC1 Clock Output A LTCA2 Output 1 MSC0 Clock Output Positive B Port 2 General Purpose I/O Line 12 SSC1 Slave Receive Input A LTCA2 Input 12 SSC1 Master Transmit Output A LTCA2 Output 2 MSC0 Serial Data Output Positive B Port 2 General Purpose I/O Line 13 SSC1 Slave Select Input 1 MSC0 Serial Data Input LTCA2 Input 13 LTCA2 Output 3 - Symbol Data Sheet 63 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 136 P3.0 RXD0A RXD0A RXD0A OUT84 135 P3.1 TXD0 TXD0 OUT85 129 P3.2 SCLK0 SCLK0 SCLK0 OUT86 130 P3.3 MRST0 MRST0 MRST0 OUT87 132 P3.4 MTSR0 MTSR0 MTSR0 OUT88 126 P3.5 SLSO00 SLSO10 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I O1 O2 O3 I/O0 O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 O1 O2 A2/ PU A2/ PU A2/ PU A2/ PU A1/ PU Type Function A1/ PU Port 3 General Purpose I/O Line 0 ASC0 Receiver Input A (Async. & Sync. Mode) ASC0 Output (Sync. Mode) ASC0 Output (Sync. Mode) GPTA0 Output 84 Port 3 General Purpose I/O Line 1 ASC0 Output ASC0 Output GPTA0 Output 85 Port 3 General Purpose I/O Line 2 SSC0 Clock Input (Slave Mode) SSC0 Clock Output (Master Mode) SSC0 Clock Input (Master Mode) GPTA0 Output 86 Port 3 General Purpose I/O Line 3 SSC0 Master Receive Input (Master Mode) SSC0 Slave Transmit Output (Slave Mode) SSC0 Slave Transmit Output (Slave Mode) GPTA0 Output 87 Port 3 General Purpose I/O Line 4 SSC0 Slave Receive Input (Slave Mode) SSC0 Master Transmit Output (Master Mode) SSC0 Master Transmit Output (Master Mode) GPTA0 Output 88 Port 3 General Purpose I/O Line 5 SSC0 Slave Select Output 0 SSC1 Slave Select Output 0 SSC0 AND SSC1 Slave Select Output 0 Symbol SLSOANDO0 O3 Data Sheet 64 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 127 P3.6 SLSO01 SLSO11 131 P3.7 SLSI01 SLSO02 SLSO12 OUT89 128 P3.8 SLSO06 TXD1 OUT90 138 P3.9 RXD1A RXD1A RXD1A OUT91 137 P3.10 REQ0 Reserved Reserved OUT92 144 P3.11 REQ1 Reserved Reserved OUT93 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 O1 O2 I/O0 I O1 O2 O3 I/O0 O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 A1/ PU A1/ PU A1/ PU A2/ PU A2/ PU Type Function A2/ PU Port 3 General Purpose I/O Line 6 SSC0 Slave Select Output 1 SSC1 Slave Select Output 1 SSC0 AND SSC1 Slave Select Output 1 Port 3 General Purpose I/O Line 7 SSC0 Slave Select Input 1 SSC0 Slave Select Output 2 SSC1 Slave Select Output 2 GPTA0 Output 89 Port 3 General Purpose I/O Line 8 SSC0 Slave Select Output 6 ASC1 Transmit Output GPTA0 Output 90 Port 3 General Purpose I/O Line 9 ASC1 Receiver Input A ASC1 Receiver Output A (Synchronous Mode) ASC1 Receiver Output A (Synchronous Mode) GPTA0 Output 91 Port 3 General Purpose I/O Line 10 External Request Input 0 GPTA0 Output 92 Port 3 General Purpose I/O Line 11 External Request Input 1 GPTA0 Output 93 Symbol SLSOANDO1 O3 Data Sheet 65 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 143 P3.12 RXDCAN0 RXD0B RXD0B RXD0B OUT94 142 P3.13 TXDCAN0 TXD0 OUT95 134 P3.14 RXDCAN1 RXD1B RXD1B RXD1B OUT96 133 P3.15 TXDCAN1 TXD1 OUT97 Port 4 86 P4.0 IN28 IN52 OUT28 OUT52 Reserved I/O0 I I O1 O2 O3 A1/ PU Port 4 General Purpose I/O Line 0 GPTA0 Input 28 GPTA0 Input 52 GPTA0 Output 28 GPTA0 Output 52 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I I O1 O2 O3 I/O0 O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 O1 O2 O3 A2/ PU A1/ PU A2/ PU Type Function A1/ PU Port 3 General Purpose I/O Line 12 CAN Node 0 Receiver Input ASC0 Receiver Input B ASC0 Receiver Output B (Synchronous Mode) ASC0 Receiver Output B (Synchronous Mode) GPTA0 Output 94 Port 3 General Purpose I/O Line 13 CAN Node 0 Transmitter Output ASC0 Transmit Output GPTA0 Output 95 Port 3 General Purpose I/O Line 14 CAN Node 1 Receiver Input ASC1 Receiver Input B ASC1 Receiver Output B (Synchronous Mode) ASC1 Receiver Output B (Synchronous Mode) GPTA0 Output 96 Port 3 General Purpose I/O Line 15 CAN Node 1 Transmitter Output ASC1 Transmit Output GPTA0 Output 97 Symbol Data Sheet 66 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 87 P4.1 IN29 IN53 OUT29 OUT53 Reserved 88 P4.2 IN30 IN54 OUT30 OUT54 EXTCLK1 90 P4.3 IN31 IN55 OUT31 OUT55 EXTCLK0 Port 5 1 P5.0 IN40 IN26 OUT40 OUT8 Reserved I/O0 I I O1 O2 O3 A1/ PU Port 5 General Purpose I/O Line 0 GPTA0 Input 40 LTCA2 Input 26 GPTA0 Output 40 LTCA2 Output 8 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I I O1 O2 O3 A2/ PU A2/ PU Type Function A1/ PU Port 4 General Purpose I/O Line 1 GPTA0 Input 29 GPTA0 Input 53 GPTA0 Output 29 GPTA0 Output 53 Port 4 General Purpose I/O Line 2 GPTA0 Input 30 GPTA0 Input 54 GPTA0 Output 30 GPTA0 Output 54 External Clock 1 Output Port 4 General Purpose I/O Line 3 GPTA0 Input 31 GPTA0 Input 55 GPTA0 Output 31 GPTA0 Output 55 External Clock 0 Output Symbol Data Sheet 67 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 2 P5.1 IN41 IN27 OUT41 OUT9 Reserved 3 P5.2 IN42 IN28 OUT42 OUT10 Reserved 4 P5.3 IN43 OUT43 OUT11 Reserved 5 P5.4 IN44 IN29 OUT44 OUT12 Reserved 6 P5.5 IN45 IN30 OUT45 OUT13 Reserved Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I I O1 O2 O3 I/O0 I I O1 O2 O3 A1/ PU A1/ PU A1/ PU A1/ PU Type Function A1/ PU Port 5 General Purpose I/O Line 1 GPTA0 Input 41 LTCA2 Input 27 GPTA0 Output 41 LTCA2 Output 9 Port 5 General Purpose I/O Line 2 GPTA0 Input 42 LTCA2 Input 28 GPTA0 Output 42 LTCA2 Output 10 Port 5 General Purpose I/O Line 3 GPTA0 Input 43 GPTA0 Output 43 LTCA2 Output 11 Port 5 General Purpose I/O Line 4 GPTA0 Input 44 LTCA2 Input 29 GPTA0 Output 44 LTCA2 Output 12 Port 5 General Purpose I/O Line 5 GPTA0 Input 45 LTCA2 Input 30 GPTA0 Output 45 LTCA2 Output 13 - Symbol Data Sheet 68 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 7 P5.6 IN46 IN31 OUT46 OUT14 Reserved 8 P5.7 IN47 OUT47 OUT15 Reserved 13 P5.8 RDATA0B Reserved Reserved OUT89 14 P5.9 RVALID0B Reserved Reserved OUT90 15 P5.10 RREADY0B Reserved OUT91 16 P5.11 RCLK0B Reserved Reserved OUT92 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 I/O0 O1 O2 O3 I/O0 I O1 O2 O3 A2/ PU A2/ PU A2/ PU A2/ PU A1/ PU Type Function A1/ PU Port 5 General Purpose I/O Line 6 GPTA0 Input 46 LTCA2 Input 31 GPTA0 Output 46 LTCA2 Output 14 Port 5 General Purpose I/O Line 7 GPTA0 Input 47 GPTA0 Output 47 LTCA2 Output 15 Port 5 General Purpose I/O Line 8 MLI0 Receiver Data Input B LTCA2 Output 89 Port 5 General Purpose I/O Line 9 MLI0 Receiver Data Valid Input B LTCA2 Output 90 Port 5 General Purpose I/O Line 10 MLI0 Receiver Ready Input B LTCA2 Output 91 Port 5 General Purpose I/O Line 11 MLI0 Receiver Clock Input B LTCA2 Output 92 Symbol Data Sheet 69 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 17 P5.12 TDATA0 SLSO07 OUT93 18 P5.13 TVALID0B SLSO16 Reserved 19 P5.14 TREADY0B Reserved Reserved OUT94 9 P5.15 TCLK0 Reserved OUT95 Port 6 156 P6.0 IN14 FCLN0 OUT80 OUT4 157 P6.1 IN15 FCLP0A OUT81 OUT5 I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 A1/ F/ PU A1/ F/ PU Port 6 General Purpose I/O Line 0 LTCA2 Input 14 MSC0 Clock Output Negative GPTA0 Output 80 LTCA2 Output 4 Port 6 General Purpose I/O Line 1 LTCA2 Input 15 MSC0 Clock Output Positive A GPTA0 Output 81 LTCA2 Output 5 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 O1 O2 O3 I/O0 O1 O2 O3 I/O0 I O1 O2 O3 I/O0 O1 O2 O3 A2/ PU A2/ PU A2/ PU Type Function A2/ PU Port 5 General Purpose I/O Line 12 MLI0 Transmitter Data Output SSC0 Slave Select Output 7 LTCA2 Output 93 Port 5 General Purpose I/O Line 13 MLI0 Transmitter Valid Input B SSC1 Slave Select Output 6 Port 5 General Purpose I/O Line 14 MLI0 Transmitter Ready Input B LTCA2 Output 94 Port 5 General Purpose I/O Line 15 MLI0 Transmitter Clock Output LTCA2 Output 95 Symbol Data Sheet 70 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 158 P6.2 IN24 SON0 OUT82 OUT6 159 P6.3 IN25 SOP0A OUT83 OUT7 Analog Input Port 67 66 65 64 63 62 61 36 60 59 58 57 56 55 50 49 48 47 46 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 I I I I I I I I I I I I I I I I I I I D D D D D D D D D D D D D D D D D D D Analog Input 0 Analog Input 1 Analog Input 2 Analog Input 3 Analog Input 4 Analog Input 5 Analog Input 6 Analog Input 7 Analog Input 8 Analog Input 9 Analog Input 10 Analog Input 11 Analog Input 12 Analog Input 13 Analog Input 14 Analog Input 15 Analog Input 16 Analog Input 17 Analog Input 18 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I/O0 I O1 O2 O3 I/O0 I O1 O2 O3 A1/ F/ PU Type Function A1/ F/ PU Port 6 General Purpose I/O Line 2 LTCA2 Input 24 MSC0 Serial Data Output Negative GPTA0 Output 82 LTCA2 Output 6 Port 6 General Purpose I/O Line 3 LTCA2 Input 25 MSC0 Serial Data Output Positive A GPTA0 Output 83 LTCA2 Output 7 Symbol Data Sheet 71 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 45 44 43 42 41 40 39 38 37 35 34 33 32 31 30 29 28 54 53 52, 51 24 23 25, 26 27 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I I I I I I I I I I I I I I I I I Type Function D D D D D D D D D D D D D D D D D Analog Input 19 Analog Input 20 Analog Input 21 Analog Input 22 Analog Input 23 Analog Input 24 Analog Input 25 Analog Input 26 Analog Input 27 Analog Input 28 Analog Input 29 Analog Input 30 Analog Input 31 Analog Input 32 Analog Input 33 Analog Input 34 Analog Input 35 ADC Analog Part Power Supply (3.3V - 5V) ADC Analog Part Ground ADC0 Reference Voltage ADC1 Reference Voltage ADC Reference Ground FADC Analog Part Power Supply (3.3V)2) FADC Analog Part Logic Power Supply (1.5V) FADC Analog Part Ground FADC Analog Part Ground FADC Reference Voltage FADC Reference Ground Symbol VDDM VSSM VAREF0 VAREF1 VAGND0 VDDMF VDDAF VSSMF VSSAF VFAREF VFAGND Data Sheet 72 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 10, VDD 213), 68, 84, 89, 99, 123, 153, 170 11, VDDP 20, 69, 83, 91, 100, 124, 139, 154, 171 12, VSS 22, 70, 82, 85, 92, 101, 125, 140, 155, 172 105 106 104 141 102 103 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. Type Function Digital Core Power Supply (1.5V) Symbol - - Port Power Supply (3.3V) - - Digital Ground VDDOSC VDDOSC3 VSSOSC VDDFL3 XTAL1 XTAL2 I O - Main Oscillator and PLL Power Supply (1.5V) Main Oscillator Power Supply (3.3V) Main Oscillator and PLL Ground Power Supply for Flash (3.3V) Main Oscillator Input Main Oscillator Output Data Sheet 73 V1.3, 2009-09 TC1767 Pinning Table 4 Pin 111 TDI BRKIN BRKOUT 112 113 TMS DAP1 TDO DAP2 BRKIN BRKOUT 114 115 118 120 121 122 TRST TCK DAP0 TESTMODE ESR1 PORST ESR0 Pin Definitions and Functions (PG-LQFP-176-5 Package1)) (cont’d) Ctrl. I I O I I/O I/O I/O I O I I I I I/O I I/O A1/ PD A1/ PD PU A2/ PD PD A2 A2/ PD A2/ PU Type Function A2/ PU JTAG Serial Data Input OCDS Break Input Line OCDS Break Output Line JTAG State Machine Control Input Device Access Port Line 1 JTAG Serial Data Output Device Access Port Line 2 OCDS Break Input Line OCDS Break Output Line JTAG Reset Input JTAG Clock Input Device Access Port Line 0 Test Mode Select Input External System Request Reset Input 1 Power On Reset Input (input pad with input spike-filter) External System Request Reset Input 0 Default configuration during and after reset is open-drain driver, corresponding to A2 strong driver, sharp edge. The driver drives low during power-on reset. Symbol 1) TC1767 ED: PG-LQFP-176-6 2) This pin is also connected to the analog power supply for comparator of the ADC module. 3) For the TC1767 emulation device (ED), this pin is bonded to VDDSB (ED Stand By RAM supply). In the TC1767 non ED device, this pin is bonded to a VDD pad. Legend for Table 4 Column “Ctrl.”: I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB) O = Output O0 = Output with IOCR bit field selection PCx = 1X00B O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1) Data Sheet 74 V1.3, 2009-09 TC1767 Pinning O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2) O3 = Output with IOCR bit field selection PCx = 1X11(ALT3) Column “Type”: A1 = Pad class A1 (LVTTL) A2 = Pad class A2 (LVTTL) F = Pad class F (LVDS/CMOS) D = Pad class D (ADC) PU = with pull-up device connected during reset (PORST = 0) PD = with pull-down device connected during reset (PORST = 0) TR = tri-state during reset (PORST = 0) 3.1.2 Reset Behavior of the Pins Table 5 describes the pull-up/pull-down behavior of the System I/O pins during poweron reset. Table 5 Pins All GPIOs, TDI, TESTMODE PORST, TRST, TCK, TMS ESR0 ESR1 TDO List of Pull-up/Pull-down PORST Reset Behavior of the Pins PORST = 0 Pull-up Pull-down The open-drain driver is Pull-up2) used to drive low.1) Pull-down3) Pull-up High-impedance PORST = 1 1) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details. 2) See the SCU_IOCR register description. 3) see the SCU_IOCR register description. Data Sheet 75 V1.3, 2009-09 TC1767 Identification Registers 4 Identification Registers The Identification Registers uniquely identify a module or the whole device. Table 6 Short Name ADC0_ID ADC1_ID ASC0_ID ASC1_ID CAN_ID CBS_JDPID CBS_JTAGID CPS_ID CPU_ID DMA_ID DMI_ID FADC_ID FLASH0_ID FPU_ID GPTA0_ID LBCU_ID LFI_ID LTCA2_ID MCHK_ID MLI0_ID MSC0_ID PCP_ID PMI_ID PMU0_ID SBCU_ID SCU_CHIPID SCU_ID TC1767 Identification Registers Value 0058 C000H 0058 C000H 0000 4402H 0000 4402H 002B C061H 0000 6350H 1015 9083H 0015 C007H 000A C006H 001A C004H 0008 C005H 0027 C003H 0053 C001H 0054 C003H 0029 C005H 000F C005H 000C C006H 002A C005H 001B C001H 0025 C007H 0028 C003H 0020 C006H 000B C005H 0050 C001H 0000 6A0CH 0000 9001H 0052 C001H Address F010 1008H F010 1408H F000 0A08H F000 0B08H F000 4008H F000 0408H F000 0464H F7E0 FF08H F7E1 FE18H F000 3C08H F87F FC08H F010 0408H F800 2008H F7E1 A020H F000 1808H F87F FE08H F87F FF08H F000 2808H F010 C208H F010 C008H F000 0808H F004 3F08H F87F FD08H F800 0508H F000 0108H F000 0640H F000 0508H Stepping – – – – – – – – – – – – – – – – – – – – – – – – – – – Data Sheet 76 V1.3, 2009-09 TC1767 Identification Registers Table 6 Short Name SCU_MANID SCU_RTID SSC0_ID SSC1_ID STM_ID TC1767 Identification Registers (cont’d) Value 0000 1820H 0000 0007H 0000 4511H 0000 4511H 0000 C006H Address F000 0644H F000 0648H F010 0108H F010 0208H F000 0208H Stepping – AD-step – – – Data Sheet 77 V1.3, 2009-09 TC1767 Electrical Parameters 5 5.1 5.1.1 Electrical Parameters General Parameters Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1767 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”: • CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1767 and must be regarded for a system design. SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1767 designed in. • Data Sheet 78 V1.3, 2009-09 TC1767 Electrical Parameters 5.1.2 Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1. Table 7 Pad Driver and Pad Classes Overview Sub Class A1 (e.g. GPIO) A2 (e.g. serial I/Os) – Speed Load Grade 6 MHz 40 MHz 50 MHz – Leakage1) Termination No Series termination recommended Parallel termination2), 100 Ω ± 10% see Table 12 Class Power Type Supply A 3.3 V LVTTL I/O, LVTTL outputs LVDS/ CMOS ADC 100 pF 500 nA 50 pF 6 µA F 3.3 V – – DE 5V – – – 1) Values are for TJmax = 150 °C. 2) In applications where the LVDSpins are not used (disabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 Ω ± 10%. Data Sheet 79 V1.3, 2009-09 TC1767 Electrical Parameters 5.1.3 Absolute Maximum Ratings Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > related VDD or VIN < VSS) the voltage on the related VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Table 8 Parameter Absolute Maximum Rating Parameters Symbol Values Min. Typ. Max. Unit Note / Test Con dition °C °C °C V V V V Under bias – Under bias – – – Whatever is lower – TA Storage temperature TST TJ Junction temperature Voltage at 1.5 V power supply VDD pins with respect to VSS1) Voltage at 3.3 V power supply VDDP pins with respect to VSS2) Voltage at 5 V power supply VDDM pins with respect to VSS Voltage on any Class A input VIN Ambient temperature pin and dedicated input pins with respect to VSS Voltage on any Class D analog input pin with respect to VAGND Voltage on any Class D analog input pin with respect to VSSAF, if the FADC is switched through to the pin. SR -40 SR -65 SR -40 – SR SR – SR – – – – – – – 125 150 150 2.25 3.75 5.5 SR -0.5 – VDDP + 0.5 or max. 3.7 VAIN VAREFx SR -0.5 – VDDM + 0.5 V VAINF VFAREF SR -0.5 – VDDM + 0.5 V – 1) Applicable for VDD, VDDOSC, VDDPLL, and VDDAF. 2) Applicable for VDDP, VDDFL3, and VDDMF. Data Sheet 80 V1.3, 2009-09 TC1767 Electrical Parameters 5.1.4 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1767. All parameters specified in the following table refer to these operating conditions, unless otherwise noted. Table 9 Parameter Digital supply voltage1) Operating Condition Parameters Symbol Min. 1.42 3.13 3.13 3.13 1.42 4.75 Values Typ. Max. – – – – – – – -40 – 1.582) 3.473) 3.473) 3.473) 1.58 5.25 – +125 – 2) Unit Note / Test Condition V V V V V V V °C – – For Class A pins (3.3 V ± 5%) – FADC FADC For Class DE pins, ADC – – See separate specification Page 88, Page 93 4) VDD SR VDDOSC SR VDDP SR VDDOSC3 SR VDDFL3 SR Analog supply voltages VDDMF SR VDDAF SR VDDM SR Digital ground voltage Ambient temperature under bias VSS TA SR 0 SR – – Analog supply voltages – Overload current at class D pins IOV -1 – – – SR SR SR – – – – – – – – – – – 81 3 10 5×10-5 5×10-4 133 80 133 80 80 +5 mA mA Sum of overload current Σ|IOV| at class D pins Overload coupling KOVAP 5) factor for analog inputs K CPU & LMB Bus Frequency PCP Frequency FPI Bus Frequency Short circuit current Data Sheet per single ADC 0 < IOV < 3 mA -1 mA < IOV < 0 OVAN fCPU fPCP fSYS ISC MHz Derivative dependent MHz MHz mA Derivative dependent 6) 7) 6) SR -5 V1.3, 2009-09 TC1767 Electrical Parameters Table 9 Parameter Absolute sum of short circuit currents of a pin group (see Table 10) Inactive device pin current Absolute sum of short circuit currents of the device External load capacitance Operating Condition Parameters Symbol Min. Σ|ISC_PG| SR – Values Typ. Max. – 20 Unit Note / Test Condition mA See note IID Σ|ISC_D| SR -1 – SR – – 1 100 mA mA All power supply voltages VDDx = 0 See note4) CL SR – – – pF Depending on pin class. See DC characteristics 1) Digital supply voltages applied to the TC1767 must be static regulated voltages which allow a typical voltage swing of ±5%. 2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 µs and the cumulated summary of the pulses does not exceed 1 h. 3) Voltage overshoot up to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 µs and the cumulated summary of the pulses does not exceed 1 h. 4) See additional document “TC1767 Pin Reliability in Overload“ for definition of overload current on digital pins. 5) The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to the resulting leakage current (IleakTOT) into an adjacent pin: IleakTOT = ±kA × |IOV| + IOZ1. Thus under overload conditions an additional error leakage voltage (VAEL) will be induced onto an adjacent analog input pin due to the resistance of the analog input source (RAIN). That means VAEL = RAIN × |IleakTOT|. The definition of adjacent pins is related to their order on the silicon. The Injected leakage current always flows in the opposite direction from the causing overload current. Therefore, the total leakage current must be calculated as an algebraic sum of the both component leakage currents (the own leakage current IOZ1 and the optional injected leakage current). 6) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters. 7) Applicable for digital outputs. Table 10 Group 1 2 3 4 Data Sheet Pin Groups for Overload/Short-Circuit Current Sum Parameter Pins P5.[14:8] P1.[14:12]; P2.[7:0] P4.[3:0] P1.[3:2]; P1.[11:8] 82 V1.3, 2009-09 TC1767 Electrical Parameters Table 10 Group 5 6 7 8 9 Pin Groups for Overload/Short-Circuit Current Sum Parameter Pins P1.[7:4]; TDI/BRKIN/BRKOUT; TRST, TCK/DAP0; P1.[1:0]; P1.15; TESTMODE; ESR0; PORST; ESR1 P3.[10:0]; P3.[15:14] P3.[13:11]; P0.[3:0]; P0.[11:8] P6.[3:0]; P2.[13:8]; P0.[5:4]; P0.[13:12] P0.[7:6]; P0.[15:14]; P5.[7:0]; P5.15 Data Sheet 83 V1.3, 2009-09 TC1767 Electrical Parameters 5.2 5.2.1 Table 11 Parameter DC Parameters Input/Output Pins Input/Output DC-Characteristics (Operating Conditions apply) Symbol Min. Values Typ. Max. – – – 100 150 10 µA µA pF Unit Note / Test Condition General Parameters Pull-up current1) Pull-down current1) Pin capacitance (Digital I/O) 1) |IPUH| CC |IPDL| CC 10 10 – CC VIN < VIHAmin; class A1/A2/F/Input pads. VIN >VILAmax; class A1/A2/F/Input pads. CIO f = 1 MHz TA = 25 °C – Whatever is lower Input only Pads (VDDP = 3.13 to 3.47 V = 3.3 V ± 5%) Input low voltage VILI SR -0.3 0.62 × SR VDDP – – 0.36 × V V Input high voltage VIHI VDDP VDDP+ 0.3 or max. 3.6 Ratio VIL/VIH CC 0.58 – – – – V – Whatever is lower Input high voltage VIHJ 0.64 × TRST, TCK SR VDDP VDDP+ 0.3 or max. 3.6 Input hysteresis Input leakage current2) HYSI 0.1 × CC VDDP – CC – – – ±3000 ±6000 10 V nA 4) IOZI ((VDDP/2)-1) < VIN < ((VDDP/2)+1) Otherwise Spike filter always tSF1 – blocked pulse CC duration – ns Data Sheet 84 V1.3, 2009-09 TC1767 Electrical Parameters Table 11 Parameter Spike filter passthrough pulse duration Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Symbol Min. Values Typ. Max. – – ns 100 CC Unit Note / Test Condition tSF2 Class A Pads (VDDP = 3.13 to 3.47 V = 3.3V ± 5%) Output low voltage VOLA 2)3) – CC – 0.4 V IOL = 2 mA for medium and strong driver mode, IOL = 500 µA for weak driver mode Output high voltage2) 3) VOHA CC 2.4 – – V IOH = -2 mA for medium and strong driver mode, IOH = -500 µA for weak driver mode VDDP - – 0.4 – V IOH = -1.4 mA for medium and strong driver mode, IOH = -400 µA for weak driver mode Input low voltage Class A1/2 pins VILA SR -0.3 – – 0.36 × V V – Whatever is lower Input high voltage VIHA1 0.62 × Class A1 pins SR VDDP VDDP VDDP+ 0.3 or max. 3.6 Ratio VIL/VIH SR 0.58 – – – – V – Whatever is lower Input high voltage VIHA2 0.60 × Class A2 pins SR VDDP VDDP+ 0.3 or max. 3.6 – – ±3000 ±6000 Ratio VIL/VIH Input hysteresis Input leakage current Class A2 pins CC 0.60 HYSA 0.1 × CC VDDP – – – – V nA – 4) IOZA2 – ((VDDP/2)-1) < VIN < ((VDDP/2)+1) Otherwise2) Data Sheet 85 V1.3, 2009-09 TC1767 Electrical Parameters Table 11 Parameter Input leakage current Class A1 pins Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Symbol Min. Values Typ. Max. – ±500 nA 0 V VDD1.5 - 0.5 V;VDD3.3 > VDD1.5 - 0.5 V, see Figure 24. 2. During power-up and power-down, the voltage difference between the power supply pins of the same voltage (3.3 V, 1.5 V, and 5 V) with different names (for example VDDP, VDDFL3 ...), that are internaly connected via diodes must be lower than 100 mV. On the other hand, all power supply pins with the same name (for example all VDDP ), are internaly directly connected. It is recommended that the power pins of the same voltage are driven by a single power supply. 102 V1.3, 2009-09 Data Sheet TC1767 Electrical Parameters 3. The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.5, and VAREF powersupplies and the oscillator have reached stable operation, within the normal operating conditions. 4. At normal power down the PORST signal should be activated within the normal operating range, and then the power supplies may be switched off. Care must be taken that all Flash write or delete sequences have been completed. 5. At power fail the PORST signal must be activated at latest when any 3.3 V or 1.5 V power supply voltage falls 12% below the nominal level. The same limit of 3.3 V-12% applies to the 5 V power supply too. If, under these conditions, the PORST is activated during a Flash write, only the memory row that was the target of the write at the moment of the power loss will contain unreliable content. In order to ensure clean power-down behavior, the PORST signal should be activated as close as possible to the normal operating voltage range. 6. In case of a power-loss at any power-supply, all power supplies must be powereddown, conforming at the same time to the rules number 2 and 4. 7. Although not necessary, it is additionally recommended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible. 8. Aditionally, regarding the ADC reference voltage VAREF: – VAREF must power-up at the same time or later than VDDM, and – VAREF must power-down eather earlier or at latest to satisfy the condition VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF filter capacitance through the ESD diodes through the VDDM power supply. In case of discharging the reference capacitance through the ESD diodes, the current must be lower than 5 mA. Data Sheet 103 V1.3, 2009-09 TC1767 Electrical Parameters 5.3.4 Table 19 Parameter Power, Pad and Reset Timing Power, Pad and Reset Timing Parameters Symbol Min. Values Typ. – Max. – Unit Note / Test Conditi on V – Min. VDDP voltage to ensure defined pad states1) Oscillator start-up time2) Minimum PORST active time after power supplies are stable at operating levels ESR0 pulse width PORST rise time Setup time to PORST rising edge4) Hold time from PORST rising edge VDDPPA CC 0.6 tOSCS tPOA CC – SR 10 – – 10 – ms ms – – tHD tPOR tPOS tPOH CC program – mable3)5) SR – SR 0 SR 100 SR 0 SR 16 × 1/fSYS5) CC – CC – – – – – – – – – 50 – – – – 150 fSYS ms ns ns ns ns ns – – – TESTMODE TRST – HWCFG – – Setup time to ESR0 rising tHDS edge Hold time from ESR0 rising edge Ports inactive after PORST reset active6)7) Ports inactive after ESR0 reset active (and for all logic) Power on Reset Boot Time8) Application Reset Boot Time 9)10) tHDH tPIP tPI 8× ns 1/fSYS 2.5 700 960 ms µs µs tBP tB CC – CC 150 – – – fCPU=133MHz fCPU=80MHz 1) This parameter is valid under assumption that PORST signal is constantly at low level during the powerup/power-down of the VDDP. Data Sheet 104 V1.3, 2009-09 TC1767 Electrical Parameters 2) tOSCS is defined from the moment when VDDOSC3 = 3.13 V until the oscillations reach an amplitude at XTAL1 of 0,3 × VDDOSC3. This parameter is verified by device characterization. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystal suppliers. 3) Any ESR0 activation is internally prolonged to SCU_RSTCNTCON.RELSA FPI bus clock (fFPI) cycles. 4) Applicable for input pins TESTMODE and TRST. 5) fFPI = fCPU / 2 6) Not subject to production test, verified by design / characterization. 7) This parameter includes the delay of the analog spike filter in the PORST pad. 8) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first user instruction has entered the CPU and its processing starts. 9) The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts. 10) The given time includes the time of the internal reset extension for a configured value of SCU_RSTCNTCON.RELSA = 0x05BE. V D D PPA VDDP VD D P -12% V D D PPA VDD tPOA tPOA PORST TRST TESTMODE t hd ESR0 tHDH HWCFG t PIP Pads tPI Pad-state undefined Tri-state or pull device active As programmed t PIP tPI tPI tPI t PIP tPI tHDH tHDH tPOH t hd tPOH VD D -12% reset_beh2 Figure 25 Power, Pad and Reset Timing Data Sheet 105 V1.3, 2009-09 TC1767 Electrical Parameters 5.3.5 Phase Locked Loop (PLL) Note: All PLL characteristics defined on this and the next page are not subject to production test, but verified by design characterization. Table 20 Parameter PLL Parameters (Operating Conditions apply) Symbol Min. Accumulated jitter Values Typ. – – – 200 – Max. 7 800 16 320 200 Unit Note / Test Con dition ns – MHz – MHz – MHz – µs – |Dm| VCO frequency range fVCO VCO input frequency range fREF fPLLBASE PLL base frequency1) PLL lock-in time tL – 400 8 50 – 1) The CPU base frequency with which the application software starts after PORST is calculated by dividing the limit values by 16 (this is the K2 factor after reset). Phase Locked Loop Operation When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMBBus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly adjusting its output frequency to correspond to the input frequency (from crystal or clock source), resulting in an accumulated jitter that is limited. This means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle. This is especially important for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in [ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the number m of consecutive fLMB clock periods. for ( K2 ≤ 100 ) and ( m ≤ ( f LMB [ MHz ] ) ⁄ 2 ) (2) ( 1 – 0, 01 × K2 ) × ( m – 1 ) 740 D m [ ns ] =  -------------------------------------------- + 5 ×  ---------------------------------------------------------------- + 0, 01 × K2  K2 × f   0, 5 × f  LMB [ MHz ] LMB [ MHz ] – 1 else 740 D m [ ns ] = -------------------------------------------- + 5 K2 × f LMB [ MHz ] (3) Data Sheet 106 V1.3, 2009-09 TC1767 Electrical Parameters With rising number m of clock cycles the maximum jitter increases linearly up to a value of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock frequency fLMB results in a higher absolute maximum jitter value. Figure 26 gives the jitter curves for several K2 / fLMB combinations. ±10.0 Dm ns ±8.0 ±7.0 ±6.0 fLMB = 40 MHz (K2 = 10) fLMB = 40 MHz (K2 = 20) ±4.0 fLMB = 80 MHz (K2 = 6) fLMB = 80 MHz (K2 = 10) ±2.0 ±1.0 fLMB = 133 MHz (K2 = 6) 0 20 40 60 80 100 120 oo ±0.0 Dm = Max. jitter m = Number of consecutive fLMB periods K2 = K2-divider of PLL m TC1767_PLL_JITT_C Figure 26 Approximated Maximum Accumulated PLL Jitter for Typical LMBBus Clock Frequencies fLMB Note: The specified PLL jitter values are valid if the capacitive load per output pin does not exceed CL = 20 pF with the maximum driver and sharp edge. In case of applications with many pins with high loads, driver strengths and toggle rates the specified jitter values could be exceeded. Note: The maximum peak-to-peak noise on the pad supply voltage, measured between VDDOSC3 at pin 106 and VSSOSC at pin 104, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. The maximum peak-to peak noise on the pad supply votage, measured between VDDOSC at pin 105 and VSSOSC at pin 104, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. Data Sheet 107 V1.3, 2009-09 TC1767 Electrical Parameters These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Data Sheet 108 V1.3, 2009-09 TC1767 Electrical Parameters 5.3.6 JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 21 Parameter TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time TDI/TMS setup to TCK rising edge TDI/TMS hold after TCK rising edge JTAG Interface Timing Parameters (Operating Conditions apply) Symbol Min. Values Typ. – – – – – – – – – – – – Max. – – – 4 4 – – 13 3 – 14 13.5 25 12 10 – – 6 6 – – 2 – – Unit Note / Test Condition ns ns ns ns ns ns ns ns ns ns ns ns CL = 50 pF CL = 50 pF – – – – – – – CL = 50 pF CL = 20 pF t1 SR t2 SR t3 SR t4 SR t5 SR t6 SR t7 SR TDO valid after TCK falling t8 CC edge1) (propagation delay) t CC 8 TDO hold after TCK falling t18 CC edge1) TDO high imped. to valid from TCK falling edge1)2) TDO valid to high imped. from TCK falling edge1) t9 CC t10 CC 1) The falling edge on TCK is used to generate the TDO timing. 2) The setup time for TDO is given implicitly by the TCK cycle time. Data Sheet 109 V1.3, 2009-09 TC1767 Electrical Parameters t1 0.9 VD D P 0.5 VD D P t5 t2 t3 t4 0.1 VD D P MC_ JTAG_ TCK Figure 27 Test Clock Timing (TCK) TCK t6 TMS t7 t6 TDI t7 t9 TDO t8 t1 0 t18 MC_JTAG Figure 28 JTAG Timing Data Sheet 110 V1.3, 2009-09 TC1767 Electrical Parameters 5.3.7 DAP Interface Timing The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 22 Parameter DAP0 clock period DAP0 high time DAP0 low time DAP0 clock rise time DAP0 clock fall time DAP1 setup to DAP0 rising edge DAP1 hold after DAP0 rising edge DAP1 valid per DAP0 clock period1) DAP Interface Timing Parameters (Operating Conditions apply) Symbol Min. Values Typ. – – – – – – – – – Max. – – – 2 2 – – – – 12.5 4 4 – – 6 6 8 10 Unit Note / Test Condition ns ns ns ns ns ns ns ns ns – – – – – – – 80 MHz, CL = 20 pF 40 MHz, CL = 50 pF t11 SR t12 SR t13 SR t14 SR t15 SR t16 SR t17 SR t19 SR t19 SR 1) The Host has to find a suitable sampling point by analyzing the sync telegram response. t11 0.9 VD D P 0.5 VD D P t1 5 t1 2 t1 3 t14 0.1 VD D P MC_DAP0 Figure 29 Test Clock Timing (DAP0) Data Sheet 111 V1.3, 2009-09 TC1767 Electrical Parameters DAP0 t1 6 DAP1 t1 7 MC_ DAP1_RX Figure 30 DAP Timing Host to Device t1 1 DAP1 t1 9 MC_ DAP1_TX Figure 31 DAP Timing Device to Host Data Sheet 112 V1.3, 2009-09 TC1767 Electrical Parameters 5.3.8 Peripheral Timings Note: Peripheral timing parameters are not subject to production test. They are verified by design / characterization. 5.3.8.1 Micro Link Interface (MLI) Timing MLI Transmitter Timing t13 t10 t12 TCLKx t14 t11 t15 t15 TDATAx TVALIDx t16 TREADYx t17 MLI Receiver Timing t23 t20 t22 RCLKx t24 t21 t25 t26 RDATAx RVALIDx t27 RREADYx t27 MLI_Tmg_2.vsd Figure 32 MLI Interface Timing Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. Data Sheet 113 V1.3, 2009-09 TC1767 Electrical Parameters Table 23 Parameter MLI Transmitter/Receiver Timing (Operating Conditions apply), CL = 50 pF Symbol Min. MLI Transmitter Timing TCLK clock period TCLK high time TCLK low time TCLK rise time TCLK fall time TDATA/TVALID output delay time TREADY setup time to TCLK rising edge TREADY hold time from TCLK rising edge MLI Receiver Timing RCLK clock period RCLK high time RCLK low time RCLK rise time RCLK fall time RDATA/RVALID setup time to RCLK falling edge Values Typ. Max. Unit Note / Test Co ndition ns 1) 2)3) 2)3) t10 t11 t12 t13 t14 t15 t16 t17 CC 2 × TMLI CC – – 0.45 × t10 0.5 × t10 0.55 × t10 ns – – – – – 4) 4) CC 0.45 × t10 0.5 × t10 0.55 × t10 ns CC – CC – CC -3 SR 18 SR 0 ns ns ns ns ns – – – – – 4.4 – – t20 t21 t22 t23 t24 t25 SR 1 × TMLI SR – SR – SR – SR – SR 4.2 SR 2.2 CC 0 – – ns ns ns ns ns ns ns ns 1) 5)6) 5)6) 7) 7) 0.5 × t20 – 0.5 × t20 – – – – – – 4 4 – – 16 – – – RDATA/RVALID hold time t26 from RCLK rising edge RREADY output delay time t27 1) TMLImin. = TSYS = 1/fSYS. When fSYS = 80 MHz, t10 = 25 ns and t20 = 12.5 ns. 2) The following formula is valid: t11 + t12 = t10 3) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be regarded additionally to t11/t12. 4) For high-speed MLI interface, strong driver sharp edge selection (class A2 pad) is recommended for TCLK. 5) The following formula is valid: t21 + t22 = t20 6) The min. and max. value of is parameter can be adjusted by considering the other receiver timing parameters. Data Sheet 114 V1.3, 2009-09 TC1767 Electrical Parameters 7) The RCLK max. input rise/fall times are best case parameters for fSYS = 80 MHz. For reduction of EMI, slower input signal rise/fall times can be used for longer RCLK clock periods. 5.3.8.2 Table 24 Parameter Micro Second Channel (MSC) Interface Timing MSC Interface Timing (Operating Conditions apply), CL = 50 pF Symbol Min. Values Typ. Max. – 10 – 100 100 ns ns ns ns ns Unit Note / Test Con dition – – – – – FCLP clock period1)2) SOP/ENx outputs delay from FCLP rising edge SDI bit time SDI rise time SDI fall time t40 t45 t46 t48 t49 CC 2 × TMSC3) – CC -10 CC 8 × TMSC SR SR 1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times. 2) FCLP signal high and low can be minimum 1 × TMSC. 3) TMSCmin = TSYS = 1/fSYS. When fSYS = 80 MHz, t40 = 25 ns t40 FCLP 0.9 VDDP 0.1 VDDP t45 SOP EN t45 t48 SDI t49 0.9 VDDP 0.1 VDDP t46 Figure 33 MSC Interface Timing t46 MSC_Tmg_1.vsd Note: Sample the data at SOP with the falling edge of FCLP in the target device. Data Sheet 115 V1.3, 2009-09 TC1767 Electrical Parameters 5.3.8.3 Table 25 Parameter SSC Master / Slave Mode Timing SSC Master/Slave Mode Timing (Operating Conditions apply), CL = 50 pF Symbol Min. Values Typ. Max. Unit Note / Test Con dition ns ns ns ns 1)2)3) Master Mode Timing SCLK clock period MTSR/SLSOx delay from SCLK rising edge MRST setup to SCLK falling edge MRST hold from SCLK falling edge Slave Mode Timing SCLK clock period SCLK duty cycle MTSR setup to SCLK latching edge MTSR hold from SCLK latching edge SLSI setup to first SCLK latching edge SLSI hold from last SCLK latching edge MRST delay from SCLK shift edge t50 t51 t52 t53 CC 2 × TSSC CC 0 SR 13 SR 0 – – – – – 8 – – – 3) 3) t54 SR 4 × TSSC t55/t54 SR 45 t56 SR TSSC + 5 t57 t58 t59 t60 SR TSSC + 5 SR TSSC + 5 SR 7 CC 0 CC – – – – – – – – – – 55 – – – – 15 10 ns % ns ns ns ns ns ns 1)3) – 3)4) 3)4) 3) – – – SLSI to valid data on MRST t61 1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times. 2) SCLK signal high and low times can be minimum 1 × TSSC. 3) TSSCmin = TSYS = 1/fSYS. When fSYS = 80 MHz, t50 = 25 ns. 4) Fractional divider switched off, SSC internal baud rate generation used. Data Sheet 116 V1.3, 2009-09 TC1767 Electrical Parameters t50 SCLK1)2) t51 MTSR1) t51 t52 MRST1) t53 Data valid t51 SLSOx2) 1) This timing is based on the following setup: CON.PH = CON.PO = 0. 2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of a transmission. SSC_TmgMM Figure 34 SSC Master Mode Timing t54 SCLK1) First shift SCLK edge First latching SCLK edge Last latching SCLK edge t55 t56 t55 t57 t56 t57 MTSR1) Data valid Data valid t60 MRST1) t60 t61 SLSI t59 t58 1) This timing is based on the following setup: CON.PH = CON.PO = 0. SSC_TmgSM Figure 35 SSC Slave Mode Timing Data Sheet 117 V1.3, 2009-09 TC1767 Electrical Parameters 5.4 5.4.1 Package and Reliability Package Parameters Table 26 Device TC1767 Thermal Parameters (Operating Conditions apply) Package PG-LQFP-176-5 RΘJCT1) 6.5 RΘJCB1) 5.5 RΘJLeads1) Unit 23 K/W Note 1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances. Thermal resistances as measured by the ‘cold plate method’ (MIL SPEC-883 Method 1012.1). Data Sheet 118 V1.3, 2009-09 TC1767 Electrical Parameters 5.4.2 Package Outline Figure 36 PG-LQFP-176-5, Plastic Green Low Profile Quad Flat Package You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 119 V1.3, 2009-09 TC1767 Electrical Parameters 5.4.3 Flash Memory Parameters The data retention time of the TC1767’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 27 Parameter Program Flash Retention Time, Physical Sector1)2) Program Flash Retention Time Logical Sector1)2) Data Flash Endurance per 32 KB Sector Flash Parameters Symbol Min. Values Typ. Max. – – years Unit Note / Test Condition Max. 1000 erase/program cycles Max. 100 erase/program cycles tRET CC 20 tRETL CC 20 – – years NE CC 30 000 – – cycles Max. data retention time 5 years cycles Max. data retention time 5 years ms s s – Data Flash Endurance, NE8 CC 120000 – EEPROM Emulation (4 × 16 KB) Programming Time per Page3) – tPR CC – – – – – 5 5 2.5 Program Flash Erase tERP CC – Time per 256-KB Sector Data Flash Erase Time tERD CC – for 2 x 32-KB Sector Wake-up time fCPU = 133 MHz fCPU = 133 MHz – tWU CC – 4000/fCPU µs +180 1) Storage and inactive time included. 2) At average weighted junction temperature Tj = 100oC, or the retention time at average weighted temperature of Tj = 110oC is minimum 10 years, or the retention time at average weighted temperature of Tj = 150oC is minimum 0.7 years. 3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes additional 5 ms. Data Sheet 120 V1.3, 2009-09 TC1767 Electrical Parameters 5.4.4 Table 28 Parameter Operation Lifetime1) Quality Declarations Quality Parameters Symbol Values Min. Typ. Max. – – – – Unit Note / Test Condition tOP 24000 hours –2) 3) 2000 V Conforming to JESD22-A114-B ESD susceptibility VHBM according to Human Body Model (HBM) ESD susceptibility VHBM1 of the LVDS pins ESD susceptibility VCDM according to Charged Device Model (CDM) Moisture Sensitivity Level MSL – – – – 500 500 V V – Conforming to JESD22-C101-C – – 3 – Conforming to Jedec J-STD-020C for 240°C 1) This lifetime refers only to the time when the device is powered on. 2) For worst-case temperature profile equivalent to: 2000 hours at Tj = 150oC 16000 hours at Tj = 125oC 6000 hours at Tj = 110oC 3) This 30000 hours worst-case temperature profile is also covered: 300 hours at Tj = 150oC 1000 hours at Tj = 140oC 1700 hours at Tj = 130oC 24000 hours at Tj = 120oC 3000 hours at Tj = 110oC Data Sheet 121 V1.3, 2009-09 www.infineon.com Published by Infineon Technologies AG