TLE4262GM

5-V Low Drop Voltage Regulator TLE 4262 Features • • • • • • • • • • • • Output voltage tolerance ≤ ±2% 200 mA output capability Low-drop voltage Very low standby current consumption Overtemperature protection Reverse polarity protection Short-circuit proof Adjustable reset threshold Wide temperature range Suitable for use in automotive electronics Green Product (RoHS compliant) AEC Qualified P-DSO-14-3, -8, -9, -11, 14 Functional Description TLE 4262 GM is a 5-V low-drop voltage regulator in a P/PG-DSO-20-1,-6,-7,-9,-14,PG-DSO-14 or PG-DSO-20 SMD package. The maximum input voltage is 45 V. The maximum output current is more than 200 mA. The IC is short-circuit proof and includes a temperature protection which turns off the IC at overtemperature. The IC regulates an input voltage VI in the range of 6 V < VI < 45 V to VQ,nom = 5.0 V. A reset signal is generated for an output voltage of VQ,rt < 4.5 V. This voltage threshold can be decreased to 3.5 V by external connection of a voltage divider. The reset delay can be set externally with a capacitor. The IC can be switched off via the inhibit input, which reduces the current consumption from 900 µA to typical 0 µA. Type TLE 4262 GM TLE 4262 G Data Sheet 1 Package PG-DSO-14-30 PG-DSO-20-35 Rev. 2.8, 2008-05-19 TLE 4262 Dimensioning Information on External Components The input capacitor CI is necessary for compensation of line influences. Using a resistor of approx. 1 Ω in series with CI, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed at values ≥ 22 µF and an ESR of ≤ 3 Ω within the operating temperature range. For small tolerances of the reset delay, the spread of the capacitance of the dalay capacitor and its temperature coefficient should be noted. TLE 4262 G Ι N.C. N.C. GND GND GND GND N.C. N.C. Q TLE 4262 GM INH RO N.C. GND GND GND GND N.C. D RADJ 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AEP01083 RO N.C. GND GND GND D RADJ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 AEP02588 INH Ι GND GND GND Q N.C. Figure 1 Pin Configuration (top view) Data Sheet 2 Rev. 2.8, 2008-05-19 TLE 4262 Table 1 Pin PG-DSO-1430 1 Pin Definitions and Functions Pin Symbol PG-DSO-2035 2 RO Function Reset output; open-collector output internally connected to the output via a resistor of 30 kΩ. Not connected Ground Reset delay; connect capacitor to GND for setting delay time Reset threshold; for setting the switching threshold connect by a voltage divider from output to ground. If this input is connected to GND, reset is triggered at an output voltage of 4.5 V. 5-V output voltage; block to ground by capacitor with C ≥ 22 µF, ESR ≤ 3 Ω at 10 kHz. Input voltage; block to ground directly at the IC by a ceramic capacitor. Inhibit; TTL-compatible, low-active input 2, 8 3 - 5, 10 - 12 6 7 3, 8, 12, 13, 18, 19 4 - 7, 14 - 17 9 10 N.C. GND D RADJ 9 11 Q 13 14 20 1 I INH Data Sheet 3 Rev. 2.8, 2008-05-19 TLE 4262 Circuit Description The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. If the externally scaled down output voltage at the reset threshold input drops below 1.35 V, the external reset delay capacitor is discharged by the reset generator. If the voltage on the capacitor reaches the lower threshold VDRL, a reset signal is issued on the reset output and not cancelled again until the upper threshold VDU is exceeded. If the reset threshold input is connected to GND, reset is triggered at an output voltage of 4.5 V. The IC can be switched at the TTL-compatible, low-active inhibit input. It also includes a number of internal circuits for protection against: • • • Overload Overtemperature Reverse polarity Temperature Sensor Saturation Control and Protection Circuit 9 Control Amplifier 6 Buffer Reset Generator 1 7 RO RADJ I 13 Q D Bandgap Reference Adjustment 14 INH 3-5, 10-12 GND AEB01081 Figure 2 Block Diagram Data Sheet 4 Rev. 2.8, 2008-05-19 TLE 4262 Table 2 Parameter Input I Input voltage Input current Absolute Maximum Ratings Symbol Limit Values Min. Max. 45 – 42 – 6 42 – V – V – V V – V – V A °C °C V °C K/W K/W – internally limited – internally limited – – internally limited – internally limited – – – – 1) Unit Remarks VI II VRO IRO VRADJ VD ID VQ IQ VINH IGND Tj Tstg VI Tj Rthj-a Rthj-p -42 – -0.3 – -0.3 -0.3 – -5.25 – -42 -0.5 – -50 5.2 -40 – – Reset Output RO Voltage Current Reset Input RADJ Voltage Reset Delay D Voltage Current Output Q Voltage Current Inhibit INH Voltage Ground GND Current Temperature Junction temperature Storage temperature Operating Range Input voltage Junction temperature Thermal resistance junction-ambient junction-case 45 150 112 32 – 2) 3) VI – 45 – 150 150 1) Corresponds with characteristics of drop voltage, output current and power description (see diagrams). 2) Package mounted on PCB 80 × 80 × 1.5 mm3; 35µ Cu; 5µ Sn; Footprint only; zero airflow. 3) Measured to pin 4. Data Sheet 5 Rev. 2.8, 2008-05-19 TLE 4262 Table 3 Characteristics VI = 13.5 V; Tj = 25 °C; VINH > 3.5 V; (unless specified otherwise) Parameter Normal Operation Output voltage Symbol Limit Values Min. Typ. 5.00 Max. 5.10 V 5 mA ≤ IQ ≤ 150 mA; 6 V ≤ VI ≤ 28 V; -40 °C ≤ Tj ≤ 125 °C 6 V ≤ VI ≤ 32 V; IQ = 100 mA Tj = 100 °C – Unit Test Condition VQ 4.90 Output voltage VQ 4.90 5.00 5.10 V Output current limiting Current consumption; Iq = Ii - IQ Drop voltage Load regulation Line regulation Power Supply Ripple Rejection Reset Generator Switching threshold IQ Iq Iq Iq Iq VDR ∆VQ,lo ∆VQ,li PSRR 200 – – – – – – – – 250 0 0.9 10 15 0.35 – 3 54 – 50 1.3 18 23 0.50 25 25 – mA µA mA mA mA V mV mV dB VINH = 0 V IQ = 0 mA IQ = 150 mA IQ = 150 mA; Vi = 4.5 V IQ = 150 mA1) IQ = 5 mA to 150 mA VI = 6 V to 28 V; IQ = 150 mA fr = 100 Hz; Vr = 0.5 Vpp VRADJ = 0 V VQ > 3.5 V IRO = 1 mA VQ < VRT – – – VQ,rt Reset adjust threshold VRADJ Saturation voltage VRO Saturation voltage VD,sat Charge current ID,c Upper timing threshold VDU Lower timing threshold VDRL trd Reset delay time Reset reaction time trr 4.5 1.26 – – 6 1.4 0.20 – – 4.65 1.35 0.10 50 10 1.8 0.35 17 1.2 4.8 1.44 0.40 100 15 2.2 0.55 – – V V V mV µA V V ms µs CD = 100 nF CD = 100 nF Data Sheet 6 Rev. 2.8, 2008-05-19 TLE 4262 Table 3 Characteristics (cont’d) VI = 13.5 V; Tj = 25 °C; VINH > 3.5 V; (unless specified otherwise) Parameter Inhibit Switch-ON voltage Switch-OFF voltage Input current Symbol Limit Values Min. Typ. – – 10 Max. – 0.8 25 V V µA IC turned on IC turned off Unit Test Condition VINH,ON VINH,OFF IINH 3.6 – 5 VINH = 5 V 1) Drop voltage VI ≥ 4.5 V; drop voltage = VI - VQ (below regulating range) Note: The reset output is low within the range 1 V ≤ VQ ≤ VQ,rt. Data Sheet 7 Rev. 2.8, 2008-05-19 TLE 4262 Input 6 V...45 V 470 nF KL15 Reset to µC Ι 13 INH RO 9Q D 100 nF 7 GND RADJ 56 k Ω Output 22 µF 100 k Ω 14 1 TLE 4262G 6 AES03028 Figure 3 Application Circuit II 1000 µF I 470 nF 13 TLE 4262G 9 Q IQ 22 µF Rext RO 1 4 RADJ IINH VI + Vripple 5.6 k Ω INH IRO VQ VRO 14 6 D GND ID VINH VDR = VI - VQ *) PSRR = 20 log *) Below VD CD IGND Vcd 100 nF Vripple ∆VQ AES03027_4262 Regulation Range Figure 4 Test Circuit Data Sheet 8 Rev. 2.8, 2008-05-19 TLE 4262 VΙ VQ < t rr V Q, rt d V Ι D,c = dt CD t t V DU V DRL VD VRO t rd t rr t t Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output AED03010 Figure 5 Reset Timing Time Response The power-on reset delay time is defined by the charging time of an external capacitor CD which can be calculated as follows: CD = (∆trd × ID,c)/∆V Definitions: • • • • • (1) CD = delay capacitor ∆trd = delay time ID,c = charge current, typical 10 µA ∆V = VDU, typical 1.8 V VDU = upper delay switching threshold at CD for reset delay time Data Sheet 9 Rev. 2.8, 2008-05-19 TLE 4262 Charge Current versus Temperature 16 µA 14 12 AED03090 Upper and Lower Timing Threshold VDU and VDRL versus Temperature 3.2 V V 2.8 2.4 AED01087_4262 ID, c VI = 13.5 V ID, c 10 8 6 4 2 0 -40 2.0 VDU VI = 13.5 V Vcd = 1.5 V 1.6 1.2 0.8 0.4 0 -40 VDRL 0 40 80 120 ˚C 160 0 40 80 120 ˚C 160 Tj Tj Reset Switching Threshold versus Temperature 1.6 VRADJ V 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 AED01088 Current Consumption of Inhibit versus Temperature Output Current 16 µA IINH 14 12 10 8 6 4 2 0 -40 AED03091 VINH = 5 V 0 40 80 120 ˚C 160 0 40 80 120 ˚C 160 Tj Tj Data Sheet 10 Rev. 2.8, 2008-05-19 TLE 4262 Output Voltage versus Temperature 5.2 V 5.1 AED01090 Output Current versus Input Voltage 300 AED01091 VQ ΙQ VI = 13.5 V mA 250 T j = 25 C 5.0 200 4.9 150 4.8 100 4.7 50 4.6 -40 0 40 80 120 ˚C 160 0 0 10 20 30 Tj 40 V 50 VΙ Drop Voltage versus Output Current 800 VDR mV 700 600 500 400 300 200 100 0 mA AED01094 Current Consumption versus Output Current 32 Iq mA 28 24 20 AED01095 VI = 13.5 V T j = 125 ˚C 25 ˚C 16 12 8 4 0 0 50 100 150 200 300 0 50 100 150 200 mA 300 IQ IQ Data Sheet 11 Rev. 2.8, 2008-05-19 TLE 4262 Current Consumption versus Input Voltage 30 AED01096 Output Voltage versus Input Voltage 12 VQ V 10 AED01097 Ιq mA 25 20 R L = 25 Ω 8 15 6 R L = 25 Ω 10 4 5 2 0 0 10 20 30 40 V 50 VΙ 0 0 2 4 6 8 V 10 VΙ Data Sheet 12 Rev. 2.8, 2008-05-19 TLE 4262 Package Outlines 0.35 x 45˚ 1.75 MAX. 0.175 ±0.07 (1.47) C 4 -0.2 1.27 0.41+0.10 2) -0.06 14 B 0.1 0.2 M A B 14x 8 6±0.2 0.64 ±0.25 0.2 M C 1 7 1) 8.75 -0.2 A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area GPS01230 Figure 6 PG-DSO-14-30 (Plastic Dual Small Outline) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 13 Dimensions in mm Rev. 2.8, 2008-05-19 8˚MAX. 1) 0.19 +0.06 TLE 4262 2.45 -0.2 0.2 -0.1 2.65 MAX. 0.35 x 45˚ 1.27 0.35 +0.15 2) 0.4 +0.8 0.1 0.2 20x 11 10.3 ±0.3 20 1 12.8 -0.2 1) Index Marking 1) 2) 10 Does not include plastic or metal protrusion of 0.15 max. per side Does not include dambar protrusion of 0.05 max. per side 8˚ MAX. 7.6 -0.2 1) 0.23 +0.09 GPS05094 Figure 7 PG-DSO-20-35 (Plastic Dual Small Outline) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 14 Dimensions in mm Rev. 2.8, 2008-05-19 TLE 4262 Revision History Version Rev. 2.8 Date Changes 2008-05-19 Modification according to PCN No. 2008-096: Typo corrected: Current consumption Iq specification @ IQ = 150mA on page 6. 2007-03-20 Initial version of RoHS-compliant derivate of TLE 4262 Page 1: AEC certified statement added Page 1 and Page 13 ff: RoHS compliance statement and Green product feature added Page 1 and Page 13 ff: Package changed to RoHS compliant version Legal Disclaimer updated Rev. 2.7 Data Sheet 15 Rev. 2.8, 2008-05-19 Edition 2008-05-19 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. 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