TLE42744EV50

Data Sheet, Rev. 1.1, January 2010 TLE42744 Low Dropout Linear Voltage Regulator Automotive Power Low Dropout Linear Voltage Regulator TLE42744 1 Features • • • • • • • • • • Overview Very Low Current Consumption Output Voltages 5 V and 3.3 V ±2% Output Current up to 400 mA Very Low Dropout Voltage Output Current Limitation Reverse Polarity Protection Overtemperature Shutdown Wide Temperature Range From -40 °C up to 150 °C Green Product (RoHS compliant) AEC Qualified PG-TO252-3 PG-SSOP-14 exposed pad PG-TO263-3 Description PG-SOT223-4 The TLE42744 is a monolithic integrated low dropout voltage regulator for load currents up to 400 mA. An input voltage up to 40 V is regulated to VQ,nom = 5 V / 3.3 V with a precision of ±2%. The device is designed for the harsh environment of automotive applications. Therefore it is protected against overload, short circuit and overtemperature conditions by the implemented output current limitation and the overtemperature shutdown circuit. The TLE42744 can be also used in all other applications requiring a stabilized 5 V / 3.3 V voltage. Due to its very low quiescent current the TLE42744 is dedicated for use in applications permanently connected to VBAT. Type TLE42744DV50 TLE42744GV50 TLE42744EV50 TLE42744DV33 TLE42744GV33 TLE42744GSV33 Data Sheet Package PG-TO252-3 PG-TO263-3 PG-SSOP-14 exposed pad PG-TO252-3 PG-TO263-3 PG-SOT223-4 2 Marking 42744V5 42744V5 42744V5 42744V33 42744V33 42744V33 Rev. 1.1, 2010-01-13 TLE42744 Block Diagram 2 Block Diagram Temperature Sensor Saturation Control and Protection Circuit Q Control Amplifier Buffer Ι Bandgap Reference GND AEB01959 Figure 1 Block Diagram Data Sheet 3 Rev. 1.1, 2010-01-13 TLE42744 Pin Configuration 3 3.1 Pin Configuration Pin Assignment PG-TO252-3, PG-TO263-3 and PG-SOT223-4 GND GND 4 1 Ι Q 3 1 I 2 GND PinConfig_PG-SOT2234.vsd 3 Q AEP02561 Ι GND Q AEP02281 Figure 2 Pin Configuration (top view) 3.2 Pin No. 1 2 3 Pin Definitions and Functions PG-TO252-3, PG-TO263-3and PG-SOT223-4 Symbol Function I GND Q Input block to ground directly at the IC with a ceramic capacitor Ground internally connected to heat slug Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in “Functional Range” on Page 7 Heat Slug internally connected to GND; connect to GND and heatsink area Heat Slug / 4 – Data Sheet 4 Rev. 1.1, 2010-01-13 TLE42744 Pin Configuration 3.3 Pin Assignment PG-SSOP-14 exposed pad Figure 3 Pin Configuration (top view) 3.4 Pin No. Pin Definitions and Functions PG-SSOP-14 exposed pad Symbol Function n.c. GND n.c. Q not connected can be open or connected to GND Ground not connected can be open or connected to GND Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in “Functional Range” on Page 7 Input block to ground directly at the IC with a ceramic capacitor Exposed Pad connect to GND and heatsink area 1, 2, 3, 5, 6, 7 4 8, 10, 11, 12, 14 9 13 Pad I – Data Sheet 5 Rev. 1.1, 2010-01-13 TLE42744 General Product Characteristics 4 4.1 General Product Characteristics Absolute Maximum Ratings Absolute Maximum Ratings1) Tj = -40 °C to 150 °C; all voltages with respect to ground, (unless otherwise specified) Pos. Input I 4.1.1 Output Q 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 Voltage Junction temperature Storage temperature ESD Absorption Voltage Parameter Symbol Min. Limit Values Max. 45 40 150 150 4 1000 V V °C °C kV V – – – – Human Body Model (HBM)2) Charge Device Model (CDM)3) at all pins Unit Test Condition VI VQ Tj Tstg VESD,HBM VESD,CDM -42 -1 -40 -50 -4 -1000 Temperature ESD Susceptibility 1) not subject to production test, specified by design 2) ESD susceptibility Human Body Model “HBM” according to AEC-Q100-002 - JESD22-A114 3) ESD susceptibility Charged Device Model “CDM” according to ESDA STM5.3.1 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 6 Rev. 1.1, 2010-01-13 TLE42744 General Product Characteristics 4.2 Pos. 4.2.1 Functional Range Parameter Input voltage Symbol Limit Values Min. Max. 40 V TLE42744DV50, TLE42744GV50, TLE42744EV50 TLE42744GV33, TLE42744DV33, TLE42744GSV33 1) 2) Unit Remarks VI 5.5 4.2.2 Input voltage VI 4.7 40 V 4.2.3 4.2.4 4.2.5 Output Capacitor’s Requirements for Stability Junction temperature CQ ESR(CQ) Tj 22 – -40 – 3 150 µF Ω °C – 1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% 2) relevant ESR value at f = 10 kHz Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. Parameter Symbol Min. TLE42744DV50, TLE42744DV33 (PG-TO252-3) 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 TLE42744GV50, TLE42744GV33 (PG-TO263-3) 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 Junction to Case1) Junction to Ambient1) Junction to Case1) Junction to Ambient1) Limit Values Typ. 3.6 27 115 52 40 Max. – – – – – K/W K/W K/W K/W K/W measured to heat slug 2) Unit Conditions RthJC RthJA – – – – – footprint only3) 300 mm² heatsink area3) 600 mm² heatsink area3) measured to heat slug 2) RthJC RthJA – – – – – 3.6 22 74 42 34 – – – – – K/W K/W K/W K/W footprint only3) 300 mm² heatsink area3) 600 mm² heatsink area3) Rev. 1.1, 2010-01-13 Data Sheet 7 TLE42744 General Product Characteristics Pos. Parameter Symbol Min. TLE42744EV50 (PG-SSOP-14 exposed pad) 4.3.11 4.3.12 4.3.13 4.3.14 4.3.15 TLE42744GSV33 (PG-SOT223-4) 4.3.16 4.3.17 4.3.18 4.3.19 4.3.20 Junction to Case1) Junction to Ambient1) Junction to Case1) Junction to Ambient1) Limit Values Typ. 7 43 120 59 49 Max. – – – – – K/W K/W K/W K/W K/W measured to exposed pad 2) Unit Conditions RthJC RthJA – – – – – footprint only3) 300 mm² heatsink area3) 600 mm² heatsink area3) measured to heat slug 2) RthJC RthJA – – – – – 17 54 139 73 64 – – – – – K/W K/W K/W K/W K/W footprint only3) 300 mm² heatsink area3) 600 mm² heatsink area3) 1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). Data Sheet 8 Rev. 1.1, 2010-01-13 TLE42744 Electrical Characteristics 5 5.1 Electrical Characteristics Electrical Characteristics Voltage Regulator Electrical Characteristics VI =13.5 V; Tj = -40 °C to 150 °C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Output Q 5.1.1 Output Voltage Typ. 5.0 Max. 5.1 V TLE42744DV50, TLE42744GV50, TLE42744EV50 5 mA < IQ< 400 mA 6 V < VI < 28 V TLE42744DV50, TLE42744GV50, TLE42744EV50 5 mA < IQ