TLE42994GM

Low Dropout Fixed Voltage Regulator TLE42994 1 Features • • • • • • • • • • • • • • • • • Overview Output Voltage 5 V ± 2% Ouput Current up to 150 mA Extreme Low Current Consumption In ON State Enable Function: Below 1 µA Current Consumption In OFF State Early Warning Power-on and Undervoltage Reset with Programmable Delay Time Reset Low Down to VQ = 1 V Adjustable Reset Threshold Very Low Dropout Voltage Output Current Limitation Reverse Polarity Protection Overtemperature Protection Suitable for Use in Automotive Electronics Wide Temperature Range from -40 °C up to 150 °C Input Voltage Range from -42 V to 45 V Green Product (RoHS compliant) AEC Qualified PG-DSO-8 PG-DSO-14 Description The TLE42994G is a monolithic integrated low dropout voltage regulator, especially designed for automotive applications that need to be in ON state during the car’s engine is turned off. An input voltage up to 45 V is regulated to an output voltage of 5.0 V. The component is able to drive loads up to 150 mA. It is short-circuit protected by the implemented current limitation and has an integrated overtemperature shutdown. A reset signal is generated for an output voltage VQ,rt of typically 4.65 V. This threshold can be decreased by an external resistor divider. The power-on reset delay time can be programmed by PG-SSOP-14 Type TLE42994G TLE42994GM TLE42994E Data Sheet Package PG-DSO-8 PG-DSO-14 PG-SSOP-14 1 Marking 42994G 42994GM 42994E Rev. 1.1, 2009-05-19 TLE42994 Overview the external delay capacitor. The additional sense comparator provides an early warning function: Any voltage (e.g. the input voltage) can be monitored, an under-voltage condition is indicated by setting the comparator’s output to low. The TLE42994GM (PG-DSO-14 package) and TLE42994E (PG-SSOP-14 package) include additionally an Enable function permitting enabling/disabling the regulator. In case the regulator is disabled it consumes less current than 1 µA. Dimensioning Information on External Components The input capacitor CI is recommended for compensation of line influences. The output capacitor CQ is necessary for the stability of the control loop. Circuit Description The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any oversaturation of the power element. The component also has a number of internal circuits for protection against: • • • Overload Overtemperature Reverse polarity Data Sheet 2 Rev. 1.1, 2009-05-19 TLE42994 Block Diagram 2 Block Diagram I BandGapReference Current and Saturation Control Q RSO RRO SO SI Reference Reset Control RADJ RO D GND AEB03103 Figure 1 Block Diagram TLE42994G (package PG-DSO-8) Data Sheet 3 Rev. 1.1, 2009-05-19 TLE42994 Block Diagram TLE 4299 I BandGapReference Current and Saturation Control Q RSO EN INH Inhibit Enable Control RRO SO SI Reference Reset Control RADJ RO D GND AEB03104 Figure 2 Block Diagram TLE42994GM, TLE42994E (packages PG-DSO-14, PG-SSOP-14) Data Sheet 4 Rev. 1.1, 2009-05-19 TLE42994 Pin Configuration 3 3.1 Pin Configuration Pin Assignment TLE42994G (PG-DSO-8) Ι SΙ RADJ D 1 2 3 4 8 7 6 5 AEP01668 Q SO RO GND Figure 3 Pin Configuration (top view) 3.2 Pin 1 Pin Definitions and Functions TLE42994G (PG-DSO-8) Symbol I Function Input for compensating line influences, a capacitor to GND close to the IC terminals is recommended Sense Input connect the voltage to be monitored; connect to Q if the sense comparator is not needed Reset Threshold Adjust connect an external voltage divider to adjust reset threshold; connect to GND for using internal threshold Reset Delay Timing connect a ceramic capacitor to GND for adjusting the reset delay time; leave open if the reset function is not needed Ground Reset Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the reset function is not needed Sense Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the sense comparator is not needed Output block to GND with a capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in “Functional Range” on Page 10 2 SI 3 RADJ 4 D 5 6 GND RO 7 SO 8 Q Data Sheet 5 Rev. 1.1, 2009-05-19 TLE42994 Pin Configuration 3.3 Pin Assignment TLE42994GM (PG-DSO-14) RADJ D GND GND GND EN RO 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SI I GND GND GND Q SO PinConfig_PG-DSO-14.vsd Figure 4 Pin Configuration (top view) 3.4 Pin 1 Pin Definitions and Functions TLE42994GM (PG-DSO-14) Symbol Function Reset Threshold Adjust connect an external voltage divider to adjust reset threshold; connect to GND for using internal threshold Reset Delay Timing connect a ceramic capacitor to GND for adjusting the reset delay time; leave open if the reset function is not needed Ground connect all pins to PCB and heatsink area Enable high signal enables the regulator; low signal disables the regulator; connect to I if the Enable function is not needed Reset Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the reset function is not needed Sense Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the sense comparator is not needed Output block to GND with a capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in the table “Functional Range” on Page 10 Ground connect all pins to PCB and heatsink area Input for compensating line influences, a capacitor to GND close to the IC terminals is recommended Sense Input connect the voltage to be monitored; connect to Q if the sense comparator is not needed 6 Rev. 1.1, 2009-05-19 RADJ 2 D 3, 4, 5 6 GND EN 7 RO 8 SO 9 Q 10, 11, 12 GND 13 I 14 SI Data Sheet TLE42994 Pin Configuration 3.5 Pin Assignment TLE42994E (PG-SSOP-14) RADJ n.c. D GND EN n.c. RO 1 2 3 4 5 6 7 14 13 12 11 10 9 8 PINCONFIG_SSOP-14.VSD SI I n.c. Q n.c. n.c. SO Figure 5 Pin Configuration (top view) 3.6 Pin 1 Pin Definitions and Functions TLE42994E (PG-SSOP-14) Symbol Function Reset Threshold Adjust connect an external voltage divider to adjust reset threshold; connect to GND for using internal threshold not connected leave open or connect to GND Reset Delay Timing connect a ceramic capacitor to GND for adjusting the reset delay time; leave open if the reset function is not needed Ground connect all pins to PCB and heatsink area Enable high signal enables the regulator; low signal disables the regulator; connect to I if the Enable function is not needed Reset Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the reset function is not needed Sense Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the sense comparator is not needed not connected leave open or connect to GND Output block to GND with a capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in the table “Functional Range” on Page 10 Input for compensating line influences, a capacitor to GND close to the IC terminals is recommended RADJ 2, 6 3 n.c. D 4 5 GND EN 7 RO 8 SO 9, 10, 12 11 n.c. Q 13 I Data Sheet 7 Rev. 1.1, 2009-05-19 TLE42994 Pin Configuration Pin 14 Symbol SI Function Sense Input connect the voltage to be monitored; connect to Q if the sense comparator is not needed Exposed Pad attach the exposed pad on package bottom to the heatsink area on circuit board; connect to GND PAD – Data Sheet 8 Rev. 1.1, 2009-05-19 TLE42994 General Product Characteristics 4 4.1 General Product Characteristics Absolute Maximum Ratings Absolute Maximum Ratings 1) -40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Input I, Enable Input EN, Sense Input SI 4.1.1 Voltage Max. 45 V – Unit Conditions VI, VEN, VSI VQ, VRO, VSO -40 Output Q, Reset Output RO, Sense Output SO 4.1.2 Voltage -0.3 7 V – Reset Delay D, Reset Threshold RADJ 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 Voltage Junction Temperature Storage Temperature ESD Absorption VD, VRADJ -0.3 Tj Tstg VESD,HBM VESD,CDM -40 -50 -2 -500 -750 7 150 150 2 500 750 V °C °C kV V V – – – Human Body Model (HBM)2) Charge Device Model (CDM)3) Charge Device Model (CDM)3) at corner pins Temperature ESD Absorption 1) not subject to production test, specified by design 2) ESD susceptibility Human Body Model “HBM” according to AEC-Q100-002 - JESD22-A114 3) ESD susceptibility Charged Device Model “CDM” according to ESDA STM5.3.1 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 9 Rev. 1.1, 2009-05-19 TLE42994 General Product Characteristics 4.2 Pos. 4.2.1 4.2.2 4.2.3 Functional Range Parameter Input Voltage Output Capacitor’s Requirements for Stability Junction Temperature Symbol Min. Limit Values Max. 45 – 3 150 V µF Ω °C – –1) –2) – 5.5 22 – -40 Unit Conditions VI CQ ESR(CQ) Tj 1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% 2) relevant ESR value at f = 10 kHz Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Data Sheet 10 Rev. 1.1, 2009-05-19 TLE42994 General Product Characteristics 4.3 Pos. Thermal Resistance Parameter Symbol Limit Value Min. Typ. – 113 185 142 136 Max. 60 – – – – K/W K/W K/W K/W K/W measured to pin 5 2) Unit Conditions TLE42994G (PG-DSO-8) 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 TLE42994GM (PG-DSO-14) 4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 TLE42994E (PG-SSOP-14) 4.3.14 4.3.15 4.3.16 4.3.17 4.3.18 Junction to Case1) Junction to Ambient1) Junction to Soldering Point1) Junction to Ambient 1) Junction to Soldering Point1) Junction to Ambient 1) RthJSP RthJA – – – – – Footprint only3) 300mm2 heatsink area on PCB3) 600mm2 heatsink area on PCB3) measured to all GND pins 2) RthJSP RthJA – – – – – – 63 112 73 65 30 – – – – K/W K/W K/W K/W K/W Footprint only3) 300mm2 heatsink area on PCB3) 600mm2 heatsink area on PCB3) – 2) RthJC RthJA – – – – – 10 47 140 63 53 – – – – – K/W K/W K/W K/W K/W Footprint only3) 300mm2 heatsink area on PCB3) 600mm2 heatsink area on PCB3) 1) not subject to production test, specified by design 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). Data Sheet 11 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics 5 5.1 Block Description and Electrical Characteristics Voltage Regulator The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Functional Range” on Page 10 have to be maintained. For details see also the typical performance graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 15. As the output capacitor also has to buffer load steps it should be sized according to the application’s needs. An input capacitor CI is strongly recommended to compensate line influences. Connect the capacitors close to the component’s terminals. A protection circuitry prevents the IC as well as the application from destruction in case of catastrophic events. These safeguards contain an output current limitation, a reverse polarity protection as well as a thermal shutdown in case of overtemperature. To avoid excessive power dissipation that could never be handled by the pass element and the package, the maximum output current is decreased at input voltages above VI = 22 V. The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator restarts. This leads to an oscillatory behaviour of the output voltage until the fault is removed. However, junction temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime. The TLE42994 allows a negative supply voltage. In this fault condition, small currents are flowing into the IC, increasing its junction temperature. This has to be considered for the thermal design, respecting that the thermal protection circuit is not operating during reverse polarity conditions. Supply II I Q IQ Regulated Output Voltage Saturation Control Current Limitation C CI Temperature S hutdown Bandgap Reference E SR } CQ LOAD BlockDiagram_VoltageRegulator.vsd GND Figure 6 Voltage Regulator Data Sheet 12 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics Electrical Characteristics Voltage Regulator VI = 13.5 V, -40 °C ≤ Tj ≤150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 5.1.9 Output Current Limitation Load Regulation steady-state Line Regulation steady-state Dropout Voltage1) Parameter Output Voltage Symbol Min. Limit Values Typ. 5.0 5.0 400 -5 10 220 – 15 66 Max. 5.1 5.15 500 – 25 500 200 – – mA mV mV mV °C °C dB V 100 µA < IQ < 100 mA 6 V < VI < 18 V 100 µA < IQ < 150 mA 6 V < VI < 18 V 4.9 4.85 Unit Conditions VQ IQ,max ∆VQ,load ∆VQ,line Vdr Tj,sd Tj,sdh PSRR 150 -30 – – 151 – – Vdr = VI - VQ Overtemperature Shutdown Threshold Overtemperature Shutdown Threshold Hysteresis Power Supply Ripple Rejection3) VQ = 4.8V IQ = 1 mA to 100 mA VI = 6 V VI = 6 V to 32 V IQ = 1 mA IQ = 100 mA Tj increasing2) Tj decreasing2) fripple = 100 Hz Vripple = 1 Vpp IQ = 100 mA 1) measured when the output voltage VQ has dropped 100mV from the nominal value obtained at VI = 13.5V 2) not subject to production test, specified by design 3) not subject to production test, specified by design Data Sheet 13 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics 5.2 Typical Performance Characteristics Voltage Regulator Output Current IQ versus Input Voltage VI 01_VQ_TJ.VSD Output Voltage VQ versus Junction Temperature TJ 5,20 400 350 300 02_IQ_VI.VSD 5,10 5,00 T j = - 40 °C IQ,max [mA] 250 200 150 100 T j = 25 °C T j = 150 °C V Q [V] 4,90 VI = 7 V I Q = 5 mA 4,80 4,70 50 0 4,60 -40 0 40 80 120 160 0 10 20 30 40 50 T j [°C] Power Supply Ripple Rejection PSRR versus ripple frequency fr 100 90 80 70 03_PSRR_FR.VSD V I [V] Line Regulation ∆VQ,line versus Input Voltage Change ∆VI 0,9 0,8 0,7 0,6 04_DVQ_DVI.VSD T j = -40 °C T j = 25 °C T j = 150 °C T j = 150 °C PSRR [dB] ∆V Q [mV] 60 50 40 30 20 10 0 0,01 T j = 25 °C 0,5 0,4 0,3 0,2 0,1 0 T j = -40 °C I Q = 10 mA C Q = 10 µF ceramic V I = 13.5 V V ripple = 0.5 Vpp 0,1 1 10 100 1000 0 10 20 30 40 f [kHz] V I [V] Data Sheet 14 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics 5.3 Load Regulation ∆VQ,load versus Output Current Change ∆IQ 5 0 -5 05_DVQ_DIQ.VSD Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ 100 06_ESR_IQ_CORRECTED.VSD VI = 6 V 10 Unstable Region ESR(C Q) [Ω ] ∆V Q [mV] -10 1 T j = -40 °C -15 C Q = 22 µF T j = -40..150 °C V I = 6..28 V T j = 25 °C T j = 150 °C 0,1 -20 -25 0 50 100 150 Stable Region 0,01 0 50 100 150 I Q [mA] Dropout Voltage Vdr versus Junction Temperature Ti 300 07_VDR_TJ.VSD I Q [mA] I Q = 100 mA 250 200 V DR [ mV] 150 I Q = 25 mA 100 50 I Q = 5 mA 0 -40 0 40 80 120 160 T j [°C] Data Sheet 15 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics 5.4 Current Consumption Electrical Characteristics Voltage Regulator VI = 13.5 V, -40 °C ≤ Tj ≤150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 5.4.1 Parameter Current Consumption Symbol Min. Limit Values Typ. – Max. 1 µA – Unit Conditions Iq = II - IQ Iq VEN = 0 V TLE42994GM and TLE42994E only Tj = 25 °C 5.4.2 – 65 100 µA Enable HIGH IQ = 100 µA Tj = 25 °C 5.4.3 – 65 105 µA Enable HIGH IQ = 100 µA Tj ≤ 85 °C Enable HIGH IQ = 10 mA Enable HIGH IQ = 50 mA 5.4.4 5.4.5 – – 0.17 0.7 0.5 2 mA mA Data Sheet 16 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics 5.5 Typical Performance Characteristics Current Consumption Current Consumption Iq versus Output Current IQ (IQ low) 08_IQ_IQ.VSD Current Consumption Iq versus Output Current IQ 6 V I = 13.5 V 1 0,9 V I = 13.5 V 09_IQ_IQ_IQ LOW.VSD 5 T j = 150 °C T j = 25 °C T j = 150 °C T j = 25 °C 0,8 0,7 0,6 4 I q [mA] I q [mA] 0 50 100 150 3 0,5 0,4 0,3 0,2 0,1 2 1 0 0 0 10 20 30 40 50 I Q [mA] Current Consumption Iq versus Input Voltage VI 12 10_IQ _VI.VSD I Q [mA] 10 8 I q [mA] 6 R LOAD = 100 Ω 4 2 R LOAD = 50 k Ω 0 0 10 20 30 40 V I [V] Data Sheet 17 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics 5.6 Enable Function (only TLE42994GM and TLE42994E) Electrical Characteristics Voltage Regulator VI = 13.5 V, -40 °C ≤ Tj ≤150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 5.6.1 5.6.2 5.6.3 5.6.4 Parameter Enable OFF Voltage Range Enable ON Voltage Range Enable OFF Input Current Enable ON Input Current Symbol Min. Limit Values Typ. – – 0.5 3 Max. 0.8 – 2 5 V V µA µA – – – 3.5 – – Unit Conditions VEN,OFF VEN,ON IEN,OFF IEN,ON VEN = 0 V VEN = 5 V 5.7 Reset Function The reset function provides several features: Output Undervoltage Reset: An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal might be used to reset a microcontroller during low supply voltage. Power-On Reset Delay Time: The power-on reset delay time trd allows a microcontoller and oscillator to start up. This delay time is the time frame from exceeding the reset switching threshold VRT until the reset is released by switching the reset output “RO” from “low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD connected to pin D charged by the delay capacitor charge current ID,ch starting from VD = 0 V. If the application needs a power-on reset delay time trd different from the value given in Item 5.7.8, the delay capacitor’s value can be derived from the specified values in Item 5.7.8 and the desired power-on delay time: t rd, new C D = ---------------- × 100nF t rd with • • • CD: capacitance of the delay capacitor to be chosen trd,new: desired power-on reset delay time trd: power-on reset delay time specified in this datasheet For a precise calculation also take the delay capacitor’s tolerance into consideration. Data Sheet 18 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics Reset Reaction Time: The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset “low” signal. The reset reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the external delay capacitor CD (see typical performance graph for details). Hence, the total reset reaction time becomes: t rr = t rd, int + t rr, d with • • • trr: reset reaction time trr,int: internal reset reaction time trr,d: reset discharge Optional Reset Output Pull-Up Resistor RRO,ext: The Reset Output RO is an open collector output with an integrated pull-up resistor. If needed, an external pull-up resistor to the output Q can be added. In Table “Electrical Characteristics Reset Function” on Page 22 a minimum value for the external resistor RRO,ext is given. Reset Adjust Function The undervoltage reset switching threshold can be adjusted according to the application’s needs by connecting an external voltage divider (RADJ1, RADJ2) at pin RADJ. For selecting the default threshold connect pin RADJ to GND. When dimensioning the voltage divider, take into consideration that there will be an additional current constantly flowing through the resistors. With a voltage divider connected, the reset switching threshold VRT,new is calculated as follows: R ADJ, 1 + R ADJ, 2 V RT, new = ----------------------------------------- × V RADJ, th R ADJ, 2 with • • • VRT,new: the desired new reset switching threshold RADJ1, RADJ2: resistors of the external voltage divider VRADJ,th: reset adjust switching threshold given in Table “Electrical Characteristics Reset Function” on Page 22 Data Sheet 19 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics Supply I Q optional VDD Int. Supply Control RRO ID,ch RO CQ I RO RRO,ext Reset VRADJ,th OR VDST RADJ,1 ID,dch RADJ optional MicroController I RADJ GND BlockDiagram_ResetAdjust.vsd D RADJ,2 CD GND Figure 7 Block Diagram Reset Function Data Sheet 20 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics VI t VQ VRT t < trr,total 1V t VD V DU V DRL t VRO t rd trr,total trd t rr,total t rd t rr,total t rd V RO,low 1V t Thermal Shutdown Input Voltage Dip Undervoltage Spike at output Overload T i mi n g Di a g ra m_ Re se t . vs Figure 8 Timing Diagram Reset Data Sheet 21 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics Electrical Characteristics Reset Function VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Output Undervoltage Reset 5.7.1 Default Output Undervoltage Reset VRT Switching Thresholds Reset Adjust Switching Threshold Reset Adjustment Range1) Reset Output Low Voltage Reset Output Internal Pull-up Resistor to VQ Optional Reset Output External Pull-up Resistor to VQ Delay Pin Output Voltage Power On Reset Delay Time 4.5 4.65 4.8 V Limit Values Typ. Max. Unit Conditions VQ decreasing Output Undervoltage Reset Threshold Adjustment 5.7.2 5.7.3 5.7.4 5.7.5 5.7.6 VRADJ,th VRT,range VRO,low RRO RRO,ext 1.26 3.50 – 10 5.6 1.36 – 0.1 20 – 1.44 4.65 0.4 40 – V V V kΩ kΩ 3.5 V ≤ VQ < 5 V – 1 V ≤ VQ ≤ VRT no external RRO,ext – 1 V ≤ VQ ≤ VRT ; VRO ≤ 0.4 V – Reset Output RO Reset Delay Timing 5.7.7 5.7.8 VD trd VDU VDL ID,ch ID,dch trr,d – 17 – 28 5 35 V ms CD = 100 nF – – Calculated Value: trd = CD * VDU / ID,ch 5.7.9 5.7.10 5.7.11 5.7.12 5.7.13 Upper Delay Switching Threshold Lower Delay Switching Threshold Delay Capacitor Charge Current Delay Capacitor Reset Discharge Current Delay Capacitor Discharge Time – – – – – 1.85 0.50 8.0 70 1.9 – – – – 3 V V µA mA µs VD = 1 V VD = 1 V Calculated Value: 5.7.14 5.7.15 Internal Reset Reaction Time Reset Reaction Time trr,int trr,total – – 14 15.9 20 23 µs µs trr,d = CD*(VDU VDL)/ ID,dch CD = 100 nF CD = 0 nF 2) Calculated Value: trr,total = trr,int + trr,d CD = 100 nF 1) VRT is scaled linearly, in case the Reset Switching Threshold is modified 2) parameter not subject to production test; specified by design Data Sheet 22 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics 5.8 Typical Performance Characteristics Reset Power On Reset Delay Time trd versus Junction Temperature Tj Undervoltage Reset Switching Threshold VRT versus Junction Temperature Tj 5 11_VRT_TJ.VSD 30 25 12_TRD_TJ.VSD 4,9 C D = 100 nF t rd [ m s ] 4,8 20 15 10 5 V RT [V] 4,7 4,6 4,5 0 4,4 -40 0 40 80 120 160 -40 T j [°C] 10 60 110 160 T j [°C] Delay Capacitor Discharge Time trr,d versus Junction Temperature Tj 2,5 14_TRRD_TJ.VSD 13_TRRINT _TJ.VSD Internal Reset Reaction Time trr,int versus Junction Temperature Tj 25 20 2 15 1,5 t rr,int [ µs] t rr,d [µs] 10 1 5 0,5 0 -40 10 60 110 160 0 -40 10 60 110 160 T j [°C] T j [°C] Data Sheet 23 Rev. 1.1, 2009-05-19 TLE42994 Block Description and Electrical Characteristics 5.9 Early Warning Function The additional sense comparator provides an early warning function: Any voltage (e.g. the input voltage) can be monitored, an undervoltage condition is indicated by setting the comparator’s output to low. Sense Input Voltage VSI, High VSI, Low t Sense Output High Low t AED03049 Figure 9 Sense Timing Diagram Electrical Characteristics Early Warning Function VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Sense Comparator Input 5.9.1 5.9.2 5.9.3 5.9.4 Sense Threshold High Sense Threshold Low Sense Switching Hysteresis Sense Input Current Limit Values Typ. 1.45 1.36 90 -0.1 Max. 1.54 1.44 130 1 V V mV µA – – Unit Conditions VSI,high VSI,low VSI,hy ISI 1.34 1.26 50 -1 24 VSI,hy = VSI,high - VSI,low – Rev. 1.1, 2009-05-19 Data Sheet TLE42994 Block Description and Electrical Characteristics Electrical Characteristics Early Warning Function VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Sense Comparator Output 5.9.5 Sense Output Low Voltage Limit Values Typ. 0.1 Max. 0.4 V Unit Conditions VSO,low – VSI < VSI,low VI > 5.5 V – no external RSO,ext 5.9.6 5.9.7 Sense Output Internal Pull-up Resistor to VQ RSO 10 5.6 20 – 40 – kΩ kΩ Optional Sense Output External RSO,ext Pull-up Resistor to VQ VI > 5.5 V VSO ≤ 0.4 V 5.10 Typical Performance Characteristics Early Warning Sense Thresholds VSI,high, VSI,low versus Junction Temperature Tj 1,45 15_VSI_T J.VSD V SI,high 1,4 1,35 V SI,low 1,3 1,25 1,2 1,15 1,1 1,05 1 -40 10 60 110 160 V SI [V] T j [°C] Data Sheet 25 Rev. 1.1, 2009-05-19 TLE42994 Package Outlines 6 Package Outlines 0.35 x 45˚ 1.75 MAX. 0.175 ±0.07 (1.45) 4 -0.21) 0.19 +0.06 C 1.27 0.41+0.1 2) -0.06 0.2 M 0.1 A B 8x B 6 ±0.2 0.64 ±0.25 0.2 M 8 MAX. C 8x GPS01181 Rev. 1.1, 2009-05-19 8 5 1 4 5 -0.2 1) Index Marking A 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area Figure 10 PG-DSO-8 Data Sheet 26 TLE42994 Package Outlines 0.35 x 45˚ 1.75 MAX. 0.175 ±0.07 (1.47) C 4 -0.2 1.27 0.41+0.10 2) -0.06 14 B 0.1 0.2 M A B 14x 8 6±0.2 0.64 ±0.25 0.2 M C 1 7 1) 8.75 -0.2 A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area GPS01230 Figure 11 PG-DSO-14 Data Sheet 27 Rev. 1.1, 2009-05-19 8˚MAX. 1) 0.19 +0.06 TLE42994 Package Outlines 0.35 x 45˚ Stand Off (1.45) 1.7 MAX. 3.9 ±0.11) 0.1 C D 0 ... 0.1 0.19 +0.06 0.08 C 6 ±0.2 0.65 0.25 ±0.05 2) C 0.64 ±0.25 D 0.2 8˚ MAX. M 0.15 M C A-B D 14x D 8x A 14 8 Bottom View 3 ±0.2 1 7 1 7 B 0.1 C A-B 2x Exposed Diepad 14 8 4.9 ±0.11) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion PG-SSOP-14-1,-2,-3-PO V02 Figure 12 PG-SSOP-14 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 28 2.65 ±0.2 Dimensions in mm Rev. 1.1, 2009-05-19 TLE42994 Revision History 7 Revision 1.1 Revision History Date 2009-05-19 Changes Updated version Data Sheet: Typing error corrected in Chapter 5.2 in conditions for graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 15: “10µF” corrected to “22µF”, no change done in specification of electrical parameters 1.0 2008-12-04 initial version Data Sheet Data Sheet 29 Rev. 1.1, 2009-05-19 Edition 2009-05-19 Published by Infineon Technologies AG 81726 Munich, Germany © 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. 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