TLE4299GV33

Low-Drop Fixed Voltage Regulator TLE 4299 Features • • • • • • • • • • • Output voltage 3.3V ± 2% 150 mA Output current Extreme low current consumption in ON state Inhibit function: Below 1 µA current consumption in off mode Early warning Reset output low down to VQ = 1 V Overtemperature protection Reverse polarity proof Wide temperature range Green Product (RoHS compliant) AEC Qualified P-DSO-8-3 Functional Description The TLE 4299 is a monolithic voltage regulator with fixed P-DSO-14-3, -8, -9, -11 5-V (see data sheet TLE4299G/GM) or 3.3 V output, supplying loads up to 150 mA. It is especially designed for applications that may not be powered down while the motor is off. In addition the TLE 4299GMV includes an inhibit function. When the inhibit signal is removed, the device is switched off and the quiescent current is less than 1 µA. To achieve proper operation of the µ-controller, the device supplies a reset signal. The reset delay time is selected application-specific by an external delay capacitor. The reset threshold is adjustable. An early warning signal supervises the voltage at pin SI. The TLE 4299 is pin-compatible to the TLE 4269 and functional similar with the additional inhibit function. The TLE 4299 is designed to supply microcontroller systems even under automotive environment conditions. Therefore it is protected against overload, short circuit and over temperature. Type TLE 4299 GV33 TLE 4299 GMV33 Datasheet 1 Package PG-DSO-8-16 PG-DSO-14-30 Rev. 1.1, 2007-10-17 TLE 4299 Circuit Description The TLE 4299 is a PNP based very low drop linear voltage regulator. It regulates the output voltage to VQ = 3.3 V for an input voltage range of 4.4 V ≤ VI ≤ 45 V. The control circuit protects the device against potential damages caused by overcurrent and overtemperature. The internal control circuit achieves a 3.3 V output voltage with a tolerance of ± 2%. The device includes a power on reset and an under voltage reset function with adjustable reset delay time and adjustable reset switching threshold as well as a sense control/early warning function. The device includes an inhibit function to disable it when the ECU is not used for example while the motor is off. The reset logic compares the output voltage VQ to an internal threshold. If the output voltage drops below this level, the external reset delay capacitor CD is discharged. When VD is lower than VST, the reset output RO is switched Low. If the output voltage drop is very short, the VST level is not reached and no reset-signal is asserted. This feature avoids resets at short negative spikes at the output voltage e.g. caused by load changes. As soon as the output voltage is more positive than the reset threshold, the delay capacitor is charged with constant current. When the voltage reaches VDT the reset output RO is set High again. The reset delay time and the reset reaction time are defined by the external capacitor CD. The reset function is active down to VI = 1 V. In addition to the normal reset function, the device gives an early warning. When the SI voltage drops below VSI,low, the devices asserts the SI output Low to indicate the logic and the µ-processor that this voltage has dropped. The sense function uses a hysteresis: When the SI-voltage reaches the VSI,high level, SO is set high again. This feature can be used as early warning function to notice the µ-controller about a battery voltage drop and a possible reset in a short time. Of course also any other voltage can be observed by this feature. The user defines the threshold by the resistor-values RSI1 and RSI2. For the exact timing and calculation of the reset and sense timing and thresholds, please refer to the application section. Datasheet 2 Rev. 1.1, 2007-10-17 TLE 4299 TLE 4299 I BandGapReference Current and Saturation Control Q RSO RRO SO SI Reference Reset Control RADJ RO D GND AEB03103 Figure 1 Block Diagram TLE 4299 GV33 Datasheet 3 Rev. 1.1, 2007-10-17 TLE 4299 TLE 4299 I BandGapReference Current and Saturation Control Q RSO INH Inhibit Control RRO SO SI Reference Reset Control RADJ RO D GND AEB03104 Figure 2 Block Diagram TLE 4299 GMV33 Datasheet 4 Rev. 1.1, 2007-10-17 TLE 4299 PG-DSO-8-16 I SI RADJ D 1 2 3 4 8 7 6 5 Q SO RO GND AEP02832 Figure 3 Pin Configuration (top view) Pin Definitions and Functions (TLE 4299 GV33) Pin No. 1 2 3 4 5 6 7 8 1) Symbol I SI RADJ D GND RO SO Q Function Input; block directly to GND on the IC with a ceramic capacitor. Sense Input; if not needed connect to Q. Reset Threshold Adjust; if not needed connect to GND. Reset Delay; to select delay time, connect to GND via external capacitor. Ground Reset Output; the open-collector output is linked internally to Q via a 20kΩ pull-up resistor. Keep open, if the pin is not needed. Sense Output; open-collector output. Keep open, if the pin is not needed. Output; connect to GND with a 22 µF capacitor, 0.4 Ω < ESR < 3.7 Ω.1) see characteristic curves Datasheet 5 Rev. 1.1, 2007-10-17 TLE 4299 PG-DSO-14-30 RADJ D GND GND GND INH RO 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SI I GND GND GND Q SO AEP02831 Figure 4 Pin Configuration (top view) Pin Definitions and Functions (TLE 4299 GMV33) Pin No. 1 2 3, 4, 5 6 7 8 9 Symbol RADJ D GND INH RO SO Q Function Reset Threshold Adjust; if not needed connect to GND. Reset Delay; connect to GND via external delay capacitor for setting delay time. Ground Inhibit: If not needed connect to Input pin I; A high signal switches the regulator ON. Reset Output; the open-collector output is linked internally to Q via a 20kΩ pull-up resistor. Keep open, if the pin is not needed. Sense Output; open-collector output. Keep open, if the pin is not needed. Output; connect to GND with a 22 µF capacitor, 0.4 Ω < ESR < 3.7 Ω.1) Ground Input; block to GND directly at the IC by a ceramic capacitor. Sense Input; if not needed connect to Q. 10, 11, 12 GND 13 14 1) I SI see characteristic curves Datasheet 6 Rev. 1.1, 2007-10-17 TLE 4299 Absolute Maximum Ratings Tj = – 40 to 150 °C Parameter Symbol Limit Values min. Input I Input voltage Inhibit Input INH Input voltage Sense Input SI Input voltage Input current max. Unit Notes VI – 40 45 V – VINH – 40 45 V – VSI ISI – 0.3 -1 45 1 V mA – – Reset Threshold Adjust RADJ Input voltage Input current Reset Delay D Voltage Reset Output RO Voltage Sense Output SO Voltage Output Q Output voltage Output current VRADJ IRADJ – 0.3 -10 7 10 V mA – – VD – 0.3 7 V – VR – 0.3 7 V – VSO – 0.3 7 V – VQ IQ – 0.3 –5 7 – V mA – – Datasheet 7 Rev. 1.1, 2007-10-17 TLE 4299 Absolute Maximum Ratings (cont’d) Tj = – 40 to 150 °C Parameter Symbol Limit Values min. Temperature Junction temperature Storage temperature Operating Range Input voltage Junction temperature Thermal Data Junction-ambient for foot Rthja print only1) Junction-ambient for 300mm2 cooling area2) Junction-pin – – – 200 130 164 70 60 30 K/W K/W K/W K/W K/W K/W PG-DSO-8-16 PG-DSO-14-30 PG-DSO-8-16 PG-DSO-14-30 PG-DSO-8-163) PG-DSO-14-30 4) 1) 2) 3) 4) Unit Notes max. Tj TStg – – 50 150 150 °C °C – – VI Tj 4.4 – 40 45 150 V °C – – Rthja Rthjp FR4, 80x80x1,5mm; 35µ Cu, 5µ Sn; Footprint only FR4, 80x80x1,5mm; 35µ Cu, 5µ Sn; 300mm2 Measured to pin 5 Measured to pin 4 Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. In the operating range, the functions given in the circuit description are fulfilled. Datasheet 8 Rev. 1.1, 2007-10-17 TLE 4299 Characteristics VI = 13.5 V; Tj = – 40 °C < Tj < 150 °C Parameter Output voltage Output voltage Current limit Current consumption; Iq = II – IQ Current consumption; Iq = II – IQ Current consumption; Iq = II – IQ Current consumption; Iq = II – IQ Load regulation Line regulation Power Supply Ripple rejection Symbol Limit Values min. typ. max. 3.23 3.30 3.37 3.20 3.30 3.40 250 – – – – – – – 400 500 65 105 Unit Measuring Condition V V mA µA µA mA µA mV mV dB 1 mA ≤ IQ ≤ 100 mA; 5.5 V ≤ VI ≤ 16 V VQ VQ IQ Iq Iq Iq Iq ∆VQ ∆VQ IQ ≤ 150 mA; 5.5 V ≤ VI ≤ 16 V – Inhibit ON; IQ ≤ 1 mA, Tj < 85 °C Inhibit ON; IQ = 10 mA Inhibit ON; IQ = 50 mA 170 500 0.7 – 5 10 66 2 1 30 25 – VINH = 0 V; Tj = 25 °C IQ = 1 mA to 100 mA VI = 6 V to 28 V; IQ = 1 mA fr = 100 Hz; Vr = 1 VSS; IQ = 100 mA PSRR Inhibit (TLE 4299 GMV33 only) Inhibit OFF voltage range VINH OFF – Inhibit ON voltage range High input current Low input current – 3 0.5 0.8 5 2 V V µA µA VQ off VQ on VINH = 5V VINH = 0.8 V VINH ON IINH ON IINH OFF 3.5 – – Datasheet 9 Rev. 1.1, 2007-10-17 TLE 4299 Characteristics (cont’d) VI = 13.5 V; Tj = – 40 °C < Tj < 150 °C Parameter Symbol Limit Values min. typ. max. Reset Generator Switching threshold Reset threshold headroom Reset pull up Reset low voltage External reset pull up Switching threshold Reset delay low voltage Charge current Power-up Reset delay time Reset reaction time Reset Adjust Switching Threshold Input Voltage Sense Sense threshold high Sense threshold low Sense input switching hysteresis Unit Measuring Condition Vrt 3.00 3.10 3.20 200 300 20 40 V mV kΩ V kΩ V V V µA ms µs V – – – VRTHEAD 50 RRO VR VR ext VST VD Ich td trr VRADJ TH 10 – 5.6 1.6 – 2.0 36 0.5 0.17 0.40 – – VQ < 3.0 V; internal RRO; IR = 1 mA Pull up resistor Q – – Delay switching threshold VDT 1.85 2.35 – 3.5 51 1.2 0.1 6.0 60 3.0 0.35 0.50 0.60 VQ < VRT VD = 1 V CD = 100 nF CD = 100 nF VQ < 3.5V 1.26 1.36 1.44 VSI high VSI low 1.34 1.45 1.54 1.26 1.36 1.44 90 0.1 – 0.1 130 0.4 – 1 V V mV V kΩ µA – – VSI HYST 50 – 5.6 –1 VSI HYST = VSI high – VSI low VSI < 1.20 V; Vi > 4.2 V; ISO = 1mA – Si > 1.0V Sense output low voltage VSO low External SO pull up resistor Sense input current RSO ext ISI Datasheet 10 Rev. 1.1, 2007-10-17 TLE 4299 Characteristics (cont’d) VI = 13.5 V; Tj = – 40 °C < Tj < 150 °C Parameter Symbol – Limit Values min. typ. max. Sense high reaction time tpd SO LH Sense low reaction time 2.4 2.5 4.0 6.0 µs µs Unit Measuring Condition RSO ext = 5.6kΩ RSO ext = 5.6kΩ tpd SO HL – Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. II VI I TLE 4299 Q1 IQ1 VQ1 IINH VINH (TLE4299GMV33 only) INH D RO CD 100 nF VRO Ich IRADJ VRADJ VSI RADJ ISI SI GND SO VSO IGND AES02835 Figure 5 Measurement Circuit Datasheet 11 Rev. 1.1, 2007-10-17 TLE 4299 Application Information TLE 4299 VBAT CI1 CI2 I C Q 22 F Q2 CQ1 P BandGapReference Current and Saturation Control RSO RRO RSI1 SI SO RSI2 Reference Reset Control RO RADJ1 RADJ GND D CD RADJ2 AES03105 Figure 6 Application Diagram TLE 4299 GV33 Datasheet 12 Rev. 1.1, 2007-10-17 TLE 4299 TLE 4299 VBAT CI1 CI2 I C Q 22 F Q2 CQ1 P BandGapReference Current and Saturation Control RSO From KI. 15 INH Inhibit Logic RRO SO RSI1 SI RSI2 Reference Reset Control RO RADJ1 RADJ GND D CD RADJ2 AES03106 Figure 7 Application Diagram with Inhibit Function TLE4299 GMV33 The TLE 4299 supplies a regulated 3.3 V output voltage with an accuracy of 2% for an input voltage between 4.4 V and 45 V in the temperature range of Tj = – 40 to 150 °C, in an output current range of 1 mA to 100 mA. The device is capable to supply 150 mA with an accuracy of 3%. For protection at high input voltage above 25 V, the output current is reduced (SOA protection). An input capacitor is necessary for compensating line influences and to limit steep input edges. A resistor of approx. 1 Ω in series with CI, can damp the LC of the input inductivity and the input capacitor. The voltage regulator requires for stability an output capacitor CQ of at least 22 µF with an 0.4Ω < ESR < 3.7Ω for the whole load- and temperature range. For more detailed information, refer to the characteristical curves. Datasheet 13 Rev. 1.1, 2007-10-17 TLE 4299 Reset The power on reset feature is necessary for a defined start of the microprocessor when switching on the application. For the reset delay time after the output voltage of the regulator is above the reset threshold, the reset signal is set High again. The reset delay time is defined by the reset delay capacitor CD at pin D. The under-voltage reset circuitry supervises the output voltage. In case VQ decreases below the reset threshold the reset output is set LOW after the reset reaction time. The reset LOW signal is generated down to an output voltage VQ to 1 V. Both the reset reaction time and the reset delay time is defined by the capacitor value. The power on reset delay time is defined by the charging time of an external delay capacitor CD. CD = (td × ID) / ∆V td = CD x ∆V / ID With [1] [2] CD td ∆V Ich reset delay capacitor reset delay time = VDT, typical 1.8 V for power up reset charge current typical 3.5 µA For a delay capacitor CD =100 nF the typical power on reset delay time is 51 ms. The reset reaction time tRR is the time it takes the voltage regulator to set reset output LOW after the output voltage has dropped below the reset threshold. It is typically 1.2 µs for delay capacitor of 100 nF. For other values for CD the reaction time can be estimated using the following equation: tRR ∼ 10 ns / nF × CD [3] Datasheet 14 Rev. 1.1, 2007-10-17 TLE 4299 VI VQ V RT t < t RR VD V DT V ST V RO VRO, SAT td t RR dV I D = dt C D t t t Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output AED03107 Figure 8 Reset Timing Diagram The reset output is an open collector output. An external pull-up can be added with a resistor value of at least 5.6 kΩ. In addition the reset switching threshold can be adjusted by an external voltage divider. The feature is useful for microprocessors which guarantee safe operation down to voltages below the internally set reset threshold of 3.10V typical. If the internal used reset threshold of typical 3.10V is used, the pin RADJ has to beconnected to GND. If a lower reset threshold is required by the system, a voltage divider defines the reset threshold VRth between 2.5V and 3.10V as long as the Input Voltage VI>4.4V VRth = VRADJ TH * (RADJ1 + RADJ2) / RADJ2 (3) VRADJ TH is typical 1.36 V. Datasheet 15 Rev. 1.1, 2007-10-17 TLE 4299 Early Warning The early warning function compares a voltage defined by the user to an internal reference voltage. Therefore the supervised voltage has to be scaled down by an external voltage divider in order to compare it to the internal sense threshold of typical 1.36 V. The sense output pin is set low, when the voltage at SI falls below this threshold. A typical example where the circuit can be used is to supervise the input voltage VI to give the microcontroller a prewarning of low battery condition. Calculation to the voltage divider can be easily done since the sense input current can be neglected. Sense Input Voltage VSI, High VSI, Low t Sense Output High t PD SO LH t PD SO HL Low t Figure 9 Sense Timing Diagram VthHL = (RSI1 + RSI2)/RSI2 × VSI low VthLH = (RSI1 + RSI2)/RSI2 × VSI high [4] [5] The sense in comparator uses a hysteresis of typical 90 mV. This hysteresis of the supervised threshold is multiplied by the resistor dividers amplification (RSI1 + RSI2)/RSI1. The sense in comparator can also be used for receiving data with a threshold of typical 1.36 V and a hysteresis of 90 mV. Of course also the data signal can be scaled down with a resistive divider as shown above. With a typical delay time of 2.5 µs for positive transitions and 2.4 µs for negative transitions receiving data of up to 100 kBaud are possible. The sense output is an open collector output. Datasheet 16 Rev. 1.1, 2007-10-17 TLE 4299 Current Consumption Iq versus Junction Temperature Tj 1_Iq-Tj.vsd Current Consumption Iq versus Output Current IQ 12 2_IQ-IQ.VSD Iq [µA] VI = 13.5V 100 Iq [mA] IQ = 1mA 10 8 Tj = 150 °C 6 Tj = 25 °C 4 1 Tj = -40 °C 2 0.01 -40 -20 0 20 40 60 80 100 120 140 0 40 80 120 160 Tj [°C] IQ [mA] Current Consumption Iq versus Input Voltage VI 3 3_IQ-VI.VSD Output Voltage VQ versus Junction Temperature Tj 3.5 AED01671 Iq [mA] T = 25°C VQ V 3.4 V Ι = 13.5 V 3.3 2 1.5 3.2 1 3.1 0.5 IQ = 10mA IQ = 1mA 0 10 20 30 40 3.0 2.9 -40 0 40 80 120 C 160 Tj VI [V] Datasheet 17 Rev. 1.1, 2007-10-17 TLE 4299 Maximum Output Current IQ versus Junction Temperature Tj 550 8_IQMAX-TJ.VSD Reverse Output Current IQ versus Output Voltage VQ 10 10_IQ-VQ.vsd IQ [mA] IQ [mA] -20 VI = 0 V Tj = -40 °C Tj = 25 °C Tj = 150 °C 450 VI = 13.5 V -40 400 -60 350 -80 300 -100 250 -40 -20 0 20 40 60 80 100 120 140 0 10 20 30 40 Tj [°C] VQ [V] Maximum Output Current IQ versus Input Voltage VI 350 Ι Q mA 300 250 200 150 100 Tj = 25 C AED03110 Output Voltage VQ at Input Voltage Extremes VQ 6 [V] AED01808 4 3 RL = 50 Ω Tj = 125 C 2 1 50 0 0 0 1 2 3 4 VΙ V5 0 10 20 30 40 V 50 VΙ Datasheet 18 Rev. 1.1, 2007-10-17 TLE 4299 Region of Stability 100 12_ESRIQ_150.VSD Power Supply Ripple Rejection PSRR versus Frequency f 90 13_PSRR.VSD ESRCQ [Ω] CQ = 22µF Tj = 150 °C VI=6V VI=25V PSRR [dB] 10 IQ = 0.1 mA 70 IQ = 1 mA 1 VI=25V VI=6V 0.1 Stable Region 60 50 IQ = 10 mA VRIPPLE = 0.5 V VIN = 13.5 V CQ = 22 µF Tantalum Tj = 25 °C 100 1k 40 IQ = 100 mA 0.01 0 40 80 120 160 10 10k 100k IQ [mA] f [Hz] Region of Stability 100 12_ESR-IQ_40.VSD Load Transient Response Peak Voltage DVQ CQ = 22µF Tj = -40 °C IQ1:100mA VI=6V VI=25V 20_Load Trancient vs time 125.vsd ESRCQ [Ω] 10 Tj=125°C Vi=13.5V 1 VI=25V 0.1 VI=6V Stable Region VQ 0.01 0 40 80 120 160 T=1µs/DIV VQ=100mV/DIV IQ [mA] Datasheet 19 Rev. 1.1, 2007-10-17 TLE 4299 Line Transient Response Peak Voltage DVQ 21_Line Trancient vs time 125.vsd Inhibit Input Current at Input Voltage Extremes (INH=OFF) 25_IINH vs VIN INH_off.vsd dVI 2V Tj=125°C Vi=13.5V [µA] 50 IINH INH = OFF 40 30 Tj = -40...150°C VQ 20 10 T=500µs/DIV VQ=50mV/DIV 10 20 30 40 VIN [V] Inhibut Input Current IINH at Inhibit Input Voltage Extremes 24_IINH vs VINH.vsd Reset Trigger Threshold VRT versus Junction Temperature Tj 3.25 26_VRT VS TEMP.VSD [µA] 50 IINH VRT [V] VI = 13.5 V 40 3.15 Tj = 150°C 30 3.10 Reset Trigger Threshold 20 Tj = 25°C Tj = -40°C 3.05 10 3.0 10 20 30 40 -40 -20 0 20 40 60 80 100 120 140 VINH [V] Tj [°C] Datasheet 20 Rev. 1.1, 2007-10-17 TLE 4299 Reset Delay Time TRD versus Junction Temperature Tj 60 [ms] 27_RESETDELAY VS TEMP.VSD Sense Threshold High versus Junction Temperature Tj 1.60 34_VSI_HI VS TEMP.VSD TRD VI = 13.5 V VSI_Hi [V] VI = 13.5 V 50 CD = 100nF 1.50 45 1.45 40 1.40 35 1.35 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] Delay Capacitor Charge Current versus Junction Temperature Tj 6 [µA] 27A_ID-TEMP.VSD Sense Threshold Low versus Junction Temperature Tj 1.50 35_VSI_LO VS TEMP.VSD ICH VI = 13.5 V VSI_Lo [V] VI = 13.5 V 4 1.40 3 1.35 2 1.30 1 1.25 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] Datasheet 21 Rev. 1.1, 2007-10-17 TLE 4299 Package Outlines PG-DSO-8-16 (SMD) (Plastic Dual Small Outline) 0.35 x 45˚ 1.75 MAX. 0.175 ±0.07 (1.45) 4 -0.21) 0.19 +0.06 C 1.27 0.41+0.1 2) -0.06 0.2 M 0.1 A B 8x B 6 ±0.2 0.64 ±0.25 0.2 M 8 MAX. C 8x GPS01181 8 5 1 4 5 -0.2 1) Index Marking A 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). SMD = Surface Mounted Device Datasheet 22 Dimensions in mm Rev. 1.1, 2007-10-17 TLE 4299 PG-DSO-14-30 (SMD) (Plastic Dual Small Outline) 0.35 x 45˚ 1.75 MAX. 0.175 ±0.07 (1.47) C 4 -0.2 1.27 0.41+0.10 2) -0.06 14 B 0.1 0.2 M A B 14x 8 6±0.2 0.64 ±0.25 0.2 M C 1 7 1) 8.75 -0.2 A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area GPS01230 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). SMD = Surface Mounted Device Datasheet 23 Dimensions in mm Rev. 1.1, 2007-10-17 8˚MAX. 1) 0.19 +0.06 TLE 4299 Revision History Version Rev. 1.1 Date Changes 2007-10-17 Initial version of RoHS-compliant derivate of TLE 4299 Page 1: AEC certified statement added Page 1 and Page 22f: RoHS compliance statement and Green product feature added Page 1 and Page 22f: Package drawing changed to RoHS compliant version Legal Disclaimer updated Datasheet 24 Rev. 1.1, 2007-10-17 Edition 2007-10-17 Published by Infineon Technologies AG 81726 Munich, Germany © 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. 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