TLE4470_08

Dual Low-Drop Voltage Regulator TLE 4470 Features • • • • • • • • • • • • • • • Stand-by output 180 mA; 5 V ± 2% Adjustable reset switching threshold Main output 350 mA; tracked to the stand-by output Low quiescent current consumption in standby mode Disable function for main output Wide operation range: up to 45 V Very low dropout Power-On-Reset circuit sensing the stand-by voltage Early warning comparator for supply undervoltage Output protected against short circuit Wide temperature range: -40 °C to 150 °C Overtemperature protection Overload protection Green Product (RoHS compliant) AEC Qualified P-DSO-14-1, -4, -7 PG-DSO-14 P/PG-DSO-20-1,-6,-7,-9,-14,-1 Functional Description PG-DSO-20 The TLE 4470 is a monolithic integrated voltage regulator with two very low-drop outputs, a main output Q2 for loads up to 350 mA and a stand by output Q1 providing a maximum of 180 mA. The device is available in two packages the PG-DSO-14 and PG-DSO-20. It is designed to supply microprocessor systems under the severe conditions of automotive applications and is therefore equipped with additional protection functions against overload, short circuit and overtemperature. Of course the TLE 4470 can also be used in other applications where two stabilized voltages are required. The device operates in the wide junction temperature range of -40 °C to 150 °C. The stand-by regulator transforms an input voltage VI in the range of 5.6 V ≤ VI ≤ 45 V to VQ1,nom = 5 V within an accuracy of 2%, whereas the main regulator is adjustable. By Type TLE 4470 GS TLE 4470 G Data Sheet 1 Package PG-DSO-14 PG-DSO-20 Rev. 1.2, 2008-03-20 TLE 4470 use of an external voltage divider the main output voltage can be set to VQ2 ≥ 5 V for the TLE 4470 G type (PG-DSO-20 package). VQ1 is compared to the voltage at pin ADJ2, which is proportional to the output voltage VQ2. A control amplifier drives the base of the series PNP transistor via a buffer. The main output voltage VQ2 is tracked to the accuracy of the stand-by output. For the TLE 4470 GS (PG-DSO-14 package) the output voltage is fixed to 5 V. To save energy e.g. in battery powered body electronic applications, the main regulator can be switched off via the disable input, which causes the current consumption to drop to 180 µA typical. Two additional features of the TLE 4470 are an early warning comparator (can be used e.g. to monitor the supply voltage VI) and reset generator with an adjustable reset delay time. The TLE 4470 G (PG-DSO-20 package) has in addition an adjustable reset switching threshold. This feature is useful with microprocessors which guarantee a safe operation down to voltages below the internally set reset threshold of 4.65 V typical. Two functions are included in the reset generator, a power-on-reset and an undervoltage reset. The power-on-reset feature is necessary for a defined start of the microprocessor when switching on the application. The reset signal is kept low for a certain delay time after the output voltage VQ1 of the regulator has surpassed the reset threshold. An external delay capacitor sets this delay time. The under voltage reset circuit supervises the stand-by output voltage. In case VQ1 falls below the reset switching threshold the reset output is set LOW after a short reaction time. The reset LOW signal is generated down to an output voltage VQ1 of 1 V. PG-DSO-14 D DIS GND GND GND RQ SQ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SI PG-DSO-20 RADJ D DIS GND GND GND GND RQ SQ Q1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SI Ι1 Ι2 GND GND GND GND Q2 Q2 ADJ2 AEP02151 Ι GND GND GND Q2 Q1 AEP02152 Figure 1 Pin Configuration (top view) Data Sheet 2 Rev. 1.2, 2008-03-20 TLE 4470 Pin Definitions and Functions Table 1 Pin No. 1 PG-DSO-20 Symbol RADJ Function Reset switching threshold adjust; for setting the reset switching threshold connect to a voltage divider from Q1 to GND. If this input is connected to GND, the reset is triggered at the internal threshold. Reset delay; connect a capacitor CD to GND for delay time adjustment Disable input main regulator; Q2 disabled with high signal Ground Reset output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor Sense output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor Stand-by regulator output voltage; block to GND with a capacitor CQ1 ≥ 6 µF, ESR < 10 Ω at 10 kHz Main regulator adjust input; Q2 can be set to higher values than 5 V by an external voltage divider from Q2 to GND Main regulator output voltage; block to GND with a capacitor CQ2 ≥ 10 µF, ESR < 10 Ω at 10 kHz Ground Main regulator input voltage; block to GND directly at the IC with a ceramic capacitor Stand-by regulator input voltage; block to GND directly at the IC with a ceramic capacitor Sense comparator input 2 3 4, 5, 6, 7 8 9 10 11 D DIS GND RQ SQ Q1 ADJ2 12, 13 14, 15, 16, 17 18 19 20 Q2 GND I2 I1 SI Data Sheet 3 Rev. 1.2, 2008-03-20 TLE 4470 Table 2 Pin No. 1 2 3, 4, 5 6 7 8 9 PG-DSO-14 Symbol D DIS GND RQ SQ Q1 Q2 Function Reset delay; connect a capacitor CD to GND for delay time adjustment Disable input main regulator; Q2 disabled with high signal Ground Reset output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor Sense output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor Stand-by regulator output voltage; block to GND with a capacitor, CQ1 ≥ 6 µF, ESR < 10 Ω at 10 kHz Main regulator output voltage; 5 V output tracking to Q1, block to GND with a capacitor CQ2 ≥ 10 µF, ESR < 10 Ω at 10 kHz Ground Main and stand-by regulator input voltage; block to GND directly at the IC with a ceramic capacitor Sense comparator input 10, 11, 12 13 14 GND I SI RADJ: Adjustable reset switching threshold is not available in the PG-DSO-14 package. Reset is always triggered at the internal threshold. ADJ2: Main regulator adjust input is internally connected to VQ2. Data Sheet 4 Rev. 1.2, 2008-03-20 TLE 4470 Ι1 19 10 Q1 Reference 18 3 V REF Stand-by-Regulator 12, 13 11 Ι2 DIS Q2 ADJ2 Main Regulator V REF 2 Ιd 8 30 k Ω V Q1 1 30 k Ω 9 D RQ = V RADJTH Reset RADJ SQ SI 20 = Sense V SITH 4-7 14-17 GND Pin numbers valid for P-DSO-20-6 (TLE 4470 G) AEB02153 Figure 2 Block Diagram Data Sheet 5 Rev. 1.2, 2008-03-20 TLE 4470 Table 3 Absolute Maximum Ratings -40 °C < Tj < 150 °C Parameter Stand-by Regulator Input I1 Voltage Current Main Regulator Input I2 Voltage Current Stand-by Output Q1 Voltage Current Main Output Q2 Voltage Current Voltage Current Sense Output SQ Voltage Current Reset Output RQ Voltage Current Disable Input DIS Voltage Current Sense Input SI Voltage Current Symbol Limit Values Min. Max. 45 – 45 – 7 – 36 – 18 – 25 5 25 5 45 2 18 2 V mA V mA V mA V mA V mA V mA V mA V mA V mA – Internally limited – Internally limited – Internally limited – Internally limited – Internally limited – – – – – – – – Unit Remarks VI1 II1 VI2 II2 VQ1 IQ1 VQ2 IQ2 VADJ2 IADJ2 VSQ ISQ VRQ IRQ VDIS IDIS VSI ISI -42 – -42 – -1 – -1 – -0.3 – -0.3 -5 -0.3 -5 -42 -2 -25 -2 Main Regulator Adjust Input ADJ2 Data Sheet 6 Rev. 1.2, 2008-03-20 TLE 4470 Table 3 Absolute Maximum Ratings (cont’d) -40 °C < Tj < 150 °C Parameter Reset Delay D Voltage Current Voltage Current Temperatures Junction temperature Storage temperature Symbol Limit Values Min. Max. 7 2 7 – 150 150 V mA V mA °C °C – – – Internally limited – – Unit Remarks VD ID VRADJ IRADJ Tj Tstg -0.3 -2 -0.3 – -50 -50 Reset Switching Threshold Adjust RADJ Note: ESD-Protection according to MIL Std. 883: ±2 kV. Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Data Sheet 7 Rev. 1.2, 2008-03-20 TLE 4470 Table 4 Parameter Operating Range Symbol Limit Values Min. Max. 45 V V mA mA V V °C K/W K/W K/W K/W – – – – – – – Measured to pin 4 1) Unit Remarks Stand-by regulator input voltage Main regulator input voltage Stand-by regulator output current Main regulator output current Disable input voltage Sense input voltage Junction temperature Junction pin Junction ambient Junction pin Junction ambient VI1 VI2 IQ1 IQ2 VDIS VSI Tj Rthj-pin Rthj-a Rthj-pin Rthj-a 5.6 VQ2,nom 45 + 0.6 V 0 0 -0.3 -0.3 -40 – – – – 180 350 45 17 150 32 112 23 100 Thermal Resistances PG-DSO-14 Thermal Resistances PG-DSO-20 Measured to pin 4 1) 1) Package mounted on PCB 80 × 80 × 1.5 mm3; 35 µ Cu; 5 µ Sn; Footprint only; zero airflow. Note: In the operating range the functions given in the circuit description are fulfilled. Data Sheet 8 Rev. 1.2, 2008-03-20 TLE 4470 Table 5 Electrical Characteristics VI1 = VI2 = 14 V; VDIS < VDISL; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Stand-by Regulator Output 1 Output voltage Output current limitation Symbol Limit Values Min. Typ. Max. Unit Test Condition VQ1 IQ1 4.90 180 – 5.0 280 300 5.10 – 500 V mA mV 1 mA < IQ1 < 100 mA 1) Output drop voltage; VDRQ1 VDRQ1 = VI1 - VQ1 Current Consumption Quiescent current; stand-by Iq = II1 - IQ1 Quiescent current Iq = II1 - IQ1 Load regulation Load regulation Line regulation IQ1 = 100 mA1) Iq – – 180 180 4 250 300 6 µA µA mA Iq – IQ1 = 300 µA; Tj = 25 °C VDIS > VDISH (Q2 = OFF) IQ1 = 300 µA; VDIS > VDISH (Q2 = OFF) IQ1 = 100 mA; VDIS > VDISH (Q2 = OFF) 1 mA < IQ1 < 150 mA 1 mA < IQ1 < 100 mA Regulator Performance ∆VQ1,Lo ∆VQ1,Lo ∆VQ1,Li – – – – – 4.5 6 – 15 5 5 60 0.3 – – – 50 25 20 – – 5.5 – 10 mV mV mV dB mV/ K V µF Ω Power Supply Ripple PSRR Rejection Temperature output voltage drift dVI1/dt stability Value of output capacitance ESR of output capacitance ∆VQ1/∆T IQ1 = 1 mA; 6 V < VI1 < 28 V 20 Hz < fr < 20 kHz; Vr = 5 Vpp – no reset occurs2) – at 10 kHz VQ1 CQ1 ESRCQ1 Data Sheet 9 Rev. 1.2, 2008-03-20 TLE 4470 Table 5 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Main-Regulator Output 2 Output voltage tracking accuracy Output voltage tracking accuracy Adjust input current Output current limitation Output drop voltage VDRQ2 = VI2 - VQ2 Quiescent current; Iq = II - IQ Quiescent current; Iq = II - IQ Load regulation Line regulation ∆VQ2 = -25 VQ2 - VQ1 -25 ∆VQ2 = VQ2 - VQ1 5 5 – 500 300 25 25 1 – 600 mV mV µA mA mV 5 mA < IQ2 < 100 mA; 6 V < VI2 < 40 V3) 5 mA < IQ2 < 250 mA; 7 V < VI2 < 28 V3) – 1) Symbol Limit Values Min. Typ. Max. Unit Test Condition IADJ2 IQ2 VDRQ2 -1 350 – IQ2 = 200 mA1) Current Consumption Iq Iq – – 7 250 15 500 mA µA IQ2 = 200 mA; IQ1 = 300 µA IQ2 = IQ1 = 300 µA; Tj = 25 °C 5 mA < IQ2 < 200 mA; Regulator Performance ∆VQ2,Lo ∆VQ2,Li – – – – 4.5 10 – 5 5 60 0.5 – – – 25 20 – – 5.5 – 10 mV mV dB mV/ K V µF Ω Power Supply Ripple PSRR Rejection Temperature output voltage drift dVI2/dt stability Value of output capacitance ESR of output capacitance ∆VQ2/∆T IQ2 = 5 mA; 6 V < VI2 < 28 V 20 Hz < fr < 20 kHz; Vr = 5 Vpp – no reset occurs3) – at 10 kHz VQ2 CQ2 ESRCQ2 Data Sheet 10 Rev. 1.2, 2008-03-20 TLE 4470 Table 5 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Disable Input DIS H-input voltage threshold L-input voltage threshold H-input current L-input current Reset switching threshold Reset adjust threshold Reset output low voltage Reset high voltage Reset pull-up resistor Reset charging current Upper timing threshold Lower timing threshold Reset delay time Reset reaction time Symbol Limit Values Min. Typ. – – -1 -2 4.65 1.35 0.15 Max. – 1.4 1 -0.5 4.8 1.45 0.3 V V µA µA V V V – Output 2 active 2.3 V < VDIS < 7 V 0 V < VDIS < 1.4 V RADJ connected to GND Unit Test Condition VDISH VDISL IDISH IDISL VQ, rt VRADJTH VRQL 2.3 – -2 -6 4.5 1.25 – Reset Timing D and Output RQ VQ1 > 3.5 V RRQ = 10 kΩ externally connected to Q1; VQ1 ≥ 1 V VRQH RRQ ID,c VDU VDL trd trr 4.5 20 3 1.5 0.3 12 – – 30 5 1.8 0.4 15 0.5 – 45 9 2.2 0.55 20 2.0 V kΩ µA V V ms µs – Internally connected to Q1 VD = 1 V – – CD = 47 nF CD = 47 nF Data Sheet 11 Rev. 1.2, 2008-03-20 TLE 4470 Table 5 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Min. Sense Input SI and Output SQ Sense threshold voltage Sense threshold hysteresis Sense output low voltage Sense output high voltage Sense pull-up resistor Typ. 1.35 60 0.15 Max. 1.45 100 0.4 V mV V Unit Test Condition VSITH VSIHY VSQL 1.28 25 – VSI decreasing – RSQ = 10 kΩ externally connected to Q1; VSI < 1.1 V; VI1 > 4.5 V VSQH RSQ 4.5 20 – 30 – 45 V kΩ – Internally connected to Q1 1) Measured when the output voltage VQ has dropped 100 mV from the nominal value. 2) Square wave at VI: 8 V to 18 V; f = 10 kHz; tr = tf ≤ 100 ns. 3) VQ2 connected to ADJ2. Data Sheet 12 Rev. 1.2, 2008-03-20 TLE 4470 Application Information VBatt D1 1N4004 Ι 1 19 10 Q1 5V C Q1 10 µF ZD1 C Ι 36 V 100 nF Reference Stand-by-Regulator ( R 1= R 2 ) 10 V C Q2 22 µF 12, 13 Q2 R1 11 ADJ2 Main Regulator R2 CD 100 nF Ι 2 18 Control R SI1 330 k Ω V REF DIS 3 V REF Ιd 2D 8 RQ 30 k Ω V Q1 1 = V RADJTH Reset RADJ 30 k Ω 9 SQ 4-7 14-17 GND SI 20 R SI2 100 k Ω C SI 10 nF = Sense V SITH Pin numbers valid for P-DSO-20-6 (TLE 4470 G) AES02154 Figure 3 Application Circuit Data Sheet 13 Rev. 1.2, 2008-03-20 TLE 4470 Input, Output The input capacitor CI is necessary for compensating line influences. Using a resistor of approx. 1 Ω in series with CI, the LC circuit of input inductivity and input capacitance can be damped. To stabilize the regulation circuits of the stand-by and main regulator, output capacitors CQ1 and CQ2 are necessary. Stability is guaranteed at values CQ1 ≥ 6 µF and CQ2 ≥ 10 µF, both with an ESR ≤ 10 Ω within the operating temperature range. For the TLE 4470 G (PG-DSO-20) the output voltage VQ2 of the main regulator can be adjusted to 5 V ≤ VQ2,nom ≤ 20 V by connecting an external voltage divider to the voltage adjust pin ADJ2. For VQ2 = 5 V the voltage adjust pin has to be connected directly to the main output. For calculating VQ2 or R1 and R2 respectively the following equations can be used: VQ2 = VQ1 × (1 + R1 / R2) or (1) R1 = R2 × (VQ2 / VQ1 - 1) Disable (2) The main regulator of the TLE 4470 can be switched OFF by a voltage above 2.3 V at pin DIS. Reducing this voltage below 1.4 V will switch ON the main regulator again. Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor CD which can be calculated as follows: CD = (∆t × ID,c) / ∆V Definitions: • • • • • (3) LOW after the output voltage has dropped below the reset threshold. It is typically 2 µs for delay capacitor of 100 nF. For other values for CD the reaction time can be estimated using the following equation: CD = delay capacitor ∆t = reset delay time ID,c = charge current, typical 5 µA ∆V = VDU, typical 1.8 V VDU = upper delay switching threshold at CD for reset delay time The reset reaction time trr is the time it takes the voltage regulator to set the reset out trr ≈ 20 s/F × CD (4) Data Sheet 14 Rev. 1.2, 2008-03-20 TLE 4470 VΙ VQ < t rr t V Q, rt d V Ι D,c = dt CD t V DU V DL VD VRO t rd t rr t t Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output AED03010_4470 Figure 4 Reset Timing Reset Switching Threshold The internally set reset threshold is 4.65 V. When using the TLE 4470 G (PG-DSO-20) this threshold can be adjusted to 3.5 V < VQ, rt < 4.6 V by connecting an external voltage divider to pin RADJ. If this pin is not needed, it can be left open or even better connected to GND. R1 = R2 × (VQ, rt - Vref) / Vref or VQ, rt = Vref (1 + R1 / R2) Definitions: • • (5) VQ, rt = Reset threshold Vref = comparator reference voltage, typical 1.35 V (Reset adjust input current ≈ 50 nA) The reset output pin is internally connected to the stand-by output Q1 via a 30 kΩ pull-up resistor. The reset LOW signal at pin RQ is guaranteed down to an output voltage VQ1 of 1 V typical. Data Sheet 15 Rev. 1.2, 2008-03-20 TLE 4470 V I1 VQ1 30 k Ω Band-Gap Reference 1.35 V Band-Gap Reference 1.35 V _