TLE5010

P reli mi nary Dat a Sheet, V 0.9, Ma y 2007 TLE5010 GMR B a sed A ng u lar S en s or S e n so rs D ra ft Edition 2007-05 Published by Infineon Technologies AG 81726 München, Germany © 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TLE5010 Draft Revision History: Previous Version: Page 2007-05 - V 0.9 Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sensors@infineon.com Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15 TLE5010 Draft 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 7 8 2.4 3 4 5 5.1 5.2 5.3 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 GMR Voltage Regulator VRG (VDDG-Voltage) . . . . . . . . . . . . . . . . . 10 Analog Voltage Regulator VRA (VDDA-Voltage) . . . . . . . . . . . . . . . . 10 Digital Voltage Regulator VRD (VDDD-Voltage) . . . . . . . . . . . . . . . . 10 GMR Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical and Magnetic Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset and Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplitude Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature dependent behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . Orthogonality Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Components of the Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Error Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature dependent Offset Value . . . . . . . . . . . . . . . . . . . . . . . . Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplitude Normalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Orthogonality Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resulting Angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Anisotropy Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hysteresis Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Residual Angle Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Parameters after Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.4 5.5 5.5.1 5.5.2 5.6 5.7 15 15 16 17 17 18 18 18 19 19 19 19 19 20 20 20 20 21 21 21 21 22 22 22 22 23 Preliminary Data Sheet V 0.9, 2007-05 TLE5010 Draft 6 7 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 9 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Synchronous Serial Communication Interface (SSC) . . . . . . . . . . . . . SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Spike Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Spike Filter Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Spike Filter On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter for DATA and CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Command Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 27 30 30 30 31 31 32 32 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reserved Registers (08H to 0BH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Data Communication via SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Active Byte Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example: Update X and Y and set ADC-Test Mode . . . . . . . . . . . . . Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Angle Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Test and Temperature Measurement Timing . . . . . . . . . . . . . . . . . Overvoltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Overvoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 44 44 45 46 46 47 47 48 49 49 49 50 50 10 10.1 10.2 11 11.1 11.2 11.3 12 12.1 12.2 12.3 12.4 13 13.1 14 14.1 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Angle Sensor System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 52 53 54 54 54 55 Preliminary Data Sheet 5 V 0.9, 2007-05 Draft GMR Based Angular Sensor TLE5010 1 1.1 Overview Features • Giant MagnetoResistance based principle • Integrated magnetic field sensing for angle measurement • Full 0 - 360° angle measurement • Highly accurate single bit SD-ADC PG-DSO-8-3 • 16 bit representation of sine / cosine values on the interface • Bidirectional SSC interface up to 2 Mbit/s • 3 pin SSC interface, SPI compatible with open drain • ADCs and filters are synchronized with external commands via SSC • Test resistors for simulating angle values • Core supply voltage 2.5 V • 0.25 µm CMOS technology • Automotive qualified: -40°C to +150°C (Junction Temperature) • Latch up immunity according JEDEC standard • ESD > 2 kV (HBM) • Green package with lead-free plating Type TLE5010 Marking 5010-2 Ordering Code tbd. 6 Package PG-DSO-8 V 0.9, 2007-05 Preliminary Data Sheet TLE5010 Draft Overview 1.2 • • • • Target Applications Angular position sensing in automotive applications like: Steering Angle Brushless DC Motor Commutation (e.g. EPS) Rotary Switch General Angular sensing in automotive applications 1.3 Product Description The TLE5010 is a 360° angle sensor, which detects the orientation of a magnetic field. This is achieved by measuring sine and cosine angle components with monolithic integrated GMR elements (Giant Magnetic Resistance). Data communication is done with a bi-directional SSC interface (SPI compatible). The sine and cosine values can be read out. These signals can be digitally processed to calculate the angle orientation of the magnetic field (magnet). This calculation can be done by using a cordic algorithm. It is possible to connect more than one TLE5010 to one SSC Interface of a µC for redundancy or any other reasons. In this case the synchronization of the connected TLE5010 is done by a broadcast command. Each connected TLE5010 can be addressed by a dedicated chip select CS pin. Online diagnostic functionalities are provided to ensure a reliable operation. These are • • • • Angle Test (generated via test voltages feeding the ADC). Crossed signal paths (switchable for comparison) Inverted signs of bit streams Over and undervoltage detections Preliminary Data Sheet 7 V 0.9, 2007-05 TLE5010 Draft Overview 1.4 Pin Configuration (top view) 8 7 6 5 Center of Sensitive Area 1 Figure 1 Table 1 Pin No. 1 2 3 4 5 6 7 8 Pin Configuration 2 3 4 Pin Definitions and Functions Symbol In/Out Function Chip Clock SSC Clock SSC Chip Select SSC Data, open drain Test Pin 1, must be connected to GND Supply voltage Ground Test Pin 2, must be connected to GND CLK SCK CS DATA TST1 VDD GND TST2 I I I I/O I/O I/O Preliminary Data Sheet 8 V 0.9, 2007-05 TLE5010 Draft General 2 2.1 General Functional Description The clock for the sensors will be provided by external. This ensures a synchronously operation in case of multiple system participants. The sensor has its own PLL to generate the necessary clock frequency for the chip operation. 2.2 Block Diagram The block diagram shows all switches in reset position. GND VDD GND-off Comp VDD_max TST1 VDD_O V Comp V DD-off Comp CLK SCK SCK V RG VRG _OV VRG _Rst V RA V RA_OV V RA_Rst VRD VRD_OV V RD_Rst SSC DA TA CS GMR X V DDG Angle V oltage Temperature Sensor A 2 D 1 Comb Filter 16 FIR Filter 16 XH XL GND V DDG FS YNC FCNT Control FSM A 2 D 1 Comb 16 Filter FIR 16 Filter YH YL GND GMR Y 2 differential A ngle Voltage Analog Clock Digital Clock V RG_Rst VRA_Rst VRD_Rst Reset Lock P LL CLK TLE5010 TS T1 TST2 Digital Reset Figure 2 Block Diagram 9 V 0.9, 2007-05 Preliminary Data Sheet TLE5010 Draft General 2.3 Internal Power Supply The internal stages of the TLE5010 are supplied with different voltage regulators. Each voltage regulator has its own over- and undervoltage detection circuits. GMR Voltage Regulator VRG (VDDG-Voltage) The GMR voltage regulator supplies all GMR parts. • GMR Bridges • Test Voltages for Angle Test • ADC Reference Voltage The voltages are monitored in the VRG over- and undervoltage detectors. Analog Voltage Regulator VRA (VDDA-Voltage) The analog voltage regulator supplies the analog parts. • • • • • ADCs PLL (analog) VDD-Off comparator GND-Off comparator VDD Overvoltage detection The voltages are monitored in the VRA over- and undervoltage detectors. Digital Voltage Regulator VRD (VDDD-Voltage) The digital voltage regulator supplies all digital parts. • • • • • Comb filters, FIR filters and Low Pass filter PLL (digital) Control FSM with Bitmap SSC -Interface Counters (Reset, FSYNC, FCNT) The voltages are monitored in the VRD over- and undervoltage detectors. Preliminary Data Sheet 10 V 0.9, 2007-05 TLE5010 Draft General 2.4 GMR Functionality The GMR sensor is implemented in vertical integration. This means, that the GMR active areas are integrated above the logic part. GMR elements change their resistance depending on the direction of the magnetic field. 4 individual GMR elements are connected to one Wheatstone sensor bridge. They sense either the • X component, VX (cosine) or the • Y component, VY (sine) of the applied magnetic field. The advantage of a full-bridge structure is that the GMR signal amplitude is doubled. GMR Resistors 90° S 0° VX VY N ADCX+ ADCX - GND ADCY+ ADCY - V DDG Figure 3 Sensitive bridges of the GMR Sensor1) 1) The arrows in the resistor symbols show the direction of the reference layer Preliminary Data Sheet 11 V 0.9, 2007-05 TLE5010 Draft General The output signal of each bridge is only unambiguous over 180° between two maxima. Therefore two bridges are orientated orthogonal to each other. Using the ARCTAN function, the true 360° angle value can be calculated which is represented by the relation of the X and Y signals. As only the relative values influence the result, the absolute size of the two signals is of minor importance. Therefore most influences to the amplitudes are compensated. Y Component (SIN) VY VX V X Component (COS) VX (COS) 0° 90° 180° 270° 360° Angle α VY (SIN) Figure 4 Ideal Output of the GMR Sensor Preliminary Data Sheet 12 V 0.9, 2007-05 TLE5010 Draft Absolute Maximum Ratings 3 Table 2 Parameter Absolute Maximum Ratings Absolute Maximum Rating Parameters Symbol Limit Values min. max. 6.5 V V °C mT max 5 min. @ tA = 25°C max 5 h @ tA = 25°C max 40 h / lifetime -0.5 -0.5 -40 Unit Notes Voltage on VDD pin respect to ground (VSS) Voltage on any pin respect to ground (VSS) Junction Temperature VDD VIN TJ 6.5 150 |125| |80| VDD + 0.35 V may not be exceeded Magnetic Field Induction B Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < GND) the voltage on VDD pins with respect to ground (GND) must not exceed the values defined by the absolute maximum ratings. Preliminary Data Sheet 13 V 0.9, 2007-05 TLE5010 Draft Operating Range 4 Operating Range The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5010. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 3 Parameter Operating Range ( - 40°C < TJ < 150°C ) Symbol Limit Values min. typ. -5 30 max. 5.5 -10 5.5 45 360 50 15 V mA V mT ° °C Years 1) 2) 3) Unit Notes Supply Voltage Output Current Input Voltage VDD IQ VIN 4.5 -0.3 25 0 -40 - VDD + 0.5 V may not be exceeded In X / Y direction4) sine / cosine Magnetic Induction BXY Angle Range Storage Temperature Overall Life Time 1) 2) 3) Ang TST tlife Directly blocked with 100 nF ceramic capacitor Max current to GND over Open Drain Output The corresponding voltage levels are listed in Table 5 "Electrical Parameters for 4.5V < VDD < 5.5V" on Page 16 Values refer to an homogenous magnetic field (Bxy) without vertical magnetic induction (Bz = 0 mT). By applying a vertical magnetic induction an additional error has to be considered 4) Note: For a calculation of the corresponding ambient temperature the thermal resistances in Table 20 "Package Parameters" on Page 51 have to be used. Preliminary Data Sheet 14 V 0.9, 2007-05 TLE5010 Draft Electrical and Magnetic Parameters 5 5.1 Electrical and Magnetic Parameters Electrical Parameters These are all parameters over operating range, unless otherwise specified. Unless individually specified, typical values correspond to a supply voltage VDD = 5.0 V and 25°C. All other values correspond to - 40°C < TJ < 150°C Table 4 Parameter Supply Current POR Level POR Hysteresis Power On Time PLL Jitter ADC Noise 5) Input Signal Low Level Input Signal High Level Capacitance of SSC Data Pin 1) 2) 3) 4) 5) Electrical Parameters Symbol Limit Values min. 1) Unit max. 20 21 2.9 200 2.0 2) 3.9 2.2 4.42) 0.3 VDD VDD +0.35 6 2) V V pF V mV µs ns mA Notes typ. 15 2.3 30 100 1.3 3.0 1 2 4 IDD - VDD = 4.5 to 5.5V VDD = 6.5 V Power On Reset VPOR 2.0 VPORhy tPon 50 tPLLjit_S tPLLjit_L NADC - VDD > VDDmin & after first edge on fCLK short term 3) long term 4) digits 1 σ @ FIR_BYP = 0 1 σ @ FIR_BYP = 1 Tested only at DATA pin as structures of all pins are identical Internal VL VH -0.35 0.7 VDD CLDATA - Without external pull-up resistor for SSC-Interface Not tested From pulse to pulse Accumulated over 1 ms ADC noise in respect to the peak ADC value specified in “Signal Processing” on Page 23. Noise tested using 1 σ of 100 sample values from Angle Test “000” Preliminary Data Sheet 15 V 0.9, 2007-05 TLE5010 Draft .. Electrical and Magnetic Parameters Electrical Parameters for 4.5V < VDD < 5.5V Symbol Limit Values min. typ. max. -150 225 225 150 0.7 0.4 V V µA µA 0.07 VDD -10 15 15 10 Unit Notes Table 5 Parameter VHY Pull-Up Current IPU Pull-Down Current IPD Input Hysteresis CS, DATA SCK, CLK TST1 TST2 Output Signal Low Level 1) VOL - IQ = - 10 mA IQ = - 5 mA 1) The value -5 mA is not tested 5.2 Table 6 Parameter ESD Protection ESD Protection Symbol Limit Values min. max. ±2 ± 500 kV V HBM 1) CDM 2) Unit Notes ESD Voltage 1) 2) VHBM VCDM - Human Body Model (HBM) according to: JEDEC EIA/JESD22-A114-B (R = 1.5 kΩ, C = 100 pF, TA = 25°C) Charge Device Model (CDM) according to: ANSI ESD STM JEDEC JESD 22-C101-A Class III. Preliminary Data Sheet 16 V 0.9, 2007-05 TLE5010 Draft Electrical and Magnetic Parameters 5.3 Table 7 Parameter GMR Parameters Basic GMR Parameters Symbol Limit Values min. typ. 12337 100 0 max. ±23230 digits 15781 20620 120 3000 10.0 5000 % ° digits @ Calib. Conditions Operating Range @ Calib. Conditions @ Calib. Conditions digits @ Calib. Conditions Unit Notes All parameters over operating range, unless otherwise specified. X, Y Output range X, Y Amplitude 1) X, Y Synchronism X; Y Offset 3) 2) RGADC AX, AY 7402 3922 k OX, OY 80 -10.0 -5000 - -3000 0 X, Y Orthogonality Error X,Y without field 1) 2) 3) 4) ϕ X0, Y0 digits without magnet4) See Figure 4, Page 12 k = 100 x ( AX / AY ). OSIN = ( YMAX + YMIN ) / 2 ; OCOS = ( XMAX + XMIN ) / 2 Not tested. Offset and Amplitude VY +A 0° 0 -A 90° 180° 270° 360° Offset Angl e Figure 5 Offset and Amplitude Definition Preliminary Data Sheet 17 V 0.9, 2007-05 TLE5010 Draft Amplitude Definition The amplitude is defined as half difference between the signed maximum and minimum values of the idealized (fitted) sine or cosine wave. Electrical and Magnetic Parameters X MAX – X MIN A X = -------------------------------AY Offset Definition The offset of the X and Y signals is defined as the mean value between the signed maximum and minimum values of the idealized (fitted) sine or cosine wave. 2 Y MAX – Y MIN = -------------------------------2 OX OY Temperature dependent behavior X MAX + X MIN --------------------------------= 2 Y MAX + Y MIN = -------------------------------2 The temperature offset gradients for both channels depend on the value at 25°C. It can be calculated using following linear equations: KT OX = tco_d_x + ( tco_k_x × O X25 ) KT OY = tco_d_y + ( tco_k_y × O Y25 ) OX25, OY25: Offset values at 25°C in digits. . Table 8 Parameter Offset Temperature Coefficient base Offset Temperature Coefficient gain GMR Temperature Coefficients Symbol Limit Values min. typ. +0.116296 -0.079401 -0.0010147 -0.0010121 max. 1_/_K digits_/_K Unit Notes tco_d_x tco_d_y tco_k_x tco_k_y - Preliminary Data Sheet 18 V 0.9, 2007-05 TLE5010 Draft Orthogonality Definition The corresponding maximum and zero crossing points of the SIN and COS signals are not exactly in a distance of 90°. The difference between X and Y phase is called ’Orthogonality Error’. Electrical and Magnetic Parameters ϕ = ϕX – ϕY jideal = 0° jX : Phase error of X (= cos) Signal jY : Phase error of Y (= sin) Signal 5.4 Calibration GMR Values The end-of-line calibration can be done using following sequence. The conditions are specified in Table 9. • • • • • • Turn magnetic field left and measure X and Y values Calculation of Amplitude, Offset, Phase correction values of left turn Turn further 90° left and 90° back right without measurement Turn magnetic field right and measure X and Y values Calculation of Amplitude, Offset, Phase correction values of right turn Calculation of mean values of Amplitude, Offset, Phase correction values The above gained values have to be stored in a non-volatile memory. They are used for the correction of the read-out X and Y values before the angular calculation. The resulting angular deviation is calculated using above determined parameters. Temperature Measurement The signal amplitude T25 of the temperature measurement path at calibration conditions has to be measured and stored. Calibration Conditions All errors are related to a calibration done using following conditions: Table 9 Parameter Flux density Temperature GMR calibration conditions Symbol Limit Values min. typ. 30 25 max. mT °C Unit Notes BCAL TCAL - BZ = 0 mT Preliminary Data Sheet 19 V 0.9, 2007-05 TLE5010 Draft Electrical and Magnetic Parameters 5.5 5.5.1 Angle Calculation Components of the Output Signals The X and Y signals at the output can be described with following equations: X = A X × cos ( α + ϕ X ) + O X Y = A Y × sin ( α + ϕ Y ) + O Y AX : Amplitude of X (= cos) Signal OX : Offset of X (= cos) Signal ϕX : Phase error of X (= cos) Signal AY : Amplitude of Y (= sin) Signal OY : Offset of Y (= sin) Signal ϕY : Phase error of Y (= sin) Signal 5.5.2 GMR Error Compensation Temperature dependent Offset Value To increase the accuracy, the temperature dependent offset drift can be compensated. The temperature of the chip has to be read out. The Offset values OX and OY have to be multiplied with the Offset temperature coefficient and the temperature value. KT OX O X = O X25 + ------------- × ( T – T 25 ) S T KT OY O Y = O Y25 + ------------- × ( T – T 25 ) S T OX25 , OY25 : Offset value at 25°C in digits T25 : Temperature value at 25°C in digits T : Temperature value in digits ST : Sensitivity of the temperature measurement path, (see chapter “Temperature Measurement” on Page 46). Preliminary Data Sheet 20 V 0.9, 2007-05 TLE5010 Draft Offset Correction After read-out of the X and Y value first the temperature corrected offset value has to be subtracted. Electrical and Magnetic Parameters X 1 = X – OX Y1 = Y – OY Amplitude Normalization Then the X and Y values are normalized using the peak values determined in the calibration. 1 X 2 = ------ X AX Y1 Y 2 = -----AY Non-Orthogonality Correction The influence of the non-orthogonality can be compensated using following equation. Only the Y channel has to be corrected. Y 2 – X 2 × sin ( – ϕ ) Y 3 = ------------------------------------------ cos ( – ϕ ) Resulting Angle After correction of all errors, the resulting angle can be calculated using the arctan function1). Y3 α = arc tan  ------ – ϕ X  X 2 1) µC-function “arctan2(Y3,X2)” to resolve 360° Preliminary Data Sheet 21 V 0.9, 2007-05 TLE5010 Draft Electrical and Magnetic Parameters 5.6 GMR Parameters after Calibration After calibration under the conditions specified in Table 9 "GMR calibration conditions" on Page 19, the sensor has following remaining error: The error value refers to BZ = 0 mT and operating conditions given in Table 3 "Operating Range ( - 40°C < TJ < 150°C )" on Page 14. Table 10 Parameter GMR parameter with temperature dependent offset compensation Symbol Limit Values min. typ. 1) Unit Notes max. 2,0 ° 2) 3) Overall Error 1) 2) 3) - 0.7 At 25°C, B=30mT incl. hysteresis error At 0h Preliminary Data Sheet 22 V 0.9, 2007-05 TLE5010 Draft Signal Processing 6 Table 11 Parameter Signal Processing Signal Processing Symbol Limit Values min. typ. 4.9 19.6 1) Unit max. kHz Notes FIR_BYP=0 FIR_BYP=1 Internal Cutoff Frequency (-3dB) of sin or cos Value Update Time of sin or cos Value2) Settle Time 3) fCut-Off - tupd - 81,9 20,5 163,8 41,0 - 23230 µs FIR_BYP=0 FIR_BYP=1 FIR_BYP=0 FIR_BYP=1 tsettle ADCPk - Peak ADC Output value digits signed 16 bit integer (2s complement) 4) 5) 6) 1) 2) For 4 Mhz input frequency tupd = 8192 / (25 x fCLK) for FIR_BYP = 0 tupd = 8192 / (100 x fCLK) for FIR_BYP = 1 tsettle = 2 x tupd , after change of ADC input source Output values are valid up to this limit. Above it, corrupted results may occur due to non-linearity of the ADC. The internal quantization is typically 5.166 µV per digit. Correspond to max. GMR output value. 3) 4) 5) 6) Preliminary Data Sheet 23 V 0.9, 2007-05 TLE5010 Draft Clock Supply (CLK Timing Definition) 7 Clock Supply (CLK Timing Definition) The clock signal input “CLK” must fulfill certain requirements which are described in the following: • The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse width and must be spike filtered. • The duty cycle factor should be 0.5 but can deviate to the values limited by tCLKh(f_min) and tCLKl(f_min). • The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is generated automatically. tCLK tCLKh tCLKl VH VL t Figure 6 CLK Timing Definition Table 12 Parameter CLK Timing Specification Symbol Limit Values min. typ. 4.00 50 100 25 40 max. 4.2 70 20 20 MHz % ns ns MHz MHz ns from VL to VH from VH to VL 3.9 30 Unit Notes fCLK CLK Duty Cycle 1) CLKDUTY CLK rise time tCLKr CLK fall time tCLKf PLL Frequency fPLL Digital Clock fDIG Digital Clock Periode tDIG Input Frequency 1) fCLK * 25 ( 25 / 4 ) * fCLK 4 / (25 * fCLK) Minimum duty cycle factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min) = 1 / fCLK(f_min) Maximum duty cycle factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max) = tCLK(f_min) - tCLKl(min) Preliminary Data Sheet 24 V 0.9, 2007-05 TLE5010 Draft Synchronous Serial Communication Interface (SSC) 8 Synchronous Serial Communication Interface (SSC) The 3 pin synchronous serial interface (SSC) has a bidirectional data line (open drain), serial clock signal and chip select. It is designed to communicate with a micro controller with bidirectional SSC interface supporting Open Drain. Other micro controllers may require an external NPN transistor. This allows communication with SPI compatible devices. µC (SSC Master) Shift Register DATA *) typ. 1k Ω *) TLE 501x (SSC Slave) DATA Shift Register SCK *) SCK *) CS Clock Generator Figure 7 CS *) optional , e.g. 100 Ω SSC Half-Duplex Configuration for µC with Open Drain support µC (SSC Master) Shift Register MRST MTSR optional typ. 1kΩ *) *) DATA TLE 501x (SSC Slave) Shift Register *) SCK *) CS *) optional , e.g. 100 Ω SCK CS Clock Generator Figure 8 SSC Half-Duplex Configuration for µC without Open Drain support Preliminary Data Sheet 25 V 0.9, 2007-05 TLE5010 Draft Synchronous Serial Communication Interface (SSC) 8.1 SSC Timing Definition SSC Timing Diagram tSCKp tCSs CS SCK tSCKh tSCKl tCSh tCSoff VH VL VH VL VH VL DATA tDATr tDATw Figure 9 SSC Timing Definition • SSC Inactive Time ( CSoff ) The SSC inactive time defines the delay, before the TLE5010 can be selected again after a transfer. The TLE5010 reacts only to one command after SSC inactive time. Then the SSC Interface of the TLE5010 is disabled until the next SSC Inactive Time is performed. • DATA Write Time ( tDATW ) During this time the TLE5010 changes the data line, thus the data are invalid. The DATA Write Time values are defined without pull-up resistor. • Pull-up Time Value ( tPU ) The value in Table 13 "SSC Timing Specification" on Page 27 is estimated with 60 ns. • Chip Select Off time ( tCSOFF ) Preliminary Data Sheet 26 V 0.9, 2007-05 TLE5010 Draft Table 13 Parameter SSC Baud Rate CS Setup Time Synchronous Serial Communication Interface (SSC) SSC Timing Specification 1) Symbol Limit Values min. typ. max. 2.0 2.12) 7*tDIG+10 7*tDIG+10 7*tDIG+50 + tPU 30 4) ns MBit / s ns ns ns ns ns ns SSC_FILT = 0 SSC_FILT = 1 SSC inactive time Unit Notes fSSC - tCSs CS Hold Time tCSh CSoff tCSoff SCK High tSCKh SCK Low tSCKl DATA Read Time tDATr (Data Valid Time) DATA Write Time (Data Valid Time) 3) 3*tDIG+10 5*tDIG+10 10*tDIG 5*tDIG 5*tDIG 6*tDIG-10 5*tDIG-10 - tDATw 6*tDIG+25 - DATA slope 1) 2) 3) 4) 5) tDATs - 20 ns Falling edge 5) Timings have to be calculated acc. Table 12 "CLK Timing Specification" on Page 24. fCLK/2, synchronized to fCLK if fCLK = fCLK(max) tPU is the time generated by the pull-up resistor Not tested. Internal slope control of falling edge for data bit transition from VH to VL. Preliminary Data Sheet 27 V 0.9, 2007-05 TLE5010 Draft Synchronous Serial Communication Interface (SSC) t SCKl MIN t SCKh SCK t DATw MIN S SC_FILT=0 t DATw MAX Wr tPU Earliest sample timepoint t DATr MIN t DATr MAX Rd SCK t DATw MIN t DATw MAX Wr tDATr MIN tPU SSC_FILT=1 Earliest sample timepoint of second sample from 2 of 3 filt er t DATr MAX Rd Figure 10 Note: SSC Interface Timing Details with worst-case specified Timing – The read window includes the sampling of the data bit. – For SSC_FILT = 1, the 2-of-3 selection is already regarded. Only the 2 last data values have to be equal. – For SSC_FILT = 0 only one sample point is selected. Preliminary Data Sheet 28 V 0.9, 2007-05 TLE5010 Draft Synchronous Serial Communication Interface (SSC) The margin time in following table is the time between write access to the SSC Data Line and the earliest possible sample read of the TLE5010 itself for read back. It is useful to have a maximum distance between WRITE and subsequent READ. This ensures a reliable read back of the written data for the Slave-Active Byte generation. Table 14 Maximum Pull-up Time Margin with worst-case specified Timing SSC_TIMING don’t care Min. tPU Margin 1) 90 50 Unit ns Comment SSC_FILT 0 1 1) Calculation: Margin=tSCKl(min)+tDATwMAX -(tPU)-tDATrMIN.For Margin Slave Active Byte: 1111_1110 Preliminary Data Sheet 43 V 0.9, 2007-05 TLE5010 Draft Example: Update X and Y and set ADC-Test Mode Command 00000001 Data 00000101 CRC (init all ‘0’) 00000000 Data Communication via SSC ----------------------------------xor 11111111 -------=11111110.0 . .A xor 10001110.1 . . --------.. . = 01110000.10 . .B xor 1000111.01 . . -------.-. . = 0110111.110 . .C xor 100011.101 . . ------.--. . = 10100.0110 . .D xor 10001.1101 . . -----.---. . = 00101.101101 . .E xor 100.011101 . . ---.------ . . = 001.11000001. .F xor 1.00011101. . ---.------ . . =.11011100.0 .G xor.10001110.1 . .--------.. = 1010010.10 .H xor 1000111.01 . -------.. = 10101.1100 .I xor 10001.1101 . ----.----. = 100.000100 .J xor 100.011101 . ---.------ . =01100100. Remainder 10011011 inverted Remainder Transmitted Sequence: Command Data CRC 00000001 00000101 10011011 Preliminary Data Sheet 44 V 0.9, 2007-05 TLE5010 Draft Test Structures 11 Test Structures Two different test signal structures are implemented in the TLE5010. These are: • Functional angle test. In this case, well-knows signals feed the ADCs. • Temperature measurement. This is useful to read out the chip temperature for compensation purposes. 11.1 Functional Angle Tests It is possible to feed the ADCs with appropriate values to simulate a certain magnetposition and other GMR effects. The values are generated with resistors on the chip. Following X / Y ADC values can be programmed: • 4 points, circle amplitude = 70.7% (0°, 90°, 180°, 270°) • 8 points, circle amplitude = 100.0% (0°, 45°, 90°, 135°,180°, 225°, 270°, 315°) • 8 points, circle amplitude = 122.1% (35.3°, 54.7°, 125.3°, 144.7°, 215.3°, 234.7°, 305.3°, 324.7°) • 4 points, circle amplitude = 141.4% (45°, 135°, 225°, 315°) Note: The 100% values correspond to typically 21700 digits and a voltage of ~ 110 mV. Table 17 Register Bits 000 001 010 011 100 101 110 111 1) Functional Angle Test X / Y Values (decimal) min. -400 14800 20700 typ. 0 15500 21700 32767 0 -15500 -21700 -32768 max. 400 16200 22700 400 -16200 -22700 1) -400 -14800 -20700 Not allowed to use. Preliminary Data Sheet 45 V 0.9, 2007-05 TLE5010 Draft ADC Test Vectors Test Structures Y 122.1% 141.4% 0% 100.0% 70.7% X Figure 14 ADC Test Vectors 11.2 Temperature Measurement An internal bandgap voltage can be used to measure the temperature on the chip. This may be used to compensate temperature dependent errors. The temperature value is sent out instead of the X value. Table 18 Parameter Value at -40°C Value at 25°C Value at 150°C Temperature Sensitivity 1) Temperature Measurement Symbol Limit Values min. typ. +5775 -188.75 max. +22000 digits +9000 digits digits dig / K 1) Unit Notes T-40 T25 T150 ST +2550 - -22000 - Should be used for temperature compensation of offset errors Preliminary Data Sheet 46 V 0.9, 2007-05 TLE5010 Draft Test Structures 11.3 Angle Test and Temperature Measurement Timing The angle test and the temperature readout is based on the same mechanism. In the Normal Mode, the output path is linked to the angle test or temperature measurement unit until the mode is terminated. < tupd tupd FSYNC (reset) FCNT[4] ADC&Filter X[16],Y[16] Buffer1 ANGT_EN or TEMP_EN Update GMR_OFF 4 Val_G4 Val_G3 5 Val_G5 0 Val_A0 1 Val_A1 Val_A0 tupd tupd < tupd tupd tupd tupd 2 Val_A2 0 Val_G0 1 Val_G1 Val_G0 2 Val_G2 Val_G1 Val_G4 Val_A1 useful No GMR signal available Figure 15 Measurement in Normal Mode In the Automatic Mode, the signal is automatically switched back to GMR measurement after the read-out of one value. < tupd tupd FSYNC (reset) FCNT[4] ADC&Filter X[16],Y[16] Buffer1 ANGT_EN or TEMP_EN Update GMR_OFF No GMR signal available automatic! 4 Val_G4 Val_G3 5 Val_G5 0 Val_A0 1 Val_A1 Val_A0 tupd tupd tupd Updated FCNT=2 0 Val_G0 Val_A1 1 Val_G1 Val_G0 2 Val_G2 Val_G1 tupd tupd Val_G4 Figure 16 Measurement in Automatic Mode 47 V 0.9, 2007-05 Preliminary Data Sheet TLE5010 Draft Overvoltage Comparators 12 Overvoltage Comparators Various comparators monitor the voltage in order to ensure a error free operation. The overvoltages must be active for at least tDEL to set the test comparator bits in the SSC Interface registers. This works as digital spike suppression. Table 19 Parameter Overvoltage Detection Test Comparators Symbol Limit Values min. typ. max. V V V V V V µs 2.80 2.80 2.80 6.5 0.54 0.48 10 - Unit Notes VOVG VOVA VOVD VDD Overvoltage VDDOV GND - Off Voltage VGNDoff VDD - Off Voltage VVDDoff Spike filter Delay VGND_OFF = VGND - VTST1 VVDD_off = VCLK - VDD or VSCK - VDD The error condition has to be longer than this value (min. 256 clocks of fDIG) tDEL 12.1 Internal Supply Voltage Comparators Every voltage regulator has an overvoltage comparator to detect a malfunction. If the nominal output voltage of 2.5 V is larger than VOVG, VOVA and VOVD, then this overvoltage comparator is activated. It sets the VRx_OV bit. . VDDA REF VDD VRG VRA VRD GND + GND 10µs Spike Filter xxx_OV Figure 17 OV Comparator 12.2 VDD Overvoltage Detection This comparator (see Figure 17) monitors the external supply voltage at the VDD pin. It activates the STAT_VR bit. Preliminary Data Sheet 48 V 0.9, 2007-05 TLE5010 Draft Overvoltage Comparators 12.3 GND - Off Comparator This comparator is used to detect a voltage difference between the GND pin and TST1 (which must be soldered to GND in the application). It activates the STAT_VR bit. This circuit can detect a disconnection of the Supply GND Pin. . VDD VGNDoff TST1 +dV VDDA + GND GND 10µs Spike Filter GND_OFF Figure 18 GND - Off Comparator 12.4 VDD - Off Comparator This comparator detects a disconnection of the VDD pin supply voltage. In this case the TLE5010 is supplied by the SCK, CLK and CS input pins via the ESD structures. It activates the STAT_VR bit. The retriggerable analog monoflop is necessary because of the not static signal of the CLK and SCK signals. This comparator is also activated, if spikes on CLK or SCK achieve the condition: (VCLK - VDD) > VVDDoff or (VSCK - VDD) > VVDDoff . VDDA VDD VVDDoff C LK SCK GND -dV + GND 1µs Mono Flop 10µs Spike Filter VDD _OFF Figure 19 VDD - Off Comparator Preliminary Data Sheet 49 V 0.9, 2007-05 TLE5010 Draft Typical Application Circuit 13 Typical Application Circuit The application circuit shows the µC version with open drain capabilities. 12V Voltage Regulator VDD SSC CLK DATA_o each 100R 1k VDD 100R CAN RX CAN TX CAN Tranceiver CAN µController Master DATA_i SCK CSQ GMR-Sensor TLE5010 GND 100nF GND Figure 20 Application Circuit 13.1 Angle Sensor System A complete system may consist out of one TLE5010 and a micro controller. The second TLE5010 can be redundand in order to increase the system reliability. The µC should contain a CORDIC coprocessor for fast angle calculations and a flash memory for the calibration data storage. Preliminary Data Sheet 50 V 0.9, 2007-05 TLE5010 Draft Package Information 14 14.1 Table 20 Parameter Package Information Package Parameters Package Parameters Symbol Limit Values min. typ. 150 MSL 3 Cu194 / OLIN Unit max. 200 75 85 K/W K/W K/W Notes Junction to Air 1) Junction to Case Junction to Lead 260°C Fe 2.35%, P 0.03%, Cu 97.5%, Zn0.12% stamped > 7 µm Halogen Free Thermal Resistance RthJA - RthJC RthJL Soldering Moisture Level Lead frame Plating Molding Compound 1) Sn 100% EME-G700 according to Jedec JESD51-7 Preliminary Data Sheet 51 V 0.9, 2007-05 TLE5010 Draft Package Outline PG-DSO-8 Package Information 0.1 MIN. STAND OFF A 1.65 ±0.1 0.33 ±0.08 x 45˚ 1.22 ±0.18 D 4.9 ±0.08 3.9 ±0.11) E 0.2 -0.01 +0.05 1.27 0.41 +0.1 -0.05 2.53 (1.5) C 0.1 8x D C 8x SEATING PLANE 0.64 ±0.25 6 ±0.2 0.2 M 0.4 B 3 x 1.27 = 3.81 1.95 0.32 MIN. Detail A ø0.6 Sensitive Area 2) 3) Center of Sensitive Area Pin 1 Index Marking 8 5 1 4 B 5.06 ±0.1 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Max. 3˚ tilt of sensitive area to preference "E" 3) Independent from dimensions 1.65 and 1.22 GPS19032 Figure 21 Package Outline PG-DSO-8 Preliminary Data Sheet 0.4 A 52 V 0.9, 2007-05 8˚MAX. A TLE5010 Draft Footprint PG-DSO-8 Package Information 1.31 0.65 5.69 1.27 Figure 22 Packing Footprint PG-DSO-8 8 0.3 12 ±0.3 5.2 6.4 1.75 2.1 Figure 23 Tape and Reel Preliminary Data Sheet 53 V 0.9, 2007-05 TLE5010 Draft Marking Package Information Top view Bottom view 1 23456 G 0624 Pin 1 marking Type code Date code (Year/Month) Green Package 111111 11111 111111 Pin 1 Production Code HLGM1227 Figure 24 Marking Processing For processing recommendations please refer Infineon’s “Notes on Processing” Preliminary Data Sheet 54 V 0.9, 2007-05 TLE5010 Draft Package Information Preliminary Data Sheet 55 V 0.9, 2007-05 www.infineon.com Published by Infineon Technologies AG