TLE5012_10

Angle Sensor GMR-Based Angular Sensor for Rotor-Position Sensing TLE5012 TLE5012-E0318 TLE5012-E0742 Data Sheet V 1.0, 2010-11 Final Sensors Edition 2010-11 Published by Infineon Technologies AG 81726 Munich, Germany © 2011 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TLE5012 TLE5012 GMR-Based Angular Sensor Revision History: 2010-11, V 1.0 Previous Version: Page Major changes since last revision general correction of typing errors We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sensors@infineon.com Final Data Sheet 3 V 1.0, 2010-11 TLE5012 Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 1.1 1.2 1.3 2 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.5 3.5.1 3.5.1.1 3.5.1.2 3.5.1.3 3.5.1.3.1 3.5.1.4 3.5.2 3.5.3 3.5.4 3.6 3.6.1 3.7 3.7.1 3.7.2 3.7.3 3.7.4 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD-ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Signal Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Communication (SSC) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLE5012 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communication Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse-Width Modulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Overvoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 8 9 9 10 10 12 12 13 13 13 13 13 14 14 14 15 15 18 18 20 20 21 22 23 23 26 27 27 28 30 33 34 50 51 53 55 57 57 59 59 59 59 60 Final Data Sheet V 1.0, 2010-11 TLE5012 Table of Contents 4 4.1 4.2 4.3 4.4 4.5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 61 62 62 63 Final Data Sheet 5 V 1.0, 2010-11 TLE5012 List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Sensitive bridges of the GMR sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Theoretical output of the GMR sensor bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLE5012 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRO-SILTM Logo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application circuit for TLE5012 with SSC and PWM Interface (using internal CLK). . . . . . . . . . . . Application circuit for TLE5012 with HS Mode (using internal CLK). . . . . . . . . . . . . . . . . . . . . . . . Application circuit for TLE5012 with SSC Interface and IIF (using external CLK) . . . . . . . . . . . . . Application circuit for TLE5012 with only PWM Interface (using internal CLK) . . . . . . . . . . . . . . . Operating magnetic induction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset and amplitude definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLE5012 signal path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delay of sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External CLK timing definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC configuration in sensor-slave mode with push-pull outputs (high speed application). . . . . . . SSC configuration in sensor-slave mode and open drain (safe bus systems) . . . . . . . . . . . . . . . . SSC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC data transfer (data-read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC data transfer (data-write example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC bit ordering (read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast CRC polynomial division circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Example for a PWM Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Interface with Step/Direction mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Interface Protocol with symbolic illustration of SPI Interface . . . . . . . . . . . . . . . . . . . IIF index coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC test vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OV comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - Off comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - Off comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-DSO-8 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Position of sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint of PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 12 13 14 15 16 16 17 19 22 24 25 26 27 28 28 30 30 32 32 51 53 55 55 56 56 58 59 60 60 61 62 62 62 Final Data Sheet 6 V 1.0, 2010-11 TLE5012 List of Tables List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical parameters for 4.5V < VDD < 5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical parameters for 3.0V < VDD < 3.6V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic GMR parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC push-pull timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC open-drain timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of the Command Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of the Safety Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC command to read the angle value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC command to read angle speed and angle revolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC command to change Interface Mode2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC command to enable ADC test vector check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of Write Data for some different test vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 18 18 20 20 21 21 22 23 24 26 27 28 29 30 31 31 33 50 50 50 51 53 56 57 58 58 59 61 Final Data Sheet 7 V 1.0, 2010-11 TLE5012 1 Product Description 1.1 Overview The TLE5012 is a 360° angle sensor that detects the orientation of a magnetic field by measuring sine and cosine angle components with monolithic integrated Giant Magneto Resistance (iGMR) elements. Highly precise angle values are maintained at various temperatures throughout the device’s lifetime using an internal autocalibration algorithm. Data communications are accomplished with a bi-directional Synchronous Serial (SSC)-Interface that is Serial Peripheral Interface (SPI)-compatible. The absolute angle value and other values are transmitted via SSC or via a Pulse-Width Modulation (PWM) protocol. The sine and cosine raw values can also be read out. These raw signals are digitally processed internally to calculate the angle orientation of the magnetic field (magnet). The TLE5012 is a precalibrated sensor. The calibration parameters are stored in laser fuses. At start-up, the values of the fuses are written into flip-flops, where these values can be changed by the application-specific parameters. The TLE5012-E0318 and TLE5012-E0742 are especially configured in a Hall-Switch emulation mode for motors with three or seven pole pairs. Online diagnostic functions are provided to ensure reliable operation. Product Type TLE5012 TLE5012-E0318 TLE5012-E0742 Final Data Sheet Marking 5012 5012E03 5012E07 8 Ordering Code SP000477068 SP000611246 SP000611250 Package PG-DSO-8 PG-DSO-8 PG-DSO-8 V 1.0, 2010-11 TLE5012 Product Description 1.2 • • • • • • • • • • • • • • Features GMR-based principle Integrated magnetic field sensing for angle measurement Fully calibrated 0 - 360° angle measurement with revolution counter and angle speed measurement Two separate highly accurate single-bit SD-ADCs 15-bit representation of absolute angle value on the output (resolution of 0.01°) 16-bit representation of sine/cosine values on the interface Max. 1.0° angle error over lifetime and temperature with activated auto-calibration Bi-directional SSC Interface up to 8 Mbit/s Supports Safety Integrity Level (SIL) with diagnostic functions and status information Interfaces: SSC, PWM, Incremental Interface (IIF), Hall-Switch Mode (HSM) 0.25-µm CMOS technology Automotive qualified: -40°C to 150°C (junction temperature) ESD > 4 kV (HBM) RoHS-compliant (Pb-free package) 1.3 Typical Applications The TLE5012 GMR-Based Angular Sensor is designed for angular position sensing in automotive applications, such as: • • • • Electrical commutated motor (e.g. used in Electric Power Steering (EPS)) Rotary switch Steering angle General angular sensing Final Data Sheet 9 V 1.0, 2010-11 TLE5012 Functional Description 2 Functional Description 2.1 General The GMR sensor uses vertical integration. This means that the GMR-sensitive areas are integrated above the logic portion of the TLE5012 device. These GMR elements change their resistance depending on the direction of the magnetic field. Four individual GMR elements are connected to one Wheatstone sensor bridge. These GMR elements sense one of two components of the applied magnetic field: • • X component, Vx (cosine) or the Y component, Vy (sine) The advantage of a full-bridge structure is that the amplitude of the GMR signal is doubled and temperature effects cancel out each other. GMR Resistors S 0° VX VY N ADCX + ADCX - GND ADCY+ ADCY- VDD 90° Figure 1 Sensitive bridges of the GMR sensor Note: In Figure 1, the arrows in the resistors represent the magnetic direction which is fixed in the Reference Layer. If the external magnetic field is parallel to the direction of the Reference Layer, the resistance is minimal. If they are anti-parallel, resistance is maximal. The output signal of each bridge is only unambiguous over 180° between two maxima. Therefore two bridges are oriented orthogonally to each other to measure 360°. With the trigonometric function ARCTAN, the true 360° angle value can be calculated, based on the relationship of X and Y signals. Because only the relative values influence the result, the absolute magnitude of the two signals is of minor importance. Therefore, it is possible to compensate for most external influences on the amplitudes. Final Data Sheet 10 V 1.0, 2010-11 TLE5012 Functional Description Y Component (SIN) VY VX V VX (COS) X Component (COS) 0° 90° 180° 270° 360° Angle α VY (SIN) Figure 2 Theoretical output of the GMR sensor bridges Final Data Sheet 11 V 1.0, 2010-11 TLE5012 Functional Description 2.2 Pin Configuration 8 7 6 5 Center of Sensitive Area 1 Figure 3 2 3 4 Pin configuration (top view) 2.3 Pin Description Table 1 Pin No. 1 2 3 4 Pin description Symbol CLK SCK CSQ DATA (DATA / IIF_Index / HS3) IFA (IIF_A / HS1 / PWM) VDD GND IFB (IIF_B / HS2) In/Out I I I I/O Function External Clock (selection of interface)1) SSC Clock SSC Chip Select Interface DATA: SSC DATA; IIF Index; Hall Switch signal 3 2) Interface A: IIF phase A; Hall Switch signal 1; PWM 2) Supply voltage Ground Interface B: IIF phase B; Hall Switch signal 2 2) 5 O 6 7 8 O 1) Connected to VDD --> Incremental Interface is used; connected to GND--> Interface in IF_MD is used; sampling within Power-On Time; interface change within operation via SSC IF possible 2) Depends on external circuit of CLK and IF_MD setting Final Data Sheet 12 V 1.0, 2010-11 TLE5012 Functional Description 2.4 Block Diagram TLE5012 Osc VRG VRA VRD PLL X GMR SDADC Digital Signal Processing Unit CCU Cordic Fuses Incremental IF PWM HSM VDD CLK CSQ SSC Interface SCK DATA IFA IFB GND Y GMR Temp SDADC SDADC Figure 4 TLE5012 block diagram 2.5 Functional Block Description 2.5.1 • • • Internal Power Supply The internal stages of the TLE5012 have different voltage regulators. GMR Voltage Regulator VRG Analog Voltage Regulator VRA Digital Voltage Regulator VRD (derived from VRA) These regulators are directly connected to the supply voltage VDD. 2.5.2 Oscillator and PLL The internal frequency oscillator feeds the Phase-Locked Loop (PLL). Therefore the external CLocK (CLK) can also be used. 2.5.3 SD-ADCs The SD-ADCs transform the analog GMR voltages and temperature voltage into the digital domain. Final Data Sheet 13 V 1.0, 2010-11 TLE5012 Functional Description 2.5.4 • • • Digital Signal Processing Unit The Digital Signal Processing Unit (DSPU) contains the: Capture Compare Unit (CCU), which is used to generate the PWM signal COordinate Rotation DIgital Computer (CORDIC), which contains the trigonometric function for angle calculation Fuses, which contain the calibration parameters 2.5.5 • • • • Interfaces Different Interfaces can be selected: SSC Interface PWM Incremental Interface Hall Switch Mode 2.5.6 Safety Features The TLE5012 offers a multiplicity of safety features to support Safety Integrity Level (SIL). Sensors with this performance are identified by the following logo: Figure 5 • • • • • • PRO-SILTM Logo Safety features are: Test vectors switchable to ADC input Inversion or combination of filter input streams Data transmission check via 8-bit Cyclic Redundancy Check (CRC) Self-test routines Two independent active interfaces possible Overvoltage and undervoltage detection Disclaimer PRO-SIL™ is a Registered Trademark of Infineon Technologies AG. The PRO-SIL™ Trademark designates Infineon products which contain SIL Supporting Features. SIL Supporting Features are intended to support the overall System Design to reach the desired SIL (according to IEC61508) or A-SIL (according to ISO26262) level for the high efficiency Safety System. SIL respectively A-SIL certification for such a system has to be reached on system level by the System Responsible at an accredited Certification Authority. SIL stands for Safety Integrity Level (according to IEC 61508) A-SIL stands for Automotive-Safety Integrity Level (according to ISO 26262) Final Data Sheet 14 V 1.0, 2010-11 TLE5012 Specifications 3 Specifications 3.1 Application Circuit The application circuits shown in Figure 6, Figure 7, Figure 8 and Figure 9 show the various communication possibilities of the TLE5012. TLE5012 Osc VRG VRA VRD PLL X GMR Y GMR SDADC SDADC CSQ CLK 100n 1 kΩ VDD (3.0 – 5.5V) Digital Signal Processing Unit CCU Cordic Fuses SSC Interface SCK *) SSC DATA IFA (PWM) Incremental IF PWM HSM 10 kΩ PWM IFB could remain open or connected via 10 kΩ r esistor to GND. Temp SDADC IFB GND *) recommended , e.g. 470 Ω Figure 6 Application circuit for TLE5012 with SSC and PWM Interface (using internal CLK) Figure 6 shows a basic block diagram of the TLE5012 with PWM Interface. This interface is selectable by connecting CLK to GND. In addition to the PWM, the SSC Interface could be used. Within the SSC Interface, the PWM Mode is selectable between push-pull and open drain. Final Data Sheet 15 V 1.0, 2010-11 TLE5012 Specifications TLE5012 Osc VRG VRA VRD PLL X GMR Y GMR SDADC SDADC CSQ CLK *) *) *) 100n VDD (3.0 – 5.5V) Digital Signal Processing Unit CCU Cordic Fuses SSC Interface SCK DATA (HS3) IFA (HS1) Incremental IF PWM HSM Temp SDADC IFB (HS2) GND *) recommended , e.g. 2. 2 kΩ Figure 7 Application circuit for TLE5012 with HS Mode (using internal CLK) Figure 7 shows a basic block-diagram of the TLE5012 in the Hall Switch Mode. This interface is selectable by connecting CLK to GND and CSQ to VDD. In addition to the HSM, the SSC Interface can be used by pulling CSQ to GND. Within the SSC Interface, the HSM is selectable between push-pull and open drain. VDD (3.0 – 5.5V) Osc VRG VRA VRD PLL X GMR Y GMR SDADC SDADC CSQ CLK 100 n **) ***) TLE5012 µC PLL Digital Signal Processing Unit CCU Cordic Fuses SSC Interface SCK *) SSC DATA IFA (IIF_A) Incremental IF PWM HSM Temp SDADC CCU IFB (IIF_B) GND *) recommended , e.g. 470 Ω **) connected to V DD for use of internal CLK ***) connected to microcontroller for use of external CLK Figure 8 Application circuit for TLE5012 with SSC Interface and IIF (using external CLK) Figure 8 shows a basic block diagram of an angle sensor system using a TLE5012 and a microcontroller for rotorpositioning applications. The interface configuration depicted is needed for high-speed applications such as electrical commutated motor drives. It is possible to connect the TLE5012 to a microcontroller via the Incremental Interface, and for safety reasons also via the SSC Interface. Final Data Sheet 16 V 1.0, 2010-11 TLE5012 Specifications The TLE5012 Exxxx can be configured with PWM only (Figure 9). This is not possible with the Standard TLE5012 type.1) TLE5012 Osc VRG VRA VRD PLL X GMR Y GMR SDADC SDADC CSQ CLK 100n 1 kΩ VDD (3.0 – 5.5V) Digital Signal Processing Unit CCU Cordic Fuses SSC Interface SCK 10 kΩ DATA and IFB could remain open or connected via 10 kΩ r esistor to GND . DATA IFA (PWM) Incremental IF PWM HSM 10 kΩ Temp SDADC IFB GND Figure 9 Application circuit for TLE5012 with only PWM Interface (using internal CLK) 1) For more information, please contact Infineon Final Data Sheet 17 V 1.0, 2010-11 TLE5012 Specifications 3.2 Absolute Maximum Ratings Table 2 Parameter Absolute maximum ratings Symbol Min. -0.5 -0.5 -40 -40 Values Typ. Max. 6.5 6.5 150 150 │125│ │100│ 150 V V °C °C mT mT °C For 1000 h not additive Max. 5 min @ TA = 25°C Max. 5 h @ TA = 25°C Without magnetic field Max. 40 h/lifetime Additionally VDD + 0.5 V may not be exceeded Unit Note / Test Condition Voltage on VDD pin with respect to VDD ground (VSS) Voltage on any pin with respect to VIN ground (VSS) Junction temperature Magnetic field induction Storage temperature TJ B TST Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the device. 3.3 Operating Range The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5012. All parameters specified in the following sections refer to these operating conditions, unless otherwise noted. Table 3 is valid for -40°C < TJ < 150°C unless otherwise noted. Table 3 Parameter Supply voltage Output current (DATA-Pad) Operating range Symbol Min. VDD IQ 3.0 Output current (IFA / IFB-Pad) IQ Input voltage VIN -0.3 Values Typ. 5.0 Max. 5.5 -25 -5 -0.4 -15 -5 5.5 V mA mA mA mA mA V 1) Unit Note / Test Condition PAD_DRV =’0x’, sink current2)3) PAD_DRV =’10’, sink current2)3) PAD_DRV =’11’, sink current2)3) PAD_DRV =’0x’, sink current2)3) PAD_DRV =’1x’, sink current2)3) VDD + 0.3 V may not be exceeded Final Data Sheet 18 V 1.0, 2010-11 TLE5012 Specifications Table 3 Parameter Magnetic induction at TA = 25°C Operating range (cont’d) Symbol Min. 4)5) Values Typ. Max. 50 60 70 30 360 30 30 30 25 0 Unit Note / Test Condition mT mT mT mT ° -40°C < TJ < 150°C -40°C < TJ < 100°C -40°C < TJ < 85°C Additional angle error of 0.1° 6) BXY BXY BXY BXY Ang Expanded magnetic induction at TA = 25°C 4)5) Angle range 1) 2) 3) 4) 5) 6) Directly blocked with 100-nF ceramic capacitor Max. current to GND over open-drain output At VDD = 5V Values refer to an homogenous magnetic field (BXY) without vertical magnetic induction (BZ = 0mT) See Figure 10 0h The field strength of a magnet can be selected within the colored area in Figure 10. By limitation of the junction temperature, a higher magnetic field can be applied. In case of a maximum temperature TJ=100°C a magnet with up to 60mT at TA=25°C is allowed. Figure 10 Magnet performance (ambient temperature) Note: The thermal resistances listed in Table 29 “Package parameters” on Page 61 must be used to calculate the corresponding ambient temperature. Final Data Sheet 19 V 1.0, 2010-11 TLE5012 Specifications Calculation of the Junction Temperature The total power dissipation PTOT of the chip increases its temperature above the ambient temperature. The power multiplied by the total thermal resistance RthJA (Junction to Ambient) leads to the final junction temperature. RthJA is the sum of the addition of the values of the two components Junction to Case and Case to Ambient. RthJA = RthJC + RthCA TJ = TA + ΔT ΔT = RthJA × PTOT = RthJA × (VDD × I DD + VOUT × I OUT ) Example (assuming no load on Vout): (IDD, I OUT > 0, if direction is into IC) (1) V DD = 5V I DD = 14 mA ⎡K Δ T = 150 ⎢ ⎣W ⎤ ⎥ × (5[V ]× 0 .014 [A ] + 0[VA ]) = 10 .5 K ⎦ (2) For molded sensors, the calculation with RthJC is more appropriate. 3.4 Characteristics 3.4.1 Electrical Parameters The indicated electrical parameters apply to the full operating range, unless otherwise specified. The typical values correspond to a supply voltage VDD = 5.0 V and 25 °C, unless individually specified. All other values correspond to -40 °C < TJ < 150°C. Table 4 Parameter Supply current POR level POR hysteresis Pull-Up current Pull-Down current Power-on time 1) Electrical parameters Symbol Min. IDD VPOR VPORhy IPU IPD tPon 2.0 -10 -10 10 10 Values Typ. 14 30 5 Max. 16 2.9 -225 -150 225 150 7 mA V mV µA µA µA µA ms CSQ DATA SCK CLK, IFA, IFB VDD > VDDmin2) Power-On Reset Unit Note / Test Condition 1) Not subject to production test - verified by design/characterization 2) Within “Power-On Time,” write access is not permitted Final Data Sheet 20 V 1.0, 2010-11 TLE5012 Specifications Table 5 Parameter Electrical parameters for 4.5V < VDD < 5.5V Symbol Min. VL5 VH5 VOL5 Values Typ. Max. 0.3 VDD 1 V V V DATA; IQ = - 25 mA (PAD_DRV=’0x’), IQ = - 5 mA (PAD_DRV=’10’), IQ = - 0.4 mA (PAD_DRV=’11’) IFA,IFB; IQ = - 15 mA (PAD_DRV=’0x’), IQ = - 5 mA (PAD_DRV=’1x’) Unit Note / Test Condition Input signal low level Input signal high level Output signal low level 0.7 VDD - - - 1 V Table 6 Parameter Electrical parameters for 3.0V < VDD < 3.6V Symbol Min. VL3 VH3 VOL3 Values Typ. Max. 0.2 VDD 0.9 V V V DATA; IQ = - 15 mA (PAD_DRV=’0x’), IQ = - 3 mA (PAD_DRV=’10’), IQ = - 0.24 mA (PAD_DRV=’11’) IFA,IFB; IQ = - 10 mA (PAD_DRV=’0x’), IQ = - 3 mA (PAD_DRV=’1x’) Unit Note / Test Condition Input signal low level Input signal high level Output signal low level 0.8 VDD - - - 0.9 V 3.4.2 ESD Protection Table 7 Parameter ESD voltage ESD protection Symbol VHBM VSDM Values min. max. ±4.0 ±0.5 kV kV Human Body Model1) Socketed Device Model2) Unit Notes 1) Human Body Model (HBM) according to AEC-Q100-002 2) Socketed Device Model (SDM) according to ESDA/ANSI/ESD SP5.3.2-2008 Final Data Sheet 21 V 1.0, 2010-11 TLE5012 Specifications 3.4.3 GMR Parameters All parameters apply over BXY = 30mT and TA = 25°C, unless otherwise specified. Table 8 Parameter X, Y output range X, Y amplitude 1) X, Y synchronism 2) X, Y offset 3) Basic GMR parameters Symbol Min. RGADC AX, AY k OX, OY Φ X 0, Y 0 6000 3922 87.5 9500 100 Values Typ. Max. ±23230 15781 20620 112.49 +2047 +11.24 +5000 digits digits digits % digits ° digits without magnet 4) operating range 4) Unit Note / Test Condition -2048 0 -11.25 0 -5000 - X, Y orthogonality error X, Y without field 1) 2) 3) 4) See Figure 11 k = 100*(AX/AY) OY=(YMAX + YMIN) / 2; OX = (XMAX + XMIN) / 2 Not subject to production test - verified by design/characterization VY +A 0 Offset 0° 90° 180° 270° 360° Angle -A Figure 11 Offset and amplitude definition Final Data Sheet 22 V 1.0, 2010-11 TLE5012 Specifications 3.4.4 Angle Performance After internal calculation the sensor has a remaining error, as shown in Table 11. The error value refers to BZ = 0mT and the operating conditions given in Table 3 “Operating range” on Page 18. The overall angle error represents the relative angle error. This error describes the deviation from the reference line after zero angle definition. Table 9 Parameter Overall Angle Error (with autocalibration) Angle performance Symbol Min. αErr Values Typ. 0.6 1) Unit ° ° Note / Test Condition including lifetime and temperature drift2)3)4) including temperature drift2)3)5) Max. 1.0 1.6 Overall Angle Error (without auto- αErr calibration) 1) 2) 3) 4) 5) 0.61) At 25°C, B = 30 mT Including hysteresis error, caused by revolution direction change. Only with calibrated GMR-compensation parameters of customer setup; Relative error after zero angle definition. Not subject to production test - verified by design/characterization 0h Autocalibration The autocalibration enables online parameter calculation and therefore reduces the angle error due to temperature drift, lifetime drift, and misalignments. The TLE5012 is a pre-calibrated sensor. After start-up, the parameters out of the laser fuses get loaded into flipflops. The TLE5012 needs more than a full revolution to generate new parameters. The update mode can be chosen within the Interface Mode 2 register (AUTOCAL). The parameters are updated in a smooth way to avoid an angle jump on the output. Therefore only one LSB will be changed within the choosen range or time. The autocalibration is done continuously. AUTOCAL Modes: • • • • 00: No autocalibration 01: Autocalibration Mode 1. Only one LSB to final values within the update time tupd (depending on FIR_MD setting). 10: Autocalibration Mode 2. Only one LSB update over one full revolution. After update of one LSB, the autocalibration will calculate the parameters again. 11: Autocalibration Mode 3. Only one LSB to final values within an angle range of 11.25°. 3.4.5 Signal Processing The signal path of the TLE5012 is depicted in Figure 12. It consists of the GMR bridge, ADC, filter, and angle calculation. Depending on the filter configuration, various total delay times are achieved. In addition to this delay time, the delay time of the interface has to be considered. The delay time leads to an additional angle error at higher speeds. By enabling the prediction, the signal delay time can be reduced (Figure 13). The prediction uses the difference between current and last angle value and calculates the output value by adding this difference to the current value. A linear prediction is thereby achieved. α (t + 1) = 2 ⋅ α (t ) − α (t − 1) (3) Final Data Sheet 23 V 1.0, 2010-11 TLE5012 Specifications TLE5012 Microcontroller tupd X GMR SDADC Filter Angle Calculation Y GMR SDADC Filter IF tadel Figure 12 TLE5012 signal path tdelIF At FIR_MD = 0 only raw values can be read out, due to the more time consuming angle calculation. Table 10 Parameter Update rate at interface Signal processing Symbol Min. tupd Angle delay time3) tadel Angle delay time with prediction3) tadel Angle noise NAngle Values Typ. 21.3 42.7 85.3 170.6 60 80 120 20 5 -40 0.11 0.08 0.05 0.04 Max. 70 95 140 30 20 -20 µs µs µs µs µs µs µs µs µs µs ° ° ° ° FIR_MD = 0 (only raw values)1)2) FIR_MD = 11)2) FIR_MD = 2 (default)1)2) FIR_MD = 31)2) FIR_MD = 11)2) FIR_MD = 21)2) FIR_MD = 31)2) FIR_MD = 1; PREDICT = 1 1)2) Unit Note / Test Condition FIR_MD = 2; PREDICT = 1 1)2) FIR_MD = 3; PREDICT = 1 1)2) FIR_MD = 0, (1 sigma)2) FIR_MD = 1, (1 sigma)2) FIR_MD = 2, (1 sigma)2) (default) FIR_MD = 3, (1 sigma)2) 1) Depends on internal oscillator frequency variation (Section 3.4.6) 2) Not subject to production test - verified by design/characterization 3) Valid at constant rotation speed Final Data Sheet 24 V 1.0, 2010-11 TLE5012 Specifications Angle Magnetic field direction Sensor output With Prediction Without Prediction tadel Figure 13 Delay of sensor output t upd time Final Data Sheet 25 V 1.0, 2010-11 TLE5012 Specifications 3.4.6 • • • Clock Supply (CLK Timing Definition) If the external clock supply is selected, the clock signal input CLK must fulfill certain requirements: The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse width and must be spike filtered. The duty cycle factor should be 0.5 but can deviate to the values limited by tCLKh(f_min) and tCLKl(f_min). The PLL is triggered at the positive edge of the clock; if more than 2 edges are missing, a chip reset is generated automatically. tCLK tCLKh tCLKl VH VL t Figure 14 Table 11 Parameter Input frequency CLK duty cycle CLK rise time CLK fall time Digital clock Internal oscillator frequency 1)2) External CLK timing definition CLK timing specification Symbol Min. fCLK CLKDUTY tCLKr tCLKf fDIG fCLK 3.8 30 22.8 3.8 Values Typ. 4.0 50 24 4.0 Max. 4.2 70 30 30 25.2 4.2 MHz % ns ns MHz MHz From VL to VH3) From VH to VL3) Unit Note / Test Condition 1) Minimum Duty Cycle Factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min)= 1 / fCLK(f_min) 2) Maximum Duty Cycle Factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max)= tCLK(f_min) - tCLKl(min) 3) Not subject to production test - verified by design/characterization Final Data Sheet 26 V 1.0, 2010-11 TLE5012 Specifications 3.5 Interfaces Within the register MOD_3, the driver strength and so the slope for push-pull communication can be varied with the sensor output. The driver strength is specified in Table 3 and the slope fall and rise times in Table 12. Table 12 Parameter Output fall time Output rise time PAD characteristics Symbol Min. tfall, trise Values Typ. Max. 8 28 45 130 15 30 ns ns ns ns ns ns DATA, 50 pF, PAD_DRV=’00’1)2) DATA, 50 pF, PAD_DRV=’01’1)2) DATA, 50 pF, PAD_DRV=’10’1)2) DATA, 50pF, PAD_DRV=’11’1)2) IFA/IFB, 20 pF, PAD_DRV=’0x’1)2) IFA/IFB, 20 pF, PAD_DRV=’1x’1)2) Unit Note / Test Condition 1) Valid for push-pull output 2) Not subject to production test - verified by design/characterization 3.5.1 Synchronous Serial Communication (SSC) Interface The 3-pin SSC Interface has a bi-directional push-pull data line, serial clock signal, and chip select. The SSC Interface is designed to communicate with a microcontroller peer-to-peer for fast applications. SSC Communication for peer to peer Data Transmission between TLE5012 and µC (SSC Slave) TLE 5012 **) µC (SSC Master) Shift Reg. EN DATA MTSR Shift Reg. EN MRST SCK *) SCK Clock Gen. CSQ *) CSQ *) optional , e.g. 100 Ω **) optional , e.g. 470 Ω Figure 15 SSC configuration in sensor-slave mode with push-pull outputs (high speed application) Final Data Sheet 27 V 1.0, 2010-11 TLE5012 Specifications Another possibility is a 3-pin SSC Interface with bidirectional open-drain data line, serial clock signal, and chip select. This setup is designed to communicate with a microcontroller in a bus system, together with other SSC slaves (e.g. two TLE5012 devices for redundancy reasons). This mode can be activated using bit SSC_OD. SSC Communication for Bus Data Transmission between one or more TLE5012 and µC (SSC Slave) TLE 5012 typ. 1kΩ *) *) µC (SSC Master) Shift Reg. DATA MTSR Shift Reg. MRST SCK *) SCK Clock Gen. CSQ *) CSQ *) optional , e.g. 100 Ω Figure 16 SSC configuration in sensor-slave mode and open drain (safe bus systems) 3.5.1.1 SSC Timing Definition tCSs tSCKp tCSh tCSoff CSQ tSCKh tSCKl tSCKoff SCK DATA tDATAs tDATAh Figure 17 SSC timing SSC Inactive Time (CSoff) The SSC inactive time defines the delay time after a transfer before the TLE5012 can be selected again. Table 13 Parameter SSC baud rate CSQ setup time SSC push-pull timing specification Symbol Min. fSSC tCSs 105 Values Typ. 8.0 Max. Mbit/s ns 1) 1) Unit Note / Test Condition Final Data Sheet 28 V 1.0, 2010-11 TLE5012 Specifications Table 13 Parameter CSQ hold time CSQ off SCK period SCK high SCK low DATA setup time DATA hold time Write read delay SCK off SSC push-pull timing specification (cont’d) Symbol Min. tCSh tCSoff tSCKp tSCKh tSCKl tDATAs tDATAh twr_delay tSCKoff 105 600 120 40 30 25 40 130 170 125 Values Typ. Max. ns ns ns ns ns ns ns ns ns 1) Unit Note / Test Condition SSC inactive time1) 1) 1) 1) 1) 1) 1) 1) 1) Not subject to production test - verified by design/characterization Table 14 Parameter SSC open-drain timing specification Symbol Min. fSSC tCSs tCSh tCSoff tSCKp tSCKh tSCKl tDATAs tDATAh twr_delay tSCKoff 300 400 600 500 25 40 130 170 Values Typ. 2.0 190 190 Max. Mbit/s ns ns ns ns ns ns ns ns ns ns Pull-up Resistor = 1kΩ1) 1) 1) Unit Note / Test Condition SSC baud rate CSQ setup time CSQ hold time CSQ off SCK period SCK high SCK low DATA setup time DATA hold time Write read delay SCK off SSC inactive time1) 1) 1) 1) 1) 1) 1) 1) 1) Not subject to production test - verified by design/characterization Final Data Sheet 29 V 1.0, 2010-11 TLE5012 Specifications 3.5.1.2 • • • SSC Data Transfer The SSC data transfer is word-aligned. The following transfer words are possible: Command Word (to access and change operating modes of the TLE5012) Data Words (any data transferred in any direction) Safety Word (confirms the data transfer and provide status information) twr_delay COMMAND READ Data 1 READ Data 2 SAFETY-WORD SSC-Master is driving DATA SSC-Slave is driving DAT A Figure 18 SSC data transfer (data-read example) twr_delay COMMAND WRITE Data 1 SAFETY-WORD SSC-Master is driving DATA SSC-Slave is driving DAT A Figure 19 SSC data transfer (data-write example) Command Word The TLE5012 is controlled by a Command Word. It is sent first at the start of every data transmission. The structure of the Command Word is shown in Table 15, where the update (UPD) bit allows access to current or updated values. If an update command is issued and UPD is set, the immediate values are stored in the update buffer simultaneously. This enables a snapshot of all necessary system parameters at the same time. Bits with an update buffer are marked by an “u” in the bit type in the register description. Table 15 Name RW Structure of the Command Word Bits [15] Description Read - write 0:Write 1:Read 4-bit lock value 0000B: Default operating access for addresses 0x00:0x04 1010B: Config- access for addresses 0x05:0x11 Update register access 0: Access to current values 1: Access to updated values 30 V 1.0, 2010-11 Lock [14..11] UPD [10] Final Data Sheet TLE5012 Specifications Table 15 Name ADDR ND Safety Word The Safety Word contains following bits: Table 16 Name STAT Structure of the Safety Word Bits [15] Description Indication of chip reset (resets after readout) via SSC 0: Reset occurred 1: No reset Reset: 1B System error (e.g. overvoltage; undervoltage; VDD-, GND- off; ROM;...) 0: Error occurred (S_VR; S_DSPU; S_OV; S_XYOL: S_MAGOL; S_ADCM; S_FUSE) 1: No error Interface access error (access to wrong address; wrong lock) 0: Error occurred 1: No error Valid angle value (no system error; no interface error; NO_GMR_A = ’0’; NO_GMR_XY=’0’) 0: Angle value invalid 1: Angle value valid Sensor number response indicator The sensor no. bit is pulled low and the other bits are high Cyclic Redundancy Check Chip and Interface Status Structure of the Command Word Bits [9..4] [3..0] Description 6-bit Address 4-bit Number of data words [14] [13] [12] RESP CRC Bit Types [11..8] [7..0] The types of bits used in the registers are listed here: Table 17 R W U Bit types Function Read Write Update Description Read-only registers Read and write registers Update buffer for this bit is present. If an update is issued and the Update Register Access bit (UPD in Command Word) is set, the immediate values are stored in this update buffer simultaneously. This enables a snapshot of all necessary system parameters at the same time. Abbreviation Final Data Sheet 31 V 1.0, 2010-11 TLE5012 Specifications Data Communication via SSC SSC Transfer Command Word SCK DATA CSQ RW LOCK SSC -Master is driving DAT A SSC -Slave is driving DAT A UPD ADDR LENGTH MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB MSB 1 LSB twr_delay Data Word (s) Figure 20 • • • • • • • • • • SSC bit ordering (read example) The data communication via SSC Interface has the following characteristics: The data transmission order is “Most Significant Bit (MSB) first”. Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK. The SSC Interface is word-aligned. All functions are activated after each transmitted word. A “high” condition on the negated Chip Select pin (CSQ) of the selected TLE5012 interrupts the transfer immediately. The CRC calculator is automatically reset. After changing the data direction, a delay (twr_delay) has to occur before continuing the data transfer. This is necessary for internal register access. Every access to the TLE5012 with the number of data (ND) ≥ 1 is performed with address auto-increment. At an overflow at address 3FH the transfer continuous at address 00H. With ND = 0, no auto-increment is done and a continuously readout of the same address can occur. Afterwards no Safety Word is sent and the transfer ends with high condition on CSQ. After every data transfer with ND ≥ 1, the 16-bit Safety Word will be appended by the selected TLE5012. After the Safety Word is sent, the transfer ends. To start another data transfer, the CSQ has to be deselected once for tCSoff. The SSC is by default push-pull. The push-pull driver is active only if the TLE5012 has to send data; otherwise the push-pull is disabled for receiving data from the microcontroller. Cyclic Redundancy Check (CRC) • • • • • • This CRC complies with the J1850 Bus Specification. Every new transfer resets the CRC generation. Every byte of a transfer will be taken into account to generate the CRC (also the sent command(s)). Generator polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast CRC generation circuit is used (see Figure 21) The remainder of the fast CRC circuit is initial set to ’11111111B’. The remainder is inverted before transmission. Serial CRC output X7 1 X6 1 X5 1 X4 1 xor X3 1 X2 xor 1 X1 xor 1 X0 1 & xor Input TX_CRC parallel Remainder Figure 21 Fast CRC polynomial division circuit Final Data Sheet 32 V 1.0, 2010-11 TLE5012 Specifications 3.5.1.3 Registers This section describes the registers of the TLE5012. It also specifies the read/write access rights of the specific registers. Table 18 identifies the values with symbols. Access to the registers is accomplished via the SSC Interface. Table 18 Registers Overview Register Long Name Status Register Activation Status Register Angle Value Register Angle Speed Register Angle Revolution Register Frame Synchronization Register Interface Mode1 Register SIL Register Interface Mode2 Register Interface Mode3 Register Offset X Offset Y Synchronicity IFAB Register Interface Mode4 Register Temperature Coefficient Register X-raw value Y-raw value IIF Counter value Offset Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 20H Page Number 34 36 37 38 39 39 40 41 42 43 44 45 45 46 47 48 48 49 49 Register Short Name STAT ACSTAT AVAL ASPD AREV FSYNC MOD_1 SIL MOD_2 MOD_3 OFFX OFFY SYNCH IFAB MOD_4 TCO_Y ADC_X ADC_Y IIF_CNT Registers, TLE5012 Register The register is addressed wordwise. Final Data Sheet 33 V 1.0, 2010-11 TLE5012 Specifications 3.5.1.3.1 TLE5012 Register Status Register STAT Status Register Offset 00H Reset Value 8001H 15 RD_ST r 7 S_MAGOL ru 14 S_NR w 6 S_XYOL ru 13 12 NO_GMR_ A 11 NO_GMR_ XY ru 3 S_FUSE ru 10 S_ROM r 2 S_VR ru 9 S_ADCT ru 1 S_WD ru 8 Res 5 S_OV ru ru 4 S_DSPU ru 0 S_RST ru Field RD_ST Bits 15 Type r Description Read Status 0B status values not changed since last readout 1B status values changed Reset: 1B Slave Number is given at startup by the external circuit of IFA and IFB and can be changed via SSC-IF Reset: 00B No valid GMR Angle Value Cyclic check of DSPU output. 0B valid GMR angle value on the interface 1B no valid GMR angle value on the interface (e.g test vectors) Reset: 0B No valid GMR XY Values Cyclic check of ADC input. 0B valid GMR_XY values on the ADC input 1B no valid GMR_XY values on the ADC input (e.g. test vectors) Reset: 0B Status ROM1) Check of ROM-CRC at startup. After fail DSPU does not start. SPI access possible. 0B CRC OK 1B CRC fail or running Reset: 0B S_NR 14:13 w NO_GMR_A 12 ru NO_GMR_XY 11 ru S_ROM 10 r Final Data Sheet 34 V 1.0, 2010-11 TLE5012 Specifications Field S_ADCT Bits 9 Type ru Description Status ADC-Test1) Check of signal path with test vectors. All test vectors at startup tested. Activation in operation via AS_ADCT possible. 0B Test vectors OK 1B Test vectors out of limit Reset: 0B Status Magnitude Out of Limit1) Cyclic check of available magnetic field strength. Deactivation via AS_VEC_MAG. 0B GMR-magnitude OK 1B GMR-magnitude out of limit Reset: 0B Status X,Y Data Out of Limit1) Cylcic check of X and Y raw values. Deactivation via AS_VEC_XY 0B X,Y data OK 1B X,Y data out of limit (>23230 digits) Reset: 0B Status Overflow1) Cyclic check of DSPU overflow. Deactivation via AS_OV. 0B No DSPU overflow occurred 1B DSPU overflow occurred Reset: 0B Status Digital Signal Processing Unit Check of DSPU, CORDIC and CAPCOM at startup. Activation in operation via AS_DSPU possible. 0B DSPU self-test OK DSPU self-test not OK, or self-test is running 1B Reset: 0B Status Fuse CRC1) Cyclic CRC check of laser-cut-fuses. Deactivation via AS_FUSE and disabled by activated autocalibration. Note: Changing of fused parameters results in new CRC, which differs from stored CRC --> Fuse CRC fail 0B Fuse CRC OK 1B Fuse CRC fail Reset: 0B S_MAGOL 7 ru S_XYOL 6 ru S_OV 5 ru S_DSPU 4 ru S_FUSE 3 ru S_VR 2 ru Status Voltage Regulator1) Permanent check of internal and external supply voltages. Deactivation via AS_VR 0B Voltages OK VDD overvoltage; VDD undervoltage; VDD-off; GND1B off; or VOVG; VOVA; VOVD too high Reset: 0B Final Data Sheet 35 V 1.0, 2010-11 TLE5012 Specifications Field S_WD Bits 1 Type ru Description Status Watchdog Permanent check of watchdog. After overflow, a reset is necessary. Deactivation via AS_WD 0B after chip reset 1B watchdog counter expired (DSPU stop), AS_RST must be activated Reset: 0B Status Reset Permanent check of any reset. Deactivation via AS_RST. 0B no reset since last readout 1B indication of power-up, short power-break or active reset Reset: 1B S_RST 0 ru 1) Reset to “0” after readout Activation Status Register ACSTAT Activation Status Register Offset 01H Reset Value 5EFEH 15 Res w 7 AS_VEC_ MAG w 6 AS_VEC_ XY w 5 AS_OV w 4 AS_DSPU w 3 AS_FUSE w 10 9 AS_ADCT w 1 AS_WD w 8 Res 2 AS_VR w 0 AS_RST w Field Res AS_ADCT Bits 15:10 9 Type w w Description Reserved Reset: 010111B Enable ADC Testvector Check 0B after execution 1B activation of ADC Testvector Check Reset: 1B Activation of Magnitude Check 0B monitoring of magnitude disabled 1B monitoring of magnitude enabled Reset: 1B AS_VEC_MAG 7 w Final Data Sheet 36 V 1.0, 2010-11 TLE5012 Specifications Field AS_VEC_XY Bits 6 Type w Description Activation of X,Yout of limit Check 0B monitoring of X,Y out of limit disabled 1B monitoring of X,Y out of limit enabled Reset: 1B Enable of DSPU Overflow Check 0B monitoring of DSPU Overflow disabled 1B monitoring of DSPU Overflow enabled Reset: 1B Activation DSPU BIST 0B after execution 1B activation of DSPU BIST or BIST running Reset: 1B Activation Fuse CRC 0B monitoring of Fuse CRC disabled 1B monitoring of Fuse CRC enabled Reset: 1B Enable Voltage Regulator Check 0B check of regulator voltages disabled 1B check of regulator voltages enabled Reset: 1B Enable DSPU Watchdog-HW-Reset 0B DSPU Watchdog monitoring disabled 1B DSPU Watchdog monitoring enabled Reset: 1B Activation of Hardware Reset Activation occurs after CSQ switches from ’0’ to ’1’ after SSC transfer. 0B after execution 1B activation of HW Reset Reset: 0B AS_OV 5 w AS_DSPU 4 w AS_FUSE 3 w AS_VR 2 w AS_WD 1 w AS_RST 0 w Angle Value Register AVAL Angle Value Register Offset 02H Reset Value 8000H 15 RD_AV r 7 14 ANG_VAL ru 8 0 ANG_VAL ru Final Data Sheet 37 V 1.0, 2010-11 TLE5012 Specifications Field RD_AV Bits 15 Type r Description Read Status, Angle Value 0B no new angle value since last readout 1B new angle value (ANG_VAL) present Reset: 1B Calculated Angle Value (ANG_RANGE = 0x080) Angle[°] = 360 ° ANG _ VAL [ digits ] 215 ANG_VAL 14:0 ru (4) 4000H -180° 0000H 0° 3FFFH +179.99° Reset: 0H Angle Speed Register ASPD Angle Speed Register Offset 03H Reset Value 8000H 15 RD_AS r 7 14 ANG_SPD ru 8 0 ANG_SPD ru Field RD_AS Bits 15 Type r Description Read Status, Angle Speed 0B no new angle speed value since last readout 1B new angle speed value (ANG_SPD) present Reset: 1B Calculated Angle Speed Without prediction difference among three consecutive angle values. With prediction, difference among three predicted angle values. AngleRange [ ° ] ANG _ SPD [ digits ] 2 15 Speed [ ° / s ] = 2 t upd [ s ] ANG_SPD 14:0 ru (5) Reset: 0H Final Data Sheet 38 V 1.0, 2010-11 TLE5012 Specifications Angle Revolution Register AREV Angle Revolution Register Offset 04H Reset Value 8000H 15 RD_REV r 7 14 FCNT wu 9 8 REVOL ru 0 REVOL ru Field RD_REV Bits 15 Type r Description Read Status, Revolution 0B no new values since last readout 1B new value (REVOL) present Reset: 1B Frame Counter (unsigned 6-bit value) Counts every new angle value Reset: 0H Number of Revolutions (signed 9-bit value) If prediction is enabled, revolution counter is one schedule delayed related to ANG_VAL. Reset: 0H FCNT 14:9 wu REVOL 8:0 ru Frame Synchronization Register FSYNC Frame Synchronization Register Offset 05H Reset Value 0000H 15 FSYNC wu 7 Res 9 8 Res 0 Final Data Sheet 39 V 1.0, 2010-11 TLE5012 Specifications Field FSYNC Bits 15:9 Type wu Description Frame Synchronization Counter Value Sub-counter within one frame. Reset: 0H Interface Mode1 Register MOD_1 Interface Mode1 Register Offset 06H Reset Value 8001H 15 FIR_MD w 7 14 13 Res 8 5 Res 4 CLK_SEL w 3 SSC_OD w 2 DSPU_HO LD w 1 IIF_MOD w 0 Field FIR_MD Bits 15:14 Type w Description Filter Decimation Setting (Update Rate Setting) 00B 21.3 µs (only for raw X/Y-values) 01B 42.7 µs 10B 85.3 µs 11B 170.6 µs Reset: 10B Clock Source Select In absence of external clock or PLL out of lock, automatically switch to internal oscillator 0B internal oscillator 1B external 4-MHz clock Reset: 0B SSC Interface 0B Push-pull 1B Open drain (default within TLE5012-E0318 and TLE5012-E0742) Reset: 0B CLK_SEL 4 w SSC_OD 3 w Final Data Sheet 40 V 1.0, 2010-11 TLE5012 Specifications Field DSPU_HOLD Bits 2 Type w Description Hold DSPU Operation If DSPU is on hold, no WD reset is performed by DSPU. Deactivate watchdog with AS_WD before setting DSPU on hold. 0B DSPU in normal schedule operation 1B DSPU is on hold Reset: 0B Incremental Interface Mode 00B IIF disabled 01B A/B operation with Index on DATA 10B Step/Direction operation with Index on DATA 11B not allowed Reset: 01B IIF_MOD 1:0 w SIL Register SIL SIL Register Offset 07H Reset Value 0000H 15 FILT_PA R w 7 Res 14 FILT_IN V w 6 ADCTV_E N w 13 Res 11 10 FUSE_RE L 9 Res 8 5 ADCTV_Y w 3 w 2 ADCTV_X w 0 Field FILT_PAR Bits 15 Type w Description Filter Parallel 0B filter parallel disabled 1B filter parallel enabled (source: X-value) Reset: 0B Filter Inverted 0B filter inverted disabled 1B filter inverted enabled Reset: 0B Fuse Reload 0B fuse reload disabled 1B fuse parameters reloaded to DSPU at next cycle start Reset: 0B FILT_INV 14 w FUSE_REL 10 w Final Data Sheet 41 V 1.0, 2010-11 TLE5012 Specifications Field ADCTV_EN Bits 6 Type w Description ADC-Test vectors 0B ADC-Test vectors disabled 1B ADC-Test vectors enabled Reset: 0B Test vector Y 000B 0V 001B +70% 010B +100% 011B +Overflow 101B -70% 110B -100% 111B -Overflow Reset: 0H Test vector X 000B 0V 001B +70% 010B +100% 011B +OV 101B -70% 110B -100% 111B -OV Reset: 0H ADCTV_Y 5:3 w ADCTV_X 2:0 w Interface Mode2 Register MOD_2 Interface Mode2 Register Offset 08H Reset Value 0800H 15 Res 14 ANG_RANGE w 3 ANG_DIR w 8 7 ANG_RANGE w 4 2 PREDICT w 1 AUTOCAL w 0 Field ANG_RANGE Bits 14:4 Type w Description Angle Range Angle Range [°] = 360° * (27 / ANG_RANGE[digits]) 200H represents 90° 080H represents 360° Reset: 080H Final Data Sheet 42 V 1.0, 2010-11 TLE5012 Specifications Field ANG_DIR Bits 3 Type w Description Angle Direction 0B counterclockwise rotation of magnet 1B clockwise rotation of magnet Reset: 0B Prediction 0B prediction disabled 1B prediction enabled (default within TLE5012-E0318 and TLE5012-E0742) Reset: 0B Autocalibration Mode Autocalibration modes are described on Page 23. 00B no autocalibration 01B autocalibration mode 1 (default within TLE5012E0318 and TLE5012-E0742) 10B autocalibration mode 2 11B autocalibration mode 3 Reset: 00B PREDICT 2 w AUTOCAL 1:0 w Interface Mode3 Register MOD_3 Interface Mode3 Register Offset 09H Reset Value 0000H 15 ANG_BASE w 7 ANG_BASE w 4 3 SPIKEF w 2 Res 1 PAD_DRV w 8 0 Field ANG_BASE Bits 15:4 Type w Description Angle Base 800H -180° 000H 0° 001H 0.0879° 7FFH +179.912° Reset: 000H Analog Spike Filters of Input Pads 0B spike filter disabled 1B spike filter enabled Reset: 0B SPIKEF 3 w Final Data Sheet 43 V 1.0, 2010-11 TLE5012 Specifications Field PAD_DRV Bits 1:0 Type w Description Configuration of Pad-Driver 00B IFA/IFB: strong driver, DATA: strong driver, fast edge 01B IFA/IFB: strong driver, DATA: strong driver, slow edge 10B IFA/IFB: weak driver, DATA: medium driver, fast edge (default within TLE5012-E0318 and TLE5012-E0742) 11B IFA/IFB: weak driver, DATA: weak driver, slow edge Reset: 00B Offset X Register OFFX Offset X Offset 0AH Reset Value 0000H 15 X_OFFSET w 7 X_OFFSET w 4 3 Res 8 0 Field X_OFFSET Bits 15:4 Type w Description Offset Correction of X-value in digits Reset: 0H Final Data Sheet 44 V 1.0, 2010-11 TLE5012 Specifications Offset Y Register OFFY Offset Y Offset 0BH Reset Value 0000H 15 Y_OFFSET w 7 Y_OFFSET w 4 3 Res 8 0 Field Y_OFFSET Bits 15:4 Type w Description Offset Correction of Y-value in digits Reset: 0H Synchronicity Register SYNCH Synchronicity Offset 0CH Reset Value 0000H 15 SYNCH w 7 SYNCH w 4 3 Res 8 0 Field SYNCH Bits 15:4 Type w Description Amplitude Synchronicity +2047D 112.494% 0D 100% -2048D 87.500% Reset: 0H Final Data Sheet 45 V 1.0, 2010-11 TLE5012 Specifications IFAB Register IFAB IFAB Register Offset 0DH Reset Value 0003H 15 ORTHO w 7 ORTHO w 4 3 Res 2 IFAB_OD w 1 IFAB_HYST w 8 0 Field ORTHO Bits 15:4 Type w Description Orthogonality Correction of X and Y Components +2047D 11.2445° 0D 0° -2048D -11.2500° Reset: 0H IFA & IFB Open Drain 0B Push-pull 1B Open drain (default within TLE5012-E0318 and TLE5012-E0742) Reset: 0B HSM Hysteresis 00B 0° 01B 0.09° 10B 0.27° 11B 0.625° Reset: 11B IFAB_OD 2 w IFAB_HYST 1:0 w Final Data Sheet 46 V 1.0, 2010-11 TLE5012 Specifications Interface Mode4 Register MOD_4 Interface Mode4 Register Offset 0EH Reset Value 0000H 15 TCO_X_T w 4 IFAB_RES w 9 8 Res 7 HSM_PLP w 5 3 2 IF_MD w 0 Field TCO_X_T HSM_PLP Bits 15:9 7:5 Type w w Description Offset Temperature Coefficient for X-Component Reset: 0H Hall Switch Mode; Pole pair Configuration 000B 2 pole pairs 001B 3 pole pairs (default within TLE5012-E0318) 010B 4 pole pairs 011B 6 pole pairs 100B 7 pole pairs (default within TLE5012-E0742) 101B 8 pole pairs 110B 12 pole pairs 111B 16 pole pairs Reset: 000B IFAB Resolution 00B 12 bit = 0.088° (244Hz) 01B 11 bit = 0.176° (488Hz) 10B 10 bit = 0.352° (977Hz) 11B 9 bit = 0.703° (1953Hz) Reset: 00B IFAB_RES 4:3 w Final Data Sheet 47 V 1.0, 2010-11 TLE5012 Specifications Field IF_MD Bits 2:0 Type w Description Interface Mode Selected by external circuit of CLK pin at Power-On Time. CLK pin connected to VDD --> Incremental Interface is selected; CLK pin connected to GND --> IF_MD stored Interface is used. Switching to another interface during operation needs to stop the DSPU (DSPU_HOLD). Note: Combinations not listed below are not allowed 000B SSC mode; IIF 001B SSC mode; PWM 010B SSC mode; HSM (default within TLE5012-E0318 and TLE5012-E0742) Reset: 000B Temperature Coefficient Register TCO_Y Temperature Coefficient Register Offset 0FH Reset Value 0000H 15 TCO_Y_T w 9 8 Res 7 CRC_PAR w 0 Field TCO_Y_T CRC_PAR Bits 15:9 7:0 Type w w Description Offset Temperature Coefficient for Y-Component Reset: 0H CRC of Parameters CRC of parameters from address 08H to 0FH. When changing any settings within these registers, this CRC has to be updated. Reset: 0H X-raw Value Register ADC_X X-raw value Offset 10H Reset Value 0000H Final Data Sheet 48 V 1.0, 2010-11 TLE5012 Specifications 15 ADC_X r 0 Field ADC_X Bits 15:0 Type r Description ADC value of X-GMR Read out of this register will update ADC_Y Reset: 0H Y-raw Value Register ADC_Y Y-raw value Offset 11H Reset Value 0000H 15 ADC_Y r 0 Field ADC_Y Bits 15:0 Type r Description ADC value of Y-GMR Updated when ADC_X or ADC_Y is read. Reset: 0H Increment Counter Register IIF_CNT IIF Counter value Offset 20H Reset Value 0000H 15 Res 12 11 IIF_CNT r 0 Final Data Sheet 49 V 1.0, 2010-11 TLE5012 Specifications Field IIF_CNT Bits 11:0 Type r Description Counter value of increments This value can be used for synchronization purposes between sensor and counter value on microcontroller side. Reset: 0H 3.5.1.4 Communication Examples This section gives some short SPI communication examples. The sensor has to be selected first via CSQ, and SCK must be available for the communication. Table 19 SSC command to read the angle value Master transmitting TLE5012 transmitting Note SSC Description Word No. 1 2 3 Command Read Data Safety Word 1_0000_0_000010_0001 1_xxxxxxxxxxxxxxx 1_1_1_1_xxxx_xxxxxxxx Read angle value Read Safety Word Table 20 SSC command to read angle speed and angle revolution Master transmitting TLE5012 transmitting Note SSC Description Word No. 1 2 3 4 Command Read Data Read Data Safety Word 1_0000_0_000011_0010 1_xxxxxxxxxxxxxxx 1_xxxxxx_xxxxxxxxx 1_1_1_1_xxxx_xxxxxxxx Read angle speed Read angle revolution Read Safety Word Table 21 SSC command to change Interface Mode2 register Master transmitting TLE5012 transmitting Note SSC Description Word No. 1 2 Command Write Data 0_1010_0_001000_0001 0_00010000000_1_0_01 ANG_Range: 080H; ANG_DIR: 1B; PREDICT: 0B; AUTOCAL: 01B 1_1_1_1_xxxx_xxxxxxxx Read Safety Word 3 Safety Word Final Data Sheet 50 V 1.0, 2010-11 TLE5012 Specifications 3.5.2 Pulse-Width Modulation Interface The Pulse-Width Modulation (PWM) Interface can be selected via SPI. The PWM update rate can be changed within the register 0EH (IFAB_RES) in following steps: • • • • 0.25 kHz with 12-bit resolution 0.5 kHz with 12-bit resolution 1.0 kHz with 12-bit resolution 2.0 kHz with 12-bit resolution PWM uses a square wave with constant frequency whose duty cycle is modulated, resulting in an average value of the waveform. Figure 22 shows the principal behavior of a PWM with various duty cycles and the definition of timing values. The duty cycle of a PWM is defined by following general formulas: Duty Cycle = ton t PWM t PWM = t on + toff f PWM = 1 t PWM (6) The range between 0 - 6.25% and 93.75 - 100% is used only for diagnostic purposes. More details are given in Table 22. UIFA Vdd ON = High level OFF = Low level tON Duty cycle = 5% tPWM UIFA ‚0' t OFF Duty cycle = 50% Vdd t UIFA ‚0' Vdd Duty cycle = 95% t ‚0' Figure 22 Table 22 Parameter PWM output frequency Typical Example for a PWM Signal PWM Interface Symbol Min. fPWM 244 Values Typ. Max. 1953 Hz Unit Note / Test Condition t selectable by IFAB_RES1)2) Final Data Sheet 51 V 1.0, 2010-11 TLE5012 Specifications Table 22 Parameter Output duty cycle range PWM Interface Symbol Min. DYPWM 6.25 2 98 Values Typ. Max. 93.75 % % % Absolute angle2) Electrical error (S_RST; S_VR)2) System error (S_FUSE; S_OV; S_XYOL; S_MAGOL; S_ADCT)2) Short to GND2) Short to VDD, Power-Loss2) 2)3) Unit Note / Test Condition 0 99 PWM period variation tPWMvar -5 - 1 100 5 % % % 1) fPWM = (fDIG * 2IFAB_RES) / (24 * 4096) 2) Not subject to production test - verified by design/characterization 3) Depends on internal oscillator frequency variation (Section 3.4.6) Final Data Sheet 52 V 1.0, 2010-11 TLE5012 Specifications 3.5.3 Hall Switch Mode The Hall Switch Mode (HSM) within the TLE5012 makes it possible to emulate the output of three Hall switches. Hall switches are often used in electrical commutated motors to get information about the rotor position. With these three output signals, the motor will be commutated in the right way. Depending on which pole pairs of the rotor are used, various electrical periods have to be utilized. This is selectable within 0EH (HSM_PLP). Within the TLE5012E0318 three pole pairs are fused; within the TLE5012-E0742, seven pole pairs are fused. Figure 23 depicts the three output signals with the relationship between electrical angle and mechanical angle. The mechanical 0° point is always used as a reference. The HSM is generally used with open-drain output, but it can be changed to push-pull within SSC_OD and IFAB_OD. Hall-Switch-Mode: 3phase Generation Electrical Angle 0° 60° 120° 180° 240° 300° 360° HS1 HS2 HS3 Angle Mech. Angle with 8 Pole Pairs Mech. Angle with 3 Pole Pairs Figure 23 0° 0° 7.5° 20° 15° 40° 22.5° 60° 30° 80° 37.5° 100° 45° 120° Hall Switch Mode The HSM Interface can be selected by connecting CLK to GND, and CSQ has to be logic “1”. Table 23 Parameter Rotation speed Hall Switch Mode Symbol Min. n Values Typ. Max. 10000 rpm 2) Unit Note / Test Condition Final Data Sheet 53 V 1.0, 2010-11 TLE5012 Specifications Table 23 Parameter Electrical angle accuracy Hall Switch Mode Symbol Min. αelect Mechanical angle switching hysteresis Electrical angle switching hysteresis5) αHShystm αHShystel 0 Fall time Rise time 1) 2) 3) 4) 5) Values Typ. 1.2 1.8 2.4 3.6 4.2 4.8 7.2 9.6 1.25 1.88 2.50 3.75 4.38 5.00 7.50 10 0.02 0.4 Max. 2 3 4 6 7 8 12 16 0.625 1 1 Unit ° Note / Test Condition 2 pole pairs with autocalibration1)2) 3 pole pairs with autocal.1)2) 4 pole pairs with autocal.1)2) 6 pole pairs with autocal.1)2) 7 pole pairs with autocal.1)2) 8 pole pairs with autocal.1)2) 12 pole pairs with autocal.1)2) 16 pole pairs with autocal.1)2) ° ° selectable by IFAB_HYST2)3)4) 2 pole pairs; IFAB_HYST=111)2) 3 pole pairs; IFAB_HYST=111)2) 4 pole pairs; IFAB_HYST=111)2) 6 pole pairs; IFAB_HYST=111)2) 7 pole pairs; IFAB_HYST=111)2) 8 pole pairs; IFAB_HYST=111)2) 12 pole pairs; IFAB_HYST=111)2) 16 pole pairs; IFAB_HYST=111)2) tHSfall tHSrise - µs µs RL = 2.2 kΩ; CL < 50 pF2) RL = 2.2 kΩ; CL < 50 pF2) Depends on internal oscillator frequency variation (Section 3.4.6) Not subject to production test - verified by design/characterization GMR hysteresis not considered Minimum hysteresis without switching The hysteresis has to be considered only when rotation direction is changed. To avoid toggling on the HS outputs during mechanical vibration of the rotor, hysteresis (IFAB_HYST) is recommended (Figure 24). Final Data Sheet 54 V 1.0, 2010-11 TLE5012 Specifications Ideal Switching Point αHShystel αHShystel α elect Figure 24 HS hysteresis 0° αelect 3.5.4 Incremental Interface The Incremental Interface (IIF) uses an up/down counter of a microcontroller for the angle transmission. The synchronization is done by the parallel active SSC Interface. The angle value read out by the SSC Interface can be compared to the stored counter value. In case of a non-synchronization, the microcontroller adds the difference to the actual counter value to synchronize the TLE5012 with the microcontroller. The resolution of the IIF can be selected within the interface mode4 register (MOD_4) under IFAB_RES. After startup, the IIF pulses out the actual absolute angle value to notify the microcontroller about the absolute position. In register MOD_1 the IIF can be set in A/B mode or Step/Direction mode (IIF_MOD). A/B Mode The phase shift between phase A and B indicates a clockwise (A follows B) or a counterclockwise (B follows A) rotation of the magnet. Step/Direction Mode Phase A pulses out the increments and phase B indicates the direction (Figure 25). VH VL VH VL 0 1 2 3 4 3 2 1 Incremental Interface (Step/Dir Mode) Step Direction Counter Value Figure 25 Incremental Interface with Step/Direction mode Final Data Sheet 55 V 1.0, 2010-11 TLE5012 Specifications VDD CSQ N SSC iGMRSensor INC SCK DATA IFA IFB A B 12bit Up/Down Counter SSC µC S GND CSQ SPI Interface SCK DATA D0 D1 D2 D3 D11 D13 D14 D15 90° el. Phase shift Incremental Interface (A/B Mode) Phase A VH VL Phase B VH VL Counter Value 0 1 2 3 4 3 2 1 Figure 26 Incremental Interface Protocol with symbolic illustration of SPI Interface Index Signal The Index Signal is generated via the Data pin while CSQ is high (no SSC communication). The Index Signal is coded in quadrants via a PWM sequence, Figure 27. Angle 0° 90° 180° 270° 0° INDEX t0° Figure 27 Table 24 Parameter Incremental output frequency IIF index coding Incremental Interface Symbol t90° t180° t 270° Values Min. Typ. Max. 1.0 - Unit MHz Note / Test Condition Frequency of Phase A and Phase B1) fInc Final Data Sheet 56 V 1.0, 2010-11 TLE5012 Specifications Table 24 Parameter Index Incremental Interface (cont’d) Symbol Min. t0° t90° t180° t270° 5 10 15 20 Values Typ. Max. µs µs µs µs 0°1) 90°1) 180°1) 270°1) Unit Note / Test Condition 1) Not subject to production test - verified by design/characterization 3.6 Test Structure 3.6.1 ADC Test Vectors It is possible to feed the ADCs with appropriate values to simulate a certain magnet position and other GMR effects. This test can be activated within the SIL register (ADCTV_EN). With ADCTV_Y and ADCTV_X the vector length can be adjusted as shown in Figure 28. The values are generated with resistors on the chip. The following X/Y ADC values can be programmed: • • • • 4 points, circle amplitude = 70% (0°,90°, 180°, 270°) 8 points, circle amplitude = 100% (0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°) 8 points, circle amplitude = 122.1% (35.3°, 54.7°, 125.3°, 144.7°, 215.3°, 234.7°, 305.3°, 324.7°) 4 points, circle amplitude = 141.4% (45°, 135°, 225°, 315°) Note: The 100% values typically correspond to 21700 digits and the 70% values to 15500 digits. Table 25 ADC Test Vectors X/Y values (decimal) min. 000 001 010 011 100 101 110 111 1) Invalid 1) Register bits typ. 0 15500 21700 32767 0 -15500 -21700 -32768 max. Final Data Sheet 57 V 1.0, 2010-11 TLE5012 Specifications ADCTV_Y 122.1% 141.4% 0% 100 .0% 70% ADCTV_X Figure 28 ADC test vectors Examples for ADC test vector check The sensor has to be selected first via CSQ and SCK must be available for the communication. Table 26 shows the structure of the communication to enable the ADC test vector for 54.7°. Table 26 SSC command to enable ADC test vector check Master transmitting TLE5012 transmitting Note SSC Description Word No. 1 2 3 Command Write Data Safety Word 0_1010_0_000111_0001 0_0_000_0_000_1_010_001 1_1_1_0_xxxx_xxxxxxxx check of 54.7° Table 27 Structure of Write Data for some different test vectors Master transmitting TLE5012 transmitting Note SSC Description Word No. 1 2 3 4 5 Write Data Write Data Write Data Write Data Write Data 0_0_000_0_000_1_001_101 0_0_000_0_000_1_010_110 0_0_000_0_000_1_101_110 0_0_000_0_000_1_101_000 0_0_000_0_000_1_101_010 ~135° ~135° ~215.3° ~270° ~324.7° Final Data Sheet 58 V 1.0, 2010-11 TLE5012 Specifications 3.7 Overvoltage Comparators Various comparators monitor the voltage in order to ensure error-free operation. The overvoltage must be active at least 256 periods of tDIG to set the test comparator bits in the SSC Interface registers. This serves as digital spike suppression. Table 28 Parameter Overvoltage Detection Test comparators Symbol Min. VOVG VOVA VOVD VDD Overvoltage VDD Undervoltage GND - Off Voltage VDD - Off Voltage Spike Filter Delay VDDOV VDDUV VGNDoff VVDDoff tDEL Values Typ. 2.80 2.80 2.80 6.05 2.70 -0.55 0.55 10 Max. V V V V V V V µs 1) Unit Note / Test Condition 1) Not subject to production test - verified by design/characterization 3.7.1 Internal Supply Voltage Comparators Every voltage regulator has an overvoltage (OV) comparator to detect a malfunction. If the nominal output voltage of 2.5 V is larger than VOVG, VOVA and VOVD, then this overvoltage comparator is activated. VDDA REF VDD VRG VRA VRD GND Figure 29 OV comparator + GND 10µs Spike Filter xxx_OV 3.7.2 VDD Overvoltage Detection The Overvoltage Detection comparator monitors the external supply voltage at the VDD pin. It activates the S_VR bit (Figure 29). 3.7.3 GND - Off Comparator The GND - Off comparator is used to detect a voltage difference between the GND pin and SCK. It activates the S_VR bit of the SSC Interface. This circuit can detect a disconnection of the supply GND pin. Final Data Sheet 59 V 1.0, 2010-11 TLE5012 Specifications VDD Diodereference VDDA SCK +dV + GND GND 1µs Mono Flop 10µs Spike Filter GND_OFF Figure 30 GND - Off comparator 3.7.4 VDD - Off Comparator The VDD - Off comparator detects a disconnection of the VDD pin supply voltage. In this case, the TLE5012 is supplied by the SCK and CSQ input pins via the ESD structures. It activates the S_VR bit. VDDA VDD VVDDoff CSQ SCK GND Figure 31 VDD - Off comparator -dV + GND 1µs Mono Flop 10µs Spike Filter VDD _OFF Final Data Sheet 60 V 1.0, 2010-11 TLE5012 Package Information 4 Package Information 4.1 Package Parameters Table 29 Parameter Package parameters Symbol Limit Values min. typ. max. 150 200 75 85 MSL 3 Cu Sn 100% > 7 µm K/W K/W K/W Junction to air1) Junction to case Junction to lead 260°C RthJA RthJC RthJL Unit Notes Thermal resistance Soldering moisture level Lead frame Plating 1) According to Jedec JESD51-7 4.2 Package Outline Figure 32 PG-DSO-8 package dimensions Final Data Sheet 61 V 1.0, 2010-11 TLE5012 Package Information Figure 33 Position of sensing element 4.3 Footprint 1.31 0.65 5.69 1.27 Figure 34 Footprint of PG-DSO-8 4.4 Packing 8 0.3 12 ±0.3 5.2 6.4 1.75 2.1 Figure 35 Tape and Reel Final Data Sheet 62 V 1.0, 2010-11 TLE5012 Package Information 4.5 Marking Position 1st Line 2nd Line 3rd Line Processing Marking 5012xx xxx Gxxxx Description See ordering table on Page 8 Lot code G..green, 4-digit..date code Note: For processing recommendations, please refer to Infineon’s Notes on processing Final Data Sheet 63 V 1.0, 2010-11 www.infineon.com Published by Infineon Technologies AG