TLE6208-3G

Triple-Half-Bridge TLE 6208-3 G 1 1.1 • • • • • • • • Overview Features • • • • • • Three Half-Bridges Optimized for DC motor management applications Delivers up to 0.6 A continuous, 1.2 A peak current RDS ON; typ. 0.8 Ω, @ 25 °C per switch Output: short circuit protected and diagnosis Overtemperature-Protection with hysteresis and diagnosis Standard SPI-Interface/Daisy chain capable Very low current consumption in stand-by (Inhibit) mode (typ. 10 µA for power and 2 µA for logic supply, @ 25 °C) Over- and Undervoltage-Lockout CMOS/TTL compatible inputs with hysteresis No crossover current Internal clamp diodes Enhanced power P-DSO-Package Programming compatibility to the TLE 5208-6 G Ordering Code Q67006-A9334 P-DSO-14-9 Enhanced Power Type TLE 6208-3 G Functional Description Package P-DSO-14-9 The TLE 6208-3 G is a fully protected Triple-Half-Bridge-Driver designed specifically for automotive and industrial motion control applications. The part is based on the Siemens power technology SPT® which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuitry. In motion control up to 2 actuators (DC-Motors) can be connected to the 3 halfbridgeoutputs (cascade configuration). Operation modes forward (cw), reverse (ccw), brake and high impedance are controlled from a standard SPI-Interface. The possibility to control the outputs via software from a central logic, allows limiting the power dissipation. So the standard P-DSO-14-package meets the application requirements and saves PCB-Board-space and cost. Furthermore the build-in features like Over- and Undervoltage-Lockout, Over-Temperature-Protection and the very low quiescent current in stand-by mode opens a wide range of automotive- and industrial-applications. Data Sheet 1 2001-05-10 TLE 6208-3 G 1.2 Pin Configuration (top view) P-DSO-14-9 GND OUT 3 VS CSN DI CLK GND 1 2 3 4 5 6 7 Chip Leadframe 14 GND 13 OUT 1 12 OUT 2 11 V CC 10 INH 9 DO 8 GND AEP02438 Figure 1 Data Sheet 2 2001-05-10 TLE 6208-3 G 1.3 Pin No. 1 Pin Definitions and Functions Symbol GND Function Ground; Reference potential; internal connection to pin 7, 8 and 14; cooling tab; to reduce thermal resistance place cooling areas on PCB close to these pins. Halfbridge-Output 3; Internally contected to Highside-Switch 3 and Lowside-Switch 3. The HS-Switch is a Power-MOS open drain with internal reverse diode; The LS-Switch is a Power-MOS open source with internal reverse diode; no internal clamp diode or active zenering; short circuit protected and open load controlled. Power Supply; needs a blocking capacitor as close as possible to GND Value: 22 µF electrolytic in parallel to 220 nF ceramic. Serial Data Input; receives serial data from the control device; serial data transmitted to DI is an 16bit control word with the Least Significant Bit (LSB) being transferred first: the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see Table Input Data Protocol. Chip-Select-Not Input; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal active pull up and requires CMOS logic level inputs. Serial Clock Input; clocks the shiftregister; CLK has an internal active pull down and requires CMOS logic level inputs. Ground; see pin 1. Serial-Data-Output; this 3-state output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on Chip-Select-Not (CSN); see Table Diagnosis Data Protocol. Inhibit Input; has an internal pull down; device is switched in standby condition by pulling the INH terminal low. Logic Supply Voltage; needs a blocking capacitor as close as possible to GND; Value: 10 µF electrolytic in parallel to 220 nF ceramic. Halfbridge-Output 2; see pin 2. Halfbridge-Output 1; see pin 2. 2 OUT3 3 VS 5 DI 4 CSN 6 7, 8, 14 9 CLK GND DO 10 INH 11 VCC 12 13 OUT2 OUT1 Data Sheet 3 2001-05-10 TLE 6208-3 G 1.4 Functional Block Diagram V CC 11 Bias Charge Pump VS DRV1 3 13 OUT 1 INH 10 Inhibit FaultDetect CSN DI CLK DO 4 5 6 9 SPI 16 Bit Logic and Latch DRV2 12 OUT 2 UV OV TSD >1 DRV3 2 OUT 3 1,7,8,14 GND AEB02439 Figure 2 Block Diagram Data Sheet 4 2001-05-10 TLE 6208-3 G 1.5 Circuit Description Figure 2 shows a block schematic diagram of the module. There are 3 halfbridge drivers on the right-hand side. An HS driver and an LS driver are combined to form a halfbridge driver in each case. The drivers communicate via the internal data bus with the logic and the other control and monitoring functions: undervoltage (UV), overvoltage (OV), overtemperature (TSD), charge pump and fault detect. Two connection interfaces are provided for supply to the module: All power drivers are connected to the supply voltage VS. These are monitored by overvoltage and undervoltage comparators with hysteresis, so that the correct function can be checked in the application at any time. The logic is supplied by the VCC voltage, typ. with 5 V. The VCC voltage uses an internally generated Power-On Reset (POR) to initialize the module at power-on. The advantage of this system is that information stored in the logic remains intact in the event of shortterm failures in the supply voltage VS. The system can therefore continue to operate following VS undervoltage, without having to be reprogrammed. The “undervoltage” information is stored, and can be read out via the interface. The same logically applies for overvoltage. “Interference spikes” on VS are therefore effectively suppressed. The situation is different in the case of undervoltage on the VCC connection pin. If this occurs, then the internally stored data is deleted, and the output levels are switched to high-impedance status (tristate). The module is initialized by VCC following restart (Power-On Reset = POR). The 16-bit wide programming word or control word (see Table Input Data Protocol) is read in via the DI data input, and this is synchronized with the clock input CLK. The status word appears synchronously at the DO data output (see Table Diagnosis Data Protocol). It is also possible to connect two TLE 6208-3 G in a daisy chain configuration. The DO data output of one device is connected with the DI data input of the second device. In this configuration these two devices are controlled with a single CSN chip select and using a 32-bit wide control word. The transmission cycle begins when the chip is selected with the CSN input (H to L). If the CSN input changes from L to H then the word which has been read in becomes the control word. The DO output switches to tristate status at this point, thereby releasing the DO bus circuit for other uses. The INH inhibit input can be used to cut off the complete module. This reduces the current consumption to just a few µA, and results in the loss of any data stored. The output levels are switched to tristate status. The module is reinitialized with the internally generated POR (Power-On Reset) at restart. This feature allows the use of this module in battery-operated applications (vehicle body control applications). Data Sheet 5 2001-05-10 TLE 6208-3 G Every driver block from DRV 1 to 3 contains a low-side driver and a high-side driver. Both drivers are connected internally to form a half-bridge at the output. This reduction of output pins was necessary to meet the small P-DSO-14 package. When commutating inductive loads, the dissipated power peak can be significantly reduced by activating the transistor located parallel to the internal freewheeling diode. A special, integrated “timer” for power ON/OFF times ensures that there is no crossover current. Input Data Protocol BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H = ON L = OFF OVLO on/off not used Overcurrent SD on/off not used not used not used not used not used not used HS-Switch 3 LS-Switch 3 HS-Switch 2 LS-Switch 2 HS-Switch 1 LS-Switch 1 Status Register Reset Diagnosis Data Protocol BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H = ON L = OFF Power supply fail Underload Overload not used not used not used not used not used not used Status HS-Switch 3 Status LS-Switch 3 Status HS-Switch 2 Status LS-Switch 2 Status HS-Switch 1 Status LS-Switch 1 Temp. Prewarning Data Sheet 6 2001-05-10 TLE 6208-3 G Fault Result Table Fault Overcurrent (load) Short circuit to GND (high-side-switch) Short circuit to VS (low-side-switch) Temperature shut down (SD) Underload/Openload Diag.-Bit 13 13 13 Result Only the failed output is switched OFF. Function can be deactivated by bit No. 13. Only the failed output is switched OFF. Function can be deactivated by bit No. 13. Only the failed output is switched OFF. Function can be deactivated by bit No. 13. Reaction of control device needed. All outputs OFF. Temperature warning is set before. Reaction of control device needed. All outputs OFF. All outputs OFF. Function can be deactivated by bit No. 15. Temperature warning 0 – 14 Undervoltage lockout 15 (UVLO) Overvoltage lockout (OVLO) H = failure; L = no failure. 15 Data Sheet 7 2001-05-10 TLE 6208-3 G 2 2.1 Parameter Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. 40 – 5.5 5.5 5.5 40 – – 150 150 – – V V V V V V A A °C °C 4kV 8kV – – 0.3 –1 – 0.3 – 0.3 – 0.3 – 0.3 – – – 40 – 50 – – Unit Remarks Supply voltage Supply voltage Logic supply voltage Logic input voltages (DI, CLK, CSN, INH) Logic output voltage (DO) Output voltage (OUT 1-3) Output current (cont.) Output current (peak) Junction temperature Storage temperature ESD voltage, human body model, according to: • MIL STD 883D, • ANSI EOS\ESD S5.1 • JEDEC JESD22-A114 VS VS VCC VI VDO VOUT IOUT1-3 IOUT1-3 Tj Tstg VESD-HBM VESD-HBMOUT t < 0.5 s; IS > – 2 A 0 V < V S < 40 V 0 V < V S < 40 V 0 V < VCC < 5.5 V 0 V < V S < 40 V 0 V < VCC < 5.5 V 0 V < V S < 40 V internal limited internal limited – – all pins only pins 2, 12 and 13 (outputs) Note: Current limits are mentioned in the overcurrent section of electrical charateristics ESD voltage, mashine model, VESD-MM according to: • ANSI EOS\ESD S5.2 • JEDEC JESD22-A115 – – 300V all pins Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data Sheet 8 2001-05-10 TLE 6208-3 G 2.2 Parameter Operating Range Symbol Limit Values min. max. V V/µs V After VS rising above VUV ON – – Outputs in tristate Outputs in tristate – – – Unit Remarks Supply voltage Supply voltage slew rate Logic supply voltage Supply voltage increasing Supply voltage decreasing Logic input voltage (DI, CLK, CSN, INH) SPI clock frequency Junction temperature Thermal Resistances Junction pin Junction ambient VS dV S / dt VUV OFF 40 – 4.75 – 0.3 – 0.3 – 0.3 – – 40 10 5.50 VCC VS VS VI fCLK Tj VUV ON V VUV OFF V VCC V 1 150 MHz °C Rthj-pin RthjA – – 30 65 K/W K/W measured to pin 1, 7, 8, 14 – Note: In the operating range, the functions given in the circuit description are fulfilled. Data Sheet 9 2001-05-10 TLE 6208-3 G 2.3 Electrical Characteristics 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Condition Current Consumption Quiescent current IS – 8 20 µA INH = Low; VS = 13.2 V T j = 2 5 °C INH = Low; VS = 13.2 V; INH = Low SPI not active – Quiescent current Logic-Supply current Logic-Supply current Supply current IS ICC ICC IS – – – – – 2 1 2 30 10 2 5 µA µA mA mA Over- and Under-Voltage Lockout UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis OV-Switch-OFF voltage OV-Switch-ON voltage OV-ON/OFF-Hysteresis VUV ON VUV OFF VUV HY VOV OFF VOV ON VOV HY – 5.6 – 34 30 – 6.5 6.1 0.4 37 33 4 7 6.6 – 40 36 – V V V V V V VS increasing VS decreasing VUV ON – VUV OFF VS increasing VS decreasing VOV OFF – VOV ON Data Sheet 10 2001-05-10 TLE 6208-3 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Condition Outputs OUT1-3 Static Drain-Source-On Resistance Source (High-Side) IOUT = – 0.5 A RDS ON H – 0.8 – 1 – 0.95 1.6 – 2 0.9 1.5 – 2 Ω Ω Ω Ω Ω Ω Ω Ω 8 V < V S < 40 V T j = 25 ° C 8 V < V S < 40 V Sink (Low-Side) RDS ON L – 0.75 – 1 – IOUT = 0.5 A VS OFF < VS ≤ 8 V T j = 25 ° C VS OFF < VS ≤ 8 V 8 V < V S < 40 V T j = 25 ° C 8 V < V S < 40 V VS OFF < VS ≤ 8 V T j = 25 ° C VS OFF < VS ≤ 8 V Leakage Current Source-Output-Stage 1 to 3 Sink-Output-Stage 1 to 3 Overcurrent Source shutdown threshold Sink shutdown threshold Current limit Shutdown delay time IQLH IQLL –5 – –1 150 – 300 µA µA VOUT1-3 = 0 V VOUT1-3 = VS ISDU ISDL IOCL tdSD –2 1 – 10 – 1.3 – 1 1.2 2.4 28 2 4 40 A A A µs – – sink and source sink and source Data Sheet 11 2001-05-10 TLE 6208-3 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Condition Open Circuit/Underload Detection Detection current Delay time IOCD tdOC 15 200 30 370 45 600 mA µs – – Output Delay Times; VS = 13.2 V; RLoad = 25 Ω (device not in stand-by for t > 1 ms) Source ON Source OFF Sink ON Sink OFF Dead time Dead time td ON H td OFF H td ON L td OFF L tD HL tD LH – – – – 1 1 8 4 7 3 3 5 20 20 20 20 – – µs µs µs µs µs µs – – – – td ON L – td OFF H td ON H – td OFF L Output Switching Times; VS = 13.2 V; RLoad = 25 Ω (device not in stand-by for t > 1 ms) Source ON Source OFF Sink ON Sink OFF tON H tOFF H tON L tOFF L – – – – 5 2 2.0 1.5 20 5 10 5 µs µs µs µs – – – – Clamp Diodes Forward Voltage Upper Lower VFU VFL – – 0.9 0.9 1.3 1.3 V V IF = 0.5 A IF = 0.5 A Data Sheet 12 2001-05-10 TLE 6208-3 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Condition Inhibit Input H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull down current Input capacitance VIH VIL VIHY II CI – 0.2 50 5 – 0.52 0.48 200 25 10 0.7 – 500 100 15 VCC VCC mV µA pF – – – VI = 0.2 × VCC 0 V < VCC < 5.25 V Note: Capacitances are guaranteed by design. SPI-Interface Delay Time from Stand-by to Data In/Power on Reset Setup time tset – – 100 µs – Logic Inputs DI, CLK and CSN H-input voltage threshold VIH VIL L-input voltage threshold Hysteresis of input voltage VIHY IICSN Pull up current at pin CSN Pull down current at pin DI IIDI Pull down current at pin CLK IICLK Input capacitance CI at pin CSN, DI or CLK – 0.2 50 – 50 10 10 – 0.52 0.48 200 – 25 25 25 10 0.7 – 500 – 10 50 50 15 VCC VCC mV µA µA µA pF – – – VCSN = 0.7 × VCC VDI = 0.2 × VCC VCLK = 0.2 × VCC 0 V < VCC < 5.25 V Note: Capacitances are guaranteed by design. Data Sheet 13 2001-05-10 TLE 6208-3 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Condition Logic Output DO H-output voltage level L-output voltage level Tri-state leakage current Tri-state input capacitance VDOH VDOL IDOLK CDO VCC – – 10 – VCC 0.2 0 10 – 0.4 10 15 V V µA pF IDOH = 1 mA IDOL = – 1.6 mA VCSN = VCC 0 V < VDO < VCC VCSN = VCC 0 V < VCC < 5.25 V – 1.0 – 0.7 Note: Capacitances are guaranteed by design. Data Input Timing Clock period Clock high time Clock low time Clock low before CSN low CSN setup time CLK setup time Clock low after CSN high DI setup time DI hold time Input signal rise time at pin DI, CLK and CSN Input signal fall time at pin DI, CLK and CSN tpCLK tCLKH tCLKL tbef tlead tlag tbeh tDISU tDIHO trIN tfIN 1000 500 500 500 500 500 500 250 250 – – – – – – – – – – – – – – – – – – – – – – 200 200 ns ns ns ns ns ns ns ns ns ns ns – – – – – – – – – – – Data Sheet 14 2001-05-10 TLE 6208-3 G 2.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Condition Data Output Timing DO rise time DO fall time DO enable time DO disable time DO valid time trDO tfDO tENDO tDISDO tVADO – – – – – 50 50 – – 100 100 100 250 250 250 ns ns ns ns ns CL = 100 pF CL = 100 pF low impedance high impedance VDO < 0.2 VCC; VDO > 0.7 VCC; CL = 100 pF Thermal Prewarning and Shutdown Thermal prewarning junction TjPW temperature Temperature prewarning hysteresis Thermal shutdown junction temperature Thermal switch-on junction temperature Temperature shutdown hysteresis Ratio of SD to PW temperature ∆T 120 – 150 120 – 145 30 175 – 30 1.20 170 – 200 170 – – °C K °C °C K – – – – – – – TjSD TjSO ∆T TjSD/TjPW 1.05 Note: Temperatures are guaranteed by design. The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Data Sheet 15 2001-05-10 TLE 6208-3 G 3 Timing Diagrams CSN High to Low & rising edge of CLK: DO is enabled. Status information is transferred to Output Shift Register CSN time CSN Low to High: Data from Shift-Register is transferred to Output Power Switches CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 time Actual Data DI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 New Data 01 ++ time DI: Data will be accepted on the falling edge of CLK-Signal Previous Status DO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ------Actual Status 0 1 time DO: State will change on the rising edge of CLK-Signal e.g. HS1 Old Data Actual Data time AET02177 Figure 3 Data Transfer Timing Data Sheet 16 2001-05-10 TLE 6208-3 G CSN High to Low & CLK Stays Low: Status information of Data Bit 0 (temperature prewarning) is transfered to DO CSN time CLK time DI time DI: Data is not accepted DO 0 time DO: Status information of Data Bit 0 (temperature prewarning) will stay as long as CSN is low AET02620 Figure 4 Timing for Temperature Prewarning only 0.7 VCC CSN 0.2 VCC t CLKH 0.7 VCC CLK 0.2 VCC t lead t bef t DISU t CLKL t DIHO Don’t Care t lag t beh 0.7 VCC Valid Don’t Care 0.2 VCC AET02178 DI Don’t Care Valid Figure 5 SPI-Input Timing Data Sheet 17 2001-05-10 TLE 6208-3 G t rIN t fIN 70% CSN t dOFF 50% 20% 70% Case 1 Ι OUT ON State t OFF t dON t ON 70% Case 2 Ι OUT OFF State ON State 50% 20% AET02179 OFF State 50% 20% Figure 6 Turn OFF/ON Time t rIN _ t fIN < 10 ns 0.7 VCC CLK t rDO 0.7 VCC DO (low to high) 0.2 VCC t VADO t fDO 0.7 VCC (high to low) 0.2 VCC AET02180 50% 0.2 VCC DO Figure 7 Data Sheet DO Valid Data Delay Time and Valid Time 18 2001-05-10 TLE 6208-3 G t fIN _ t rIN < 10 ns 0.7 VCC CSN t ENDO 50% 0.2 VCC t DISDO 10 k Ω Pullup to VCC DO t ENDO 50% t DISDO 10 k Ω Pulldown to GND DO 50% AET02181 Figure 8 DO Enable and Disable Time Data Sheet 19 2001-05-10 TLE 6208-3 G Watchdog Reset Q D TLE 4278G Ι D01 1N4001 D02 Z39 V S = 12V CQ 22 µF V CC CD 47 nF V CC 11 Bias CS 10 µF WD R VS DRV1 3 Charge Pump 13 OUT 1 INH 10 Inhibit FaultDetect M CSN 4 DI 5 µP CLK 6 DO 9 SPI 16 Bit Logic and Latch DRV2 12 OUT 2 M UV OV TSD >1 DRV3 2 OUT 3 1,7,8,14 GND GND AEB02441 Figure 9 Application Circuit Data Sheet 20 2001-05-10 TLE 6208-3 G 4 Package Outlines P-DSO-14-9 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 21 Dimensions in mm 2001-05-10 GPS09222