TLE6220GP_07

Data Sheet TLE 6220 GP Smart Quad Low-Side Switch Features Product Summary • Short Circuit Protection Supply voltage • Overtemperature Protection Drain source voltage • Overvoltage Protection • 8 bit Serial Data Input and DiagOn resistance nostic Output (SPI protocol) Output current (all outp. ON equal) • Direct Parallel Control of Four (individually) Channels for PWM Applications • Cascadable with Other Quad Switches • Low Quiescent Current • µC Compatible Input • Electostatic Discharge (ESD) Protection • Green Product (RoHS compliant) • AEC qualified Application • µC Compatible Power Switch for 12 V and 24 V Applications • Switch for Automotive and Industrial System • Solenoids, Relays and Resistive Loads • Injectors • Robotic controls VS VDS(AZ) max RON ID(NOM) 4.5 – 5.5 60 0.32 1 3 V V Ω A A PG-DSO-20-37 General Description Quad Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and four open drain DMOS output stages. The TLE 6 220 GP is protected by embedded protection functions and designed for automotive and industrial applications. The output stages can be controlled d irect in parallel for PWM applications (injector coils), or through serial control via the SPI. Therefore the TLE 6220 GP is particularly suitable for engine management and powertrain systems. Block Diagram PRG GND VS RESET VS FAULT normal function VBB IN1 IN2 IN3 IN4 as Ch. 1 as Ch. 1 SCB / overload LOGIC open load short to ground Output Stage as Ch. 1 OUT1 8 SCLK SI 8 1 4 4 OUT4 CS SO Serial Interface SPI Output Control Buffer GND V2.1 Page 1 2007-05-03 Data Sheet TLE 6220 GP Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol GND IN2 OUT1 VS Function Ground Input Channel 2 Power Output Channel 1 Supply Voltage Reset Chip Select Program (inputs high or low active) Power Output Channel 2 Input Channel 1 Ground Ground Input Channel 4 Power Output Channel 3 General Fault Flag Serial Data Output Serial Clock Serial Data Input Power Output Channel 4 Input Channel 3 Ground Pin Configuration (Top view) GND IN2 OUT1 VS RESET CS RESET CS PRG OUT2 IN1 GND GND IN4 OUT3 FAULT SO SCLK SI OUT4 IN3 GND PRG OUT2 IN1 GND 1• 2 3 4 5 6 7 8 9 10 Power SO-20 20 GND 19 IN3 18 OUT4 17 SI 16 SCLK 15 SO 14 FAULT 13 OUT3 12 IN4 11 GND Heat slug internally connected to ground pins V2.1 Page 2 2007-05-03 Data Sheet TLE 6220 GP Maximum Ratings for Tj = – 40°C to 150°C P arameter Supply Voltage Continuous Drain Source Voltage (OUT1...OUT4) Input Voltage, All Inputs and Data Lines Load Dump Protection VLoad Dump = UP+US; UP=13.5 V With Automotive Injector Valve RL = 14 Ω RI1)=2 Ω ; td=400ms; IN = low or high With RL= 6.8 Ω (ID = 2A) RI=2 Ω ; td=400ms; IN = low or high Operating Temperature Range Storage Temperature Range Output Current per Channel (see el. characteristics) Output Current per Channel @ TA = 25°C (All 4 Channels ON; Mounted on PCB )3) Output Clamping Energy ID = 1A P ower Dissipation (DC, mounted on PCB) @ TA = 25°C Electrostatic Discharge Voltage (human body model) according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993 DIN Humidity Category, DIN 40 040 IEC Climatic Category, DIN IEC 68-1 Thermal resistance junction – case (die soldered on the frame) junction - ambient @ min. footprint junction - ambient @ 6 cm2 cooling area Symbol VS VDS VIN VLoad Dump 2) Values -0.3 ... +7 45 - 0.3 ... + 7 62 52 Unit V V V V Tj Tstg ID(lim) ID EAS Ptot VESD - 40 ... + 150 - 55 ... + 150 ID(lim) min 1 50 3 2000 °C A A mJ W V E 40/150/56 K/W RthJC RthJA 2 50 38 Minimum footprint PCB with heat pipes, backside 6 cm2 cooling area 1) 2) RI=internal resistance of the load dump test pulse generator LD200 VLoadDump is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839. 3) Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 °C the output current has to be calculated using RthJA according mounting conditions. V2.1 Page 3 2007-05-03 Data Sheet TLE 6220 GP Electrical Characteristics Parameter and Conditions VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H (unless otherwise specified) 1. Power Supply, Reset Supply Voltage4 Supply Current 5 Symbol Values min Unit typ max VS IS 4.5 -10 -1 5.5 2 V mA µs Minimum Reset Duration tReset,min (After a reset all parallel inputs are ORed with the SPI data bits) 2. Power Outputs ON Resistance VS = 5 V; ID = 1 A Output Clamping Voltage Current Limit Output Leakage Current Turn-On Time Turn-Off Time 3. Digital Inputs Input Low Voltage Input High Voltage Input Voltage Hysteresis Input Pull Down/Up Current (IN1 ... IN4) PRG, RESET Pull Up Current Input Pull Down Current (SI, SCLK) Input Pull Up Current (CS ) 4. Digital Outputs (SO, FAULT ) SO High State Output Voltage SO Low State Output Voltage Output Tri-state Leakage Current FAULT Output Low Voltage VRESET = L ID = 1 A, resistive load ID = 1 A, resistive load TJ = 25°C TJ = 150°C output OFF RDS(ON) VDS(AZ) ID(lim) ID(lkg) tON tOFF --45 3 ---- 0.32 -53 4.5 -5 5 0.4 0.7 60 6 10 10 10 Ω V A µA µs µs VINL VINH VINHys IIN(1..4) IIN(PRG,Res) IIN(SI,SCLK) IIN(CS) - 0.3 2.0 50 20 20 10 10 --100 50 50 20 20 1.0 VS+0. 3 V V mV µA µA µA µA 200 100 100 50 50 ISOH = 2 mA ISOL = 2.5 mA CS = H, 0 ≤ VSO ≤ VS IFAULT = 1.6 mA VSOH VSOL ISOlkg VFAULTL ID(lim) 1...4 Tth(sd) Thys VS - 0.4 ----10 0 -3 170 --4.5 -10 -0.4 10 0.4 6 200 -- V V µA V A °C K Current Limitation; Overload Threshold Current Overtemperature Shutdown Threshold Hysteresis6 4 For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched off. This undervoltage reset gets active at VS = 3V (typ. value) and is guaranteed by design. 5 If Reset = L the supply current is reduced to typ. 20µA 6 This parameter will not be tested but guaranteed by design V2.1 Page 4 2007-05-03 Data Sheet TLE 6220 GP Electrical Characteristics cont. Parameter and Conditions VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H (unless otherwise specified) 5. Diagnostic Functions Open Load Detection Voltage Output Pull Down Current Fault Delay Time Short to Ground Detection Voltage Short to Ground Detection Current 6. SPI-Timing Serial Clock Frequency (depending on SO load) Serial Clock Period (1/fclk) Serial Clock High Time Serial Clock Low Time Enable Lead Time (falling edge of CS to rising edge of CLK) Enable Lag Time (falling edge of CLK to rising edge ofCS ) Data Setup Time (required time SI to falling of CLK) Data Hold Time (falling edge of CLK to SI) Disable Time @ CL = 50 pF8 Transfer Delay Time7 ( CS high time between two accesses) Data Valid Time CL = 50 pF CL = 100 pF8 CL = 220 pF8 Symbol Values min Unit typ max VDS(OL) IPD(OL) td(fault) VDS(SHG) ISHG VS -2.5 50 50 VS –3.3 -50 VS -2 90 110 VS -2.9 -100 VS -1.3 150 200 VS -2.5 -150 V µA µs V µA fSCK tp(SCK) tSCKH tSCKL tlead tlag tSU tH tDIS tdt tvalid DC 200 50 50 250 250 20 20 -200 ---- --------------- 5 -------150 -110 120 150 MHz ns ns ns ns ns ns ns ns ns ns 7 This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time td(fault)max = 200µs. 8 This parameter will not be tested but guaranteed by design V2.1 Page 5 2007-05-03 Data Sheet TLE 6220 GP Functional Description The TLE 6220 GP is an quad-low-side power switch which provides a serial peripheral interface (SPI) to control the 4 power DMOS switches, as well as diagnostic feedback. The power transistors are protected against short to VBB, overload, overtemperature and against overvoltage by an active zener clamp. The diagnostic logic recognises a fault condition which can be read out via the serial diagnostic output (SO). Circuit Description Power Transistor Protection Functions 9) Each of the four output stages has its own zener clamp, which causes a voltage limitation at the power transistor when solenoid loads are switched off. The outputs are provided with a current limitation set to a minimum of 3 A. The continuous current for each channel is 1A (all channels ON; depending on cooling). Each output is protected by embedded protection functions. In the event of an overload or short to supply, the current is internally limited and the corresponding bit combination is set (early warning). If this operation leads to an overtemperature condition, a second protection level (about 170 °C) will change the output into a low duty cycle PWM (selective thermal shutdown with restart) to prevent critical chip temperatures. SPI Signal Description CS - Chip Select. The system microcontroller selects the TLE 6220 GP by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice versa. CS High to Low transition: - Diagnostic status information is transferred from the power outputs into the shift register. - Serial input data can be clocked in from then on. - SO changes from high impedance state to logic high or low state corresponding to the SO bits. CS Low to High transition: - Transfer of SI bits from shift register into output buffers - Reset of diagnosis register. To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition of CS . When CS is in a logic high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. 9) The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or permanently. V2.1 Page 6 2007-05-03 Data Sheet TLE 6220 GP SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE 6220 GP. The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select CS makes any transition. SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on the falling edge of SCLK. Input data is latched in the shift register and then transferred to the control buffer of the output stages. The input data consists of one byte, made up of four control bits and four data bits. The control word is used to program the device, to operate it in a certain mode as well as providing diagnostic information (see page 11). The four data bits contain the input information for the four channels, and are high active. SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin following the rising edge of SCLK. RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and switches all outputs OFF. An internal pull-up structure is provided on chip. As long as the reset pin is low the device is in low quiescent current mode and the supply current is reduced to typ. 20µA. Output Stage Control The four outputs of the TLE 6220 GP can either be controlled in parallel (IN1...IN4), or via the Serial Peripheral Interface (SPI). Parallel Control A Boolean operation (either AND or OR) is performed on each of the parallel inputs and r e spective SPI data bits, in order to determine the states of the respective outputs. The type of Boolean operation performed is programmed via the serial interface. The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins are not connected (independent of high or low activity) it is guaranteed that the outputs 1 to 4 are switched OFF. PRG pin itself is internally pulled up when it is not connected. PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1 to 4 are high active PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active. V2.1 Page 7 2007-05-03 Data Sheet TLE 6220 GP Serial Control of the Outputs: SPI protocol Each output is independently controlled by an output latch and a common reset line, which disables all four outputs. The Serial Input (SI) is read on the falling edge of the serial clock. A logic high input 'data bit' turns the respective output channel ON, a logic low 'data bit' turns it OFF. CS must be low whilst shifting all the serial data into the device. A low -to-high transition of CS transfers the serial data input bits to the output control buffer. As mentioned above, the serial input byte consists of a 4 bit control word and a 4 bit data word. Via the control word, the specific mode of the device is programmable. MSB L SB CCCC DDDD : Serial input byte 123 123 Control Bits Data Bits Five specific control words are recognised, having the following functions: No. 1 2 3 4 5 Serial Input Byte LLLL XXXX HHLL XXXX HLHL XXXX LLHH DDDD HHHH DDDD Function Only 'Full Diagnosis' performed. No change to output states. State of four parallel inputs and '1-bit Diagnosis' outputted. Echo-function of SPI; SI direct connected to SO IN1...4 and serial data bits 'OR'ed. 'Full Diagnosis' performed. IN1...4 and serial data bits 'AND'ed. 'Full Diagnosis' performed. Note: 'X' means 'don't care', because this bit will be ignored 'D' represents the data bit, either being H (=ON) or L (=OFF) 1. LLLL XXXX - Diagnosis only By clocking in this control byte, it is possible to get pure diagnostic information (two bits per channel) in accordance with Figure 1 (page 11). The data bits are ignored, so that the state of the outputs are not influenced. This command is only active once unless the next control command is again "Diagnosis only". 2. HHLL XXXX - Reading back of input, and ‘1-bit Diagnosis’ If the TLE 6220 GP is used as bare die in a hybrid application, it is necessary to know if proper connections exist between the µC-port and parallel inputs. By entering ‘HHLL’ as the control word, the first four bits of the SO give the state of the parallel inputs, depending on the µC signals. By comparing the four IN-bits with the corresponding µC-port signal, the necessary connection between the µC and the TLE 6220 can be verified - i.e. ‘read back of the inputs’. The second 4-bit word fed out at the serial output contains ‘1-bit’ fault information of the outputs ( H = no fault, L = fault ). In the expression given below for the output byte, ‘FX’ is the fault bit for channel X. M SB LSB IN4 IN3 IN2 IN1 F4 F3 F2 F1 : Serial Output byte V2.1 Page 8 2007-05-03 Data Sheet TLE 6220 GP CS CS CS SI HHLL XXXX SI SO HHHH LHHL IN4 IN3 IN2 IN1 F4 F3 F2 F1 SI HHHH LLLL SO H H H H H H H H SI command: No change of the output state; reading back of inputs and 1bit diagnosis SO diagnosis : No fault, normal function SO H H H H H H H H SI command: AND-Operation and all channels OFF. SO diagnosis: No fault, normal function SI command : AND-Operation; Ch1 and 4 OFF, Ch2 and 3 ON. SO diagnosis: State of four parallel inputs and 1 bit diagnosis performed 3. HLHL XXXX - Echo-function of SPI To check the proper function of the s erial interface the TLE 6220 GP provides a "SPI Echo Function". By entering HLHL as control word, SI and SO are connected during the next CS period. By comparing the bits clocked in with the serial output bits, the proper function of the SPI interface can be verified. This internal loop is only closed once (for one CS period). CS CS SI HLHL XXXX SI SI word SO SO H H H H L H H H SI command: No change of the output states; Echo function of SPI SO diagnosis : Open load condition at channel 2, other channels ok. Echo-function of SPI , i.e. SI directly connected to SO. SI information will be accepted during this cycle and the outputs set accordingly after chip select rising edge 4. LLHH DDDD - OR operation, and ‘full diagnosis’ With LLHH as the control word, each of the input signals IN1...IN4 a 'OR'ed with the correre sponding data bits (DDDD). IN 1...4 ≥1 Serial Input, data bits 0...3 Output Driver This OR operation enables the serial interface to switch the channel ON, even though the corresponding parallel input might be in the off state. ⇒ SPI Priority for ON-State Also parallel control of the outputs is possible without an SPI input. The OR-function is the default Boolean operation if the device restarts after a Reset, or when the supply voltage is switched on for the first time. V2.1 Page 9 2007-05-03 Data Sheet TLE 6220 GP If the OR operation is programmed it is latched until it is overwritten by the AND operation. 5. HHHH DDDD - AND operation, and ‘full diagnosis’ With HHHH as the control word, each of the input signals IN1...IN4 are 'AND'ed with the corresponding data bits (DDDD). IN 1...4 & Serial Input, data bits 0...3 Output Driver The AND operation implies that the output can be switched off by the SPI data bit input, even if the corresponding parallel input is in the ON state. ⇒ SPI Priority for OFF-state This also implies that the serial input data bit can only switch the output channel ON if the corresponding parallel input is in the ON state. If the AND operation is programmed it is latched until it is overwritten by the OR operation. Control words beside No. 1- 5 All control words except those for Diag Only, Read Back of Inputs, SPI echo, will be accepted as an OR or an AND command with valid data bits depending on the boolean operation which was programmed before. Example 1: LLHH HLLH: OR operation between parallel inputs and data bits, i.e channel 1 and 4 will be switched on. The next command is now: LHHH HHLH LHHH as command word has no special meaning but it will be accepted as an OR operation and the data bits will be ORed with the inputs and the outputs 1,3 and 4 will be switched on. See above: 'If the OR operation is programmed it is latched until it is overwritten by the AND operation.' Example 2: HHHH LLHL means: Data bits will be ANDed with the parallel inputs and the outputs switch accordingly. Then HLLH HHLH is clocked in: AND was latched by the command before and is now valid again by using the HLLH command word. So the data bits will be accepted and again ANDed with the parallel input signals. See above: 'If the AND operation is programmed it is latched until it is overwritten by the OR operation.' V2.1 Page 10 2007-05-03 Data Sheet TLE 6220 GP Diagnostics FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transition as soon as an error occurs for any one of the four channels. This fault indication can be used to generate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called after this fault indication. This saves processor time compared to a cyclic reading of the SO information. As soon as a fault occurs, the fault information is latched into the diagnosis register. A new error will over-write the old error report. Serial data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially. The rising edge of CS will reset all error registers. Full Diagnosis For full diagnosis there are two diagnostic bits per channel configured as shown in Figure 1. Diagnostic Serial OUT (SO) 7 6 5 4 3 2 1 0 Ch.4 Ch.3 Ch.2 Ch.1 HH HL LH LL Normal function Overload, Shorted Load or Overtemperature Open Load Shorted to Ground Figure 1: Two bits per channel diagnostic feedback Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function. Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current limitation gets active, i.e. there is a overload, short to supply or overtemperature condition. Open load: An open load condition is detected when the drain voltage decreases below 3 V (typ.). LH bit combination is set. Short Circuit to GND: If a drain to ground short circuit exists and the drain to ground current exceeds 100 µA, short to ground is detected and the LL bit combination is set. A definite distinction between open load and short to ground is guaranteed by design. The standard way of obtaining diagnostic information is as follows: Clock in serial information into SI pin and wait approximately 150 µs to allow the outputs to settle. Clock in the identical serial information once again - during this process the data coming out at SO contains the bit combinations representing the diagnosis conditions as described in Fi g ure 1. V2.1 Page 11 2007-05-03 Data Sheet TLE 6220 GP Timing Diagrams CS SCLK Control Bits Data Bits 64444744448 64444744448 SI 7 MSB SO 7 6 5 4 3 2 1 6 5 4 3 2 1 0 LSB 0 Outputs OLD NEW Figure 2: Serial Interface Figure 3: Input Timing Diagram CS 0.7VS 0.2 VS tSCKH tlead tlag 0.7VS 0.2VS tdt SCLK tSCKL tSU tH 0.7VS 0.2V S SI Figure 4: 0.7 V S SCLK t valid CS 0.2 V S tD i s SO 0.7 V S 0.2 V S SO SO 0.7 V S 0.2 V S SO Valid Time Waveforms Enable and Disable Time Waveforms V2.1 Page 12 2007-05-03 Data Sheet TLE 6220 GP VIN t VDS 80% 20% tON tOFF t Figure 5: Power Outputs Application Circuit VBB VS 10k VS PRG FAULT OUT1 OUT2 RESET IN1 µC e.g. C166 MTSR MRST CLK P xy OUT4 IN2 IN3 IN4 SI SO CLK TLE 6220 GP GND V2.1 Page 13 2007-05-03 Data Sheet TLE 6220 GP Typical electrical Characteristics Drain-Source on-resistance RDS(ON) = f (Tj) ; Vs = 5V Typical Drain- Source ON-Resistance 0,58 0,53 0,48 RDS(ON) [Ohm] 0,43 0,38 0,33 0,28 0,23 -50 Channel 1-4 -25 0 25 50 Tj[°C] 75 100 125 150 175 Figure 6 : Typical ON Resistance versus Junction-Temperature Channel 1-4 Output Clamping Voltage VDS(AZ) = f (Tj) ; Vs = 5V Typical Clamping Voltage 55 54 53 Channel 1-4 VDS (AZ) [V] 52 51 50 49 48 -50 -25 0 25 50 Tj[°C] 75 100 125 150 175 Figure 7 : Typical Clamp Voltage versus Junction-Temperature Channel 1-4 Page 14 V2.1 2007-05-03 Data Sheet TLE 6220 GP Parallel SPI Configuration Engine Management Application TLE 6230 GP in combination with TLE 6240 GP (16-fold switch) for relays and general purpose loads and TLE 6220 GP (quad switch) to drive the injector valves. This arrangement covers the numerous loads to be driven in a modern Engine Management/Powertrain system. From 28 channels in sum 16 can be controlled direct in parallel for PWM applications. Injector 1 P x.1-4 4 4 PWM Channels SI SO CLK CS CS Injector 2 Injector 3 Injector 4 MTSR MRST CLK P x.y TLE 6220 GP Quad 4 P x.1-4 4 PWM Channels µC C167 P x.y 8 P x.1-8 SI SO CS CLK TLE 6230 GP Octal 8 PWM Channels SI SO CLK CS P x.y TLE 6240 GP 16-fold Daisy Chain Application TLE 6220 GP Px.1 Px.2 CS µC SI MTSR CLK CS SI CLK CS SI CLK TLE SO 6220 GP CS Q uad TLE SO 6220 GP Q uad TLE SO 6220 GP Q uad MRST V2.1 Page 15 2007-05-03 Data Sheet TLE 6220 GP Package and Ordering Code (all dimensions in mm) PG - DSO - 20 - 37 TLE 6220 GP Ordering Code Q67006-A9315 15 .7 4 + /- 0 .1 13.7 1.27 - 0.2 9 x 1 .2 7 = 1 1.43 0.4 + 0 .1 3 0.25 M A 20 11 3 . 2 + /- 0 .1 1 1 x 45° 10 P IN 1 IN D EX M AR K IN G A 1 5.9 + /- 0 .1 5 1.2 0 .1 1 .3 - 0.3 8° 2.8 8° 8° 6.3 8° 1) 1 1 + /- 0.15 14 .2 + /- 0 .3 V2.1 Page 5 .9 + / -0 . 1 16 2007-05-03 Data Sheet TLE 6220 GP Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHSCompliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD020). V2.1 Page 17 2007-05-03 Data Sheet TLE 6220 GP Revision History Version V2.0 -> V2.1 V1.1 -> V2.0 V2.0 Date 20.05.03 Changes Ordering Code removed 20.04.2007 20.04.2007 Green Date sheet Version created Changes to Green Product Version: - AEC, RoHS Logo and Feature List content added - Package Name P-DSO -> PGDSO - Change History added - Disclaimer re-newed Layout Changes, correct green package name implemented P-DSO-3612 à PG-DSO-36-26 Initial Version of “grey” product V2.0 -> V2.1 V1.1 05.04.2007 28.Aug.2007 V2.1 Page 18 2007-05-03 Data Sheet TLE 6220 GP Edition 2007-04-17 Published by Infineon Technologies AG 81726 Munich, Germany © 5/4/07 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com ). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. V2.1 Page 19 2007-05-03