TLE6240GP

TLE6240GP Smart 16-Channel Low-Side Switch coreFLEX Data Sheet Rev.3.3, 2010-02-15 Automotive Power TLE6240GP Smart 16-Channel Low-Side Switch Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 2 2.1 2.2 2.3 3 3.1 3.2 4 4.1 4.2 4.3 5 5.1 5.2 5.3 5.3.1 5.4 5.5 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.5.1 6.1.5.2 6.1.5.3 6.1.5.4 6.1.5.5 6.1.5.6 6.2 6.2.1 7 7.1 7.2 7.3 8 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Maximum Ratings and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical and Functional Description of Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Functions and FAULT-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control of the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Stage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Control and PRG - Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control of the Outputs: SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control- and Data Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Byte - Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Byte No.1 and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Byte No. 2 and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Byte No. 3 and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Byte No. 4 and 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Byte No. 5 and 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for an access to channel 1 to 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis Read-out options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Engine Management Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 14 17 18 21 21 21 21 21 23 24 24 25 26 26 27 28 28 29 32 32 33 34 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Data Sheet 2 V3.3, 2010-02-15 Smart 16-Channel Low-Side Switch coreFLEX TLE6240GP 1 Features • • • • • • • • • • • • Overview Short Circuit Protection Overtemperature Protection Overvoltage Protection 16 bit Serial Data Input and Diagnostic Output (2 bit/channel for Open Load- and Short to GND detection) Direct Parallel Control of eight channels for PWM Applications Parallel Inputs High or Low Active programmable General Fault Flag Low Quiescent Current Compatible with 3 V Microcontrollers Electrostatic discharge (ESD) Protection Green Product (RoHS compliant) AEC Qualified PG-DSO-36 Applications • • Automotive and Industrial Systems Solenoids, Relays and Resistive Loads General Description 16-fold Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and 16 open drain DMOS output stages. The TLE6240GP is protected by embedded protection functions and designed for automotive and industrial applications. The output stages are controlled via SPI Interface. Additionally 8 channels can be controlled direct in parallel for PWM applications. Therefore the TLE6240GP is particularly suitable for engine management and powertrain systems, safety and body applications. Type TLE6240GP Data Sheet Package PG-DSO-36 3 Marking TLE6240GP Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Overview Product Summary Parameter Supply voltage Drain source clamping voltage On resistance Symbol Value 4.5 … 5.5 45 .... 60 2.2 0.7 0.6 0.5 1 1 3 Unit V V Ω Ω Ω A A A A Nominal Output current (channel 1 - 8) Nominal Output current (channel 9 - 16) Minimum Output current Limit (channel 1 - 8) Minimum Output current Limit (channel 9 - 16) VS VDS(AZ)max RON1-8 (max @ 150°C) RON10,11,14,15 (max @ 150°C) RON9,12,13,16 (max @ 150°C) ID ID ID(lim)_min ID(lim)_min Block Diagram Figure 1 Application Block Diagram Data Sheet 4 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Block Diagram 2 2.1 Block Diagram Detailed Block Diagram Figure 2 Detailed Block Diagram 2.2 Description of Block Diagram All 16 channels can be controlled via the serial interface (SPI). In addition to the serial control it is possible to control channel 1 to 4 and 9 to 12 direct in parallel with a separate input pin. The parallel input signal is either OR - operated or AND - operated with the respective SPI data bit. This boolean operation can be programmed via SPI control byte (see Chapter 5). The SPI interface also performs a diagnostic information for each channel. Data Sheet 5 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Block Diagram 2.3 Terms VBatt PG-DSO-36 VOUT9 V OUT10 VOUT1 VOUT2 V IN1 VIN 2 VS VRESET VCS VPRG VIN3 VIN4 VOUT3 VOUT4 VOUT11 IOUT9 IOUT10 IOUT1 IOUT2 IIN1 IIN2 IS IRESET ICS IPRG IIN3 IIN4 I OUT3 IOUT4 IOUT11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND OUT9 OUT10 OUT1 OUT2 IN1 IN2 VS RESET CS PRG IN3 IN4 OUT3 OUT4 OUT11 OUT12 GND GND OUT16 OUT15 OUT8 OUT7 IN12 IN11 SI SCLK SO FAULT IN10 IN9 OUT6 OUT5 OUT14 OUT13 GND 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 IOUT16 IOUT15 IOUT8 I OUT7 IIN12 IIN11 ISI ISCLK I SO I FAULT IIN10 IIN9 I OUT6 IOUT5 IOUT14 IOUT13 V OUT13 VOUT6 VOUT5 V OUT14 VSCLK VSO V FAULT VIN10 VIN9 VIN4 VOUT4 V OUT16 V OUT15 VOUT8 VOUT7 V IN12 V IN11 VSI IOUT12 VOUT12 DSO-36(Power )_terms_TLE6240 .vsd Figure 3 Terms for Voltages and Currents Data Sheet 6 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Pin Configuration 3 3.1 Pin Configuration Pin Assignment PG-DSO-36 GND OUT9 1 2 36 GND 35 OUT16 34 OUT15 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 DSO-36(Power )_TLE6240.vsd OUT10 3 OUT1 OUT2 IN1 IN2 VS 4 5 6 7 8 OUT8 OUT7 IN12 IN11 SI SCLK SO FAULT IN10 IN9 OUT6 OUT5 OUT14 OUT13 GND RESET 9 CS PRG IN3 IN4 OUT3 OUT4 10 11 12 13 14 15 OUT11 16 OUT12 17 GND 18 Figure 4 Pin Configuration (top view) 3.2 Pin 1 2 3 4 5 6 7 8 9 10 Pin Definitions and Functions Symbol GND OUT9 OUT10 OUT1 OUT2 IN1 IN2 Function Ground Power Output Channel 9 Power Output Channel 10 Power Output Channel 1 Power Output Channel 2 Input Channel 1 Input Channel 2 Supply Voltage Reset Chip Select VS RESET CS Data Sheet 7 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Pin Configuration Pin 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol PRG IN3 IN4 OUT3 OUT4 OUT11 OUT12 GND GND OUT13 OUT14 OUT5 OUT6 IN9 IN10 FAULT SO SCLK SI IN11 IN12 OUT7 OUT8 OUT15 OUT16 GND Function Program (inputs high or low-active) Input Channel 3 Input Channel 4 Power Output Channel 3 Power Output Channel 4 Power Output Channel 11 Power Output Channel 12 Ground Ground Power Output Channel 13 Power Output Channel 14 Power Output Channel 5 Power Output Channel 6 Input Channel 9 Input Channel 10 General Fault Flag Serial Data Output Serial Clock Serial Data Input Input Channel 11 Input Channel 12 Power Output Channel 7 Power Output Channel 8 Power Output Channel 15 Power Output Channel 16 Ground Heat Slug internally connected to ground pins Data Sheet 8 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Maximum Ratings and Operating Conditions 4 4.1 Maximum Ratings and Operating Conditions Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Voltages 4.1.1 4.1.2 4.1.3 Currents 4.1.4 4.1.5 4.1.6 Output current per Channel (see Chapter 5) Output current per Channel (All 16 Channels ON; Mounted on PCB)2) Output current (Max. total current of all channels on; Heat Sink required) Electrostatic Discharge Voltage Supply voltage Continuous Drain Source Voltage (OUT1 to OUT16) Input Voltage, All Inputs and Data Lines Parameter Symbol Limit Values Min. Max. 7 45 7 V V V A A A A – – – – Unit Conditions VS VDS VIN ID(lim) ID 1-8 ID 9-16 IDmax -0.3 – -0.3 – – – – ID(lim) min 0.3 0.5 14 TA = 25 °C TA = 25 °C – ESD Susceptibility 4.1.7 VESD – 2000 V HBM3) 1) Not subject to production test, specified by design. 2) Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 °C the output current has to be calculated using RthJA according mounting conditions. 3) Human Body Model according to EIA/JESD22-A114-E. Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 9 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Maximum Ratings and Operating Conditions 4.2 Pos. Functional Range Parameter Symbol Min. Limit Values Typ. – – – Max. 150 150 50 °C °C mJ – – Unit Conditions Temperature Range 4.2.1 4.2.2 4.2.3 Operating Temperature Range Storage Temperature Range Tj Tstg -40 -55 – Single Pulse Inductive Energy Single pulse inductive Energy (internal EAS clamping) TJ = 25 °C; ID1-8 = 0.5 A; ID9-16 = 1 A TA = 25 °C all Channel active Power Dissipation 4.2.4 Power Dissipation (mounted on PCB) Ptot – 3.3 – W Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Pos. 4.3.1 4.3.2 Thermal Resistance Parameter Junction to Case (die soldered on heat slug)1) Junction to ambient (see Figure 51)); all channels active Symbol Min. Limit Values Typ. 0.5 12 Max. 1 – K/W K/W Pv = 3W Pv = 3W – – Unit Conditions RthJSp RthjA 1) Not subject to production test, specified by design. Data Sheet 10 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Maximum Ratings and Operating Conditions Dimensions: 76.2 x 114.3 x 1.5 mm³ ; Material: FR4 Thermal Vias: diameter= 0.3 mm; plating 25 µm; 61 pcs. Metalization accodring: JEDEC 2s2p (JESD 51-7) + (JESD 51-5) 70µm modeled (traces) 1,5 mm 35µm, 90% metalization 35µm, 90% metalization 70µm, 5% metalization Thermal_Setup.vsd Figure 5 Thermal Simulation - PCB set-up Data Sheet 11 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Electrical and Functional Description of Blocks 5 Electrical and Functional Description of Blocks The TLE6240GP is an 16-fold low-side power switch which provides a serial peripheral interface (SPI) to control the 16 power DMOS switches, and diagnostic feedback. The power transistors are protected against short to VBB, overload, overtemperature and against overvoltage by active zener clamp. The diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic output (SO). 5.1 Power Supply & Reset RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and switches all outputs OFF. An internal pull-up structure is provided on chip. In case the RESET Pin is pulled down statically, the device remains in Stand-by Mode Electrical Characteristics: Power Supply VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. 5.1.1 5.1.2 5.1.3 Parameter Supply Voltage Supply Current Supply Current in Standby Mode 1) Symbol Min. Limit Values Typ. – 5 10 Max. 5.5 10 50 4.5 – – Unit V mA µA Conditions – – (RESET = L) VS IS IS(stdy) 1) For VS < 4.5 V the power stages are switched according the input signals and data bits or are definitely switched off. This undervoltage reset gets active at VS = 3 V (typ. value) and is specified by design and not subject to production test. 5.2 • • • Digital Inputs In this chapter is the electrical behavior of the following Digital Input Pins described: parallel Input Pin INx Reset Pin RESET Program Pin PRG Electrical Characteristics: Digital Inputs VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 Parameter Input Low Voltage Input High Voltage Input Voltage Hysteresis Input Pull-down/up Current (IN1 to IN4, IN9 to IN12) PRG, Reset Pull-up Current Minimum Reset Duration (After a reset all parallel inputs are ORed with the SPI data bits) Symbol Min. Limit Values Typ. – – 100 50 50 – Max. 1.0 – 200 100 100 – V V mV µA µA µs – – – -0.3 2.0 50 20 Unit Conditions VINL VINH VINHys IIN(1..4,9..12) VIN = 5 V – – IIN(PRG,Res) 20 tReset,min 10 Data Sheet 12 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Electrical and Functional Description of Blocks 5.3 Power Outputs Power Transistor Protection Functions1) Each of the 16 output stages has its own zener clamp, which causes a voltage limitation at the power transistor when solenoid loads are switched off. The outputs are provided with a current limitation set to a minimum of 1 A for channels 1 to 8 and 3 A for channels 9 to 16. In the event of an overload or short to supply, the current is internally limited and the corresponding diagnosis bit combination is set. If this operation leads to an overtemperature condition, a second protection level will change the output into a low duty cycle PWM (selective thermal shut-down with restart) to prevent critical chip temperatures. Electrical Characteristics: Power Outputs VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 Parameter ON Resistance VS = 5 V; Channel 1-8 ON Resistance VS = 5 V; Channel 10, 11, 14, 15 ON Resistance VS = 5 V; Channel 9, 12, 13, 16 Output Clamping Voltage Channel 1-8 Output Clamping Voltage Channel 9-16 Current Limit Channel 1-8 Current Limit Channel 9-16 Output Leakage Current Turn-On Time Turn-Off Time Symbol Min. Limit Values Typ. 1 1.7 0.35 0.60 0.30 0.50 50 52.5 1.5 4.5 – 6 6 Max. – 2.2 – 0.70 – 0.60 60 60 2 6 10 12 12 Ω Ω Ω Ω Ω Ω V V A A µA µs µs – – – – – – 45 45 1 3 – – – Unit Conditions RDS(ON) RDS(ON) RDS(ON) VDS(AZ) VDS(AZ) ID(lim) ID(lim) ID(lkg) tON tOFF TJ = 25 °C1) TJ = 150 °C TJ = 25 °C1) TJ = 150 °C TJ = 25 °C1) TJ = 150 °C Output OFF Output OFF – – VReset = L ID = 0.5 A, resistive load 1) Specified by design and not subject to production test. 1) The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or permanently. Data Sheet 13 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Electrical and Functional Description of Blocks V IN t V DS 80% 20% tON tOFF t Figure 6 Timing 5.3.1 Typical Characteristics Drain-Source On-Resistance RDS(ON) = f(Tj); VS = 5 V Typical Drain-Source ON- Resistance 1,8 1,7 1,6 1,5 1,4 1,3 1,2 1,1 1 0,9 0,8 0,7 0,6 -50 Channel 1 - 8 RDS(ON) [Ohm] -25 0 25 50 Tj [°C] 75 100 125 150 175 Figure 7 Typical ON Resistance versus Junction-Temperature (Channel 1-8) Typical Drain-Source ON- Resistance Channel 10,11,14,15 0,65 0,6 0,55 RDS(ON) [Ohm] 0,5 0,45 0,4 0,35 0,3 0,25 0,2 -50 -25 0 25 50 Tj [°C] 75 100 125 150 175 Figure 8 Typical ON Resistance versus Junction-Temperature (Channel 10, 11, 14, 15) Data Sheet 14 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Electrical and Functional Description of Blocks Typical Drain-Source ON- Resistance Channel 9,12,13,16 0,55 0,5 RDS(ON) [Ohm] 0,45 0,4 0,35 0,3 0,25 0,2 0,15 -50 -25 0 25 50 Tj [°C] 75 100 125 150 175 Figure 9 Typical ON Resistance versus Junction-Temperature (Channel 9, 12, 13, 16) Output Clamping Voltage VDS(AZ) = f(Tj); VS = 5 V Typical Clamping Voltage 54 53 52 VDS(AZ) [V] 51 50 49 48 47 46 -50 Channel 1-8 -25 0 25 50 Tj [°C] 75 100 125 150 175 Figure 10 Typical Clamping Voltage versus Junction Temperature (Channel 1-8) Data Sheet 15 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Electrical and Functional Description of Blocks Typical Clamping Voltage 56 55 54 VDS(AZ) [V] 53 52 51 50 49 48 -50 Channel 9-16 -25 0 25 50 Tj [°C] 75 100 125 150 175 Figure 11 Typical Clamping Voltage versus Junction Temperature (Channel 9-16) Data Sheet 16 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Electrical and Functional Description of Blocks 5.4 Diagnostic Functions and FAULT-Pin The device provides diagnosis information about the device and about the load. There are following diagnosis flags implemented for each channel: • • • The diagnosis information of the protective functions, such as “over current” and “over temperature” The open load diagnosis The short to ground information. For further details, refer to the Chapter “Control of the device” FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transition as soon as an error occurs for any one of the sixteen channels. This fault indication can be used to generate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called after this fault indication. This saves processor time compared to a cyclic reading of the SO information. As soon as a fault occurs, the fault information is latched into the diagnosis register. A new error will overwrite the old error report. Serial data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially. Electrical Characteristics: Diagnostic Functions VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 Parameter Open Load Detection Voltage Symbol Min. Limit Values Typ. 90 100 -100 1.3 4 – 10 – Max. Unit Conditions – Threshold1) VDS(OL) Output Pull-down Current IPD(OL) Fault Delay Time td(fault) Short to Ground Detection Voltage VDS(SHG) Short to Ground Detection Current ISHG Overload Detection Threshold ID(lim) 1-8 ID(lim) 9-16 Overtemperature Shutdown Tth(sd) Overtemperature Hysteresis1) FAULT Output Low Voltage VS - 2.5 VS - 2 50 50 -50 1 3 170 – – VS - 1.3 V 150 200 -150 2 6 200 – 0.4 µA µs µA A A °C K V VReset = H – – VS - 3.3 VS - 2.9 VS - 2.5 V VReset = H – – – – Thys VfaultL IfaultL = 1.6 mA 1) Specified by design and not subject to production test. Data Sheet 17 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Electrical and Functional Description of Blocks 5.5 SPI Interface Electrical Characteristics: SPI Interface VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.5.10 5.5.11 5.5.12 5.5.13 5.5.14 5.5.15 Parameter Symbol Min. Input Pull-down Current (SI, SCLK) IIN(SI,SCLK) 10 Input Pull-up Current (CS) SO High State Output Voltage SO Low State Output Voltage Output Tri-state Leakage Current Serial Clock Frequency (depending on SO load) Serial Clock Period (1/fclk) Serial Clock High Time Serial Clock Low Time Enable Lead Time (falling edge of CS to rising edge of CLK) Enable Lag Time (falling edge of CLK to rising edge of CS) Limit Values Typ. 20 20 – 0 – – – – – – – – – – Max. 50 50 – 0.4 10 5 – – – – – – – 150 – µA µA V V µA MHz ns ns ns ns ns ns ns ns ns – – Unit Conditions IIN(CS) VSOH VSOL ISOlkg fSCK tp(SCK) tSCKH tSCKL tlead tlag 10 – -10 DC 200 50 50 200 200 20 20 – 200 VS - 0.4 – ISOH = 2 mA ISOL = 2.5 mA CS = H; 0 ≤ VSO ≤ VS – – – – – – – – – – Data Setup Time (required time SI tSU to falling of CLK) Data Hold Time (falling edge of CLK to SI) Disable Time (@ CL = 50 pF)1) Transfer Delay Time (CS high time between two accesses) Data Valid Time 2) tH tDIS tdt 5.5.16 tvalid – – – – – – 100 120 150 ns ns ns CL = 50 pF1) CL = 100 pF1) CL = 220 pF1) 1) This parameter will not be tested but specified by design 2) This time is necessary between two write accesses to control e.g. channel 1 to 8 during the first access and channel 9 to 16 during the second access. To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time td(fault)max = 200 µs. Data Sheet 18 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Electrical and Functional Description of Blocks CS 0.7VS 0.2 VS tSCKH tlag 0.7VS 0.2VS tdt SCLK tlead tSCKL tH 0.7VS 0.2VS tSU SI Figure 12 Input Timing Diagram 0.7 VS SCLK tvalid CS 0.2 VS tDis SO SO 0.7 VS 0.2 VS 0.7 VS 0.2 VS SO Figure 13 SO Valid Time Waveforms and Enable and Disable Time Waveforms SPI Signal Description CS - Chip Select. The system microcontroller selects the TLE6240GP by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice versa. • CS High to Low Transition: – diagnostic status information is transferred from the power outputs into the shift register – serial input data can be clocked in from then on – SO changes from high impedance state to logic high or low state corresponding to the SO bits CS Low to High Transition: – transfer of SI bits from shift register into output buffers • To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition of CS. When CS is in a logic high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE6240GP. The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while the serial output (SO) shifts Data Sheet 19 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Electrical and Functional Description of Blocks diagnostic information out of the shift register on the rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select CS makes any transition. SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on the falling edge of SCLK. Input data is latched in the shift register and then transferred to the control buffer of the output stages. The input data consist of 16 bit, made up of one control byte and one data byte. The control byte is used to program the device, to operate it in a certain mode as well as providing diagnostic information (see Chapter 6.2). The eight data bits contain the input information for the eight channels, and are high active. SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin following the rising edge of SCLK. Data Sheet 20 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device 6 6.1 Control of the Device Output Stage Control The 16 outputs of the TLE6240GP can be controlled via serial interface. Additionally eight of these 16 channels can alternatively be controlled in parallel (Channel 1 to 4 and 9 to 12) for PWM applications. 6.1.1 Parallel Control and PRG - Pin A Boolean operation (either AND or OR) is performed on each of the parallel inputs and respective SPI data bits, in order to determine the states of the respective outputs. The type of Boolean operation performed is programmed via the serial interface. The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins are not connected (independent of high or low activity) it is guaranteed that the outputs 1 to 4 and 9 to 12 are switched off. The PRG pin itself is internally pulled up when it is not connected. PRG - Program pin. • • PRG = High (VS): Parallel inputs Channel 1 to 4 and 9 to 12 are high active PRG = Low (GND): Parallel inputs Channel 1 to 4 and 9 to 12 are low active 6.1.2 6.1.3 Serial Control of the Outputs: SPI Protocol Overview Each output is independently controlled by an output latch and a common reset line, which disables all outputs. The Serial Input (SI) is read on the falling edge of the serial clock. A logic high input ‘data bit’ turns the respective output channel ON, a logic low ‘data bit’ turns it OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition of CS transfers the serial data input bits to the output control buffer. The 16 channels of the TLE6240GP are divided up into two parts for the control of the outputs (ON, OFF) and the diagnosis information. Serial Input (SI) information consists of 16 bit. 8 bit contain the input driver information for channel 1 to 8 or for channel 9 to 16. The remaining 8 bits are used to program a certain operation mode. Serial Output (SO) data consists of 16 bit containing the diagnosis information for channels 1 to 8 or channels 9 to 16 with two bits per channel. Channel 1 to 8: • • • Control Byte 1: Operation mode and diagnosis select for channels 1 to 8 Data Byte1: ON/OFF information for channel 1 to 8 DIAG_1: Diagnosis data for channels 1 to 8 Channel 9 to 16: • • • Control Byte 2: Operation mode and diagnosis select for channels 9 to 16 Data Byte2: ON/OFF information for channel 9 to 16 DIAG_2: Diagnosis data for channels 9 to 16 Data Sheet 21 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device To drive all 16 channels and to get the complete diagnosis data of the TLE6240GP a two step access has to be performed as follows: CS CS SI SO Control Byte1 Data Byte1 SI SO Control Byte1 Data Byte1 16 bit Diagnosis DIAG_1 (Ch. 1 to 8) SI command: Control Byte 1 programs the operation mode of channels 1 to 8. Data Byte 1 gives the input information (on or off) for Channel 1 to 8. SO diagnosis: Diagnosis information of channel 1 to 8 or 9 to 16, depending on the SI control word before. SI command: Control Byte 1 programs the operation mode of Channels 1 to 8. Data Byte 1 gives the input information (on or off) for Channel 1 to 8. SO diagnosis: 16 bit diagnosis information (two bit per channel) of channels 1 to 8 Figure 14 First Access CS CS SI SO Control Byte2 Data Byte2 SI SO Control Byte2 Data Byte2 16 bit Diagnosis DIAG_2 (Ch. 9 to 16) SI command: Control Byte 2 programs the operation mode of channels 9 to 16. Data Byte 2 gives the input information (on or off) for Channel 9 to 16. SO diagnosis: Diagnosis information of channel 1 to 8 or 9 to 16, depending on the SI control word before. SI command: Control Byte 2 programs the operation mode of Channels 9 to 16. Data Byte 2 gives the input information (on or off) for Channel 9 to 16. SO diagnosis: 16 bit diagnosis information (two bit per channel) of channels 9 to 16 Figure 15 Second Access Data Sheet 22 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device 6.1.4 Control- and Data Byte As mentioned above, the serial input information consist of a control byte and a data byte. Via the control byte, the specific mode of the device is programmable. Table 1 MSB C C C C C C C C D D D D D D D Control and Data Byte LSB D Control Byte Data Byte Ten specific control words are recognized, having the following functions: Table 2 No. 1 2 3 4 5 Commands Function ‘Full Diagnosis’ (two bits per channel) performed for channels 1 to 8. No change to output states. State of the eight parallel inputs and ‘1-bit Diagnosis’ for channel 1 to 8 is provided. Echo-function of SPI; SI direct connected to SO. 2) Control Byte Data Byte LLLL LLLL1) HHLL LLLL HLHL LLLL LLHH LLLL HHHH LLLL XXXX XXXX2) XXXX XXXX XXXX XXXX DDDDDDDD DDDDDDDD Channel 1 to 8 IN1 … 4 and serial data bits ‘OR’ed. ‘Full Diagnosis’ performed for channels 1 to 8. IN1 … 4 and serial data bits ‘AND’ed. ‘Full Diagnosis’ performed for channels 1 to 8. ‘Full Diagnosis’ (two bits per channel) performed for channels 9 to 16. No change to output states. State of the eight parallel inputs and ‘1-bit Diagnosis’ for channel 9 to 16 is provided. Echo-function of SPI; SI direct connected to SO. IN9 … 12 and serial data bits ‘OR’ed. ‘Full Diagnosis’ performed for channels 9 to 16. IN9 … 12 and serial data bits ‘AND’ed. ‘Full Diagnosis’ performed for channels 9 to 16. Channel 9 to 16 6 7 8 9 10 LLLL HHHH1) XXXX XXXX HHLL HHHH HLHL HHHH LLHH HHHH XXXX XXXX XXXX XXXX DDDDDDDD HHHH HHHH DDDDDDDD 1) Control Byte: Channel Selection via Bit 0 to 3 Bits 0 to 3 = L, Channels 1 to 8 selected Bits 0 to 3 = H, Channels 9 to 16 selected 2) Data Byte: ‘X’ means ‘don’t care’, because this data bits will be ignored. ‘D’ represents the data bits, either being H (= ON) or L (= OFF). Control words beside No. 1- 10 Not specified Control words are not executed (cause no function) and the shift register (SO Data) is reset after the CS signal (all ‘0’). Data Sheet 23 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device 6.1.5 Control Byte - Detailed description In the following section the different control bytes will be described. X used within the control byte means: Table 3 MSB X X X X L L L L Control Byte - Channel Group selection Comment Command is valid for Channels 1 to 8 X X X X H H H H Command is valid for Channels 9 to 16 Control Byte The following Control Byte descriptions are referring to the Overview Table 2. 6.1.5.1 Table 4 MSB L L Control Byte No.1 and 6 Control Byte No. 1 to 6 Comment L L X X X X Diagnosis only Control Byte By clocking in this control byte, it is possible to get pure diagnostic information (two bits per channel) in accordance with Figure 21. The data bits are ignored, so that the state of the outputs are not influenced. This command is only active once unless the next control command is again “Diagnosis only”. Diagnostic information can be read out at any time with no change of the switching conditions. CS SI SO LLLL HHHH LLLL HHHH XXXX HHHH XXXX HHHH SI command: Diagnosis only for channels 1 to 8. No change of the output states SO diagnosis: No fault, normal function of channels 1 to 8 or 9 to 16 depending on previous SI command CS SI SO LLLL HHHH XXXX XXXX DIAG_1 SI command: Diagnosis only for channels 9 to 16. No change of the output states ⇒ DIAG_2 provided during next chip select cycle SO diagnosis: 2 bit diagnosis performed for channels 1 to 8 Figure 16 Example for two Consecutive Chip Select Cycles Data Sheet 24 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device 6.1.5.2 Table 5 MSB H H Control Byte No. 2 and 7 Control Byte No. 2 and 7 Comment L L X X X X Reading back of the eight inputs and ‘1-bit Diagnosis’ provided Control Byte If the TLE6240GP is used as bare die in a hybrid application, it is necessary to know if proper connections exist between the µC-port and parallel inputs. By entering ‘HHLL’ as the control word, the first eight bits of the SO give the state of the parallel inputs, depending on the µC signals. By comparing the IN-bits with the corresponding µC-port signal, the necessary connection between the µC and the TLE6240GP can be verified - i.e. ‘read back of the inputs’. The second 8-bits fed out at the serial output contains ‘1-bit’ fault information of the outputs (H = no fault, L = fault). In the expression given below for the output byte, ‘FX’ is the fault bit for channel X. Table 6 MSB IN12 IN11 IN10 IN9 IN4 IN3 IN2 IN1 FX FX FX FX FX FX FX Serial Output LSB FX Parallel Input Signals Fault Bits Channel 1 to 8 or 9 to 16 CS SI SO HHLL HHHH LLLL HHHH XXXX HHHH XXXX HHHH SI command: No change of the output states; reading back of the 8 inputs and 1bit diagnosis for channels 1 to 8 SO diagnosis: No fault, normal function of channels 1 to 8 or 9 to 16 depending on previous SI command CS SI SO HHLL HHHH XXXX XXXX State of 8 par. inputs 1bit diagnosis Ch.1..8 SI command: No change of the output states; reading back of the 8 inputs and 1bit diagnosis for channels 9 to 16 provided during next chip select cycle SO diagnosis: State of eight parallel inputs and 1 bit diagnosis performed for channels 1 to 8 Figure 17 Example for two Consecutive Chip Select Cycles Data Sheet 25 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device 6.1.5.3 Table 7 MSB H L Control Byte No. 3 and 8 Control Byte No. 3 and 8 Comment H L X X X X Echo-function of SPI Control Byte To check the proper function of the serial interface the TLE6240GP provides a “SPI Echo Function”. By entering HLHL as control word, SI and SO are connected during the next CS period. By comparing the bits clocked in with the serial output bits, the proper function of the SPI interface can be verified. This internal loop is only closed once (for one CS period). The “Echo Function” does not cause any internal processing of data and after the next CS signal the SO data is ‘0’ (all registers reset). CS CS SI SO HLHL HHHH LLLL HHHH XXXX HHHH XXXX HHHH SI SI and SO int. connected Echo-function of SPI, i.e. SI directly connected to SO. SI information will not be accepted during this cycle. SO SI command: No change of the output states; Echo function of SPI SO diagnosis: No fault, normal function of channels 1 to 8 or 9 to 16 depending on previous SI command Figure 18 Echo-function of SPI 6.1.5.4 Table 8 MSB L L Control Byte No. 4 and 9 Control Byte No. 4 and 9 Comment H H X X X X OR operation, and ‘full diagnosis’ Control Byte With LLHH LLLL as the control word, each of the input signals IN1 to IN4 are ‘OR’ed with the corresponding SI data bits. With LLHH HHHH as the control word, each of the input signals IN9 to IN12 are ‘OR’ed with the corresponding SI data bits. Data Sheet 26 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device IN 1...4/9...12 ≥1 Serial Input, data bits 0...3 Output Driver Figure 19 OR Operation between IN and Serial Input This OR operation enables the serial interface to switch the channel ON, even though the corresponding parallel input might be in the off state. SPI Priority for ON-State Also parallel control of the outputs is possible without an SPI input. The OR-function is the default Boolean operation if the device restarts after a Reset, or when the supply voltage is switched on for the first time. If the OR operation is programmed it is latched until it is overwritten by the AND operation. 6.1.5.5 Table 9 MSB H H Control Byte No. 5 and 10 Control Byte No. 5 and 10 Comment H H X X X X AND operation, and ‘full diagnosis’ Control Byte With HHHH LLLL as the control word, each of the input signals IN1 to IN4 are ‘AND’ed with the corresponding SI data bits. With HHHH HHHH as the control word, each of the input signals IN9 to IN12 are ‘AND’ed with the corresponding SI data bits. IN 1...4/9...12 & Serial Input, data bits 0...3 Figure 20 AND Operation between IN and Serial Input Output Driver Data Sheet 27 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device The AND operation implies that the output can be switched off by the SPI data bit input, even if the corresponding parallel input is in the ON state. SPI Priority for OFF-State This also implies that the serial input data bit can only switch the output channel ON if the corresponding parallel input is in the ON state. If the AND operation is programmed it is latched until it is overwritten by the OR operation. 6.1.5.6 Example for an access to channel 1 to 8 LLHH LLLL HLLH LLLH: OR operation between parallel inputs and data bits, i.e channel 1, 5 and 8 will be switched on. The next command is now: LHHH LLLL HHHH LLLL LHHH LLLL as command word has no special meaning and will not be accepted. The output states will not be changed and the shift register will be reset (at the next CS SO Data all ‘0’). 6.2 Diagnostics For full diagnosis there are two diagnostic bits per channel configured as shown in Figure 21. Diagnostic Serial Data OUT SO 15 14 13 12 11 10 9 8 7 6- - - - - Ch.8 Ch.7 Ch.16 Ch.15 Ch.6 Ch.14 Ch.5 Ch.13 HH HL LH LL Normal function Overload, Shorted Load or Overtemperature Open Load Shorted to Ground Figure 21 • • • • Two Bits per Channel Diagnostic Feedback Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function. Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current limitation gets active, i.e. there is a overload, short to supply or overtemperature condition. Open load: An open load condition is detected when the drain voltage decreases below 3 V (typ.). LH bit combination is set. Short Circuit to GND: If a drain to ground short circuit exists and the drain to ground current exceeds 100 µA, short to ground is detected and the LL bit combination is set. A definite distinction between open load and short to ground is specified by design. The standard way of obtaining diagnostic information is as follows: Clock in serial information into SI pin and wait approximately 150 µs to allow the outputs to settle. Clock in the identical serial information once again - during this process the data coming out at SO contains the bit combinations representing the diagnosis conditions as described in Figure 21. Reset of the Diagnosis Register The diagnosis register is reset after reading the diagnosis data (after the falling CS edge). This is done for channels 1-8 and channels 9-16 separately depending on the previous command. Data Sheet 28 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device 6.2.1 Diagnosis Read-out options By means of the control byte it is possible either to: 1. control the outputs according to the data byte, as well as being able to read the diagnostic information (two bits per channel) 2. or purely get diagnostic information without changing the state of the outputs 3. or read back the parallel inputs plus a simple diagnosis (one bit per channel) 4. or SPI “Echo Function” as a diagnosis of proper SPI function. Diagnosis Read-Out Option 1): Serial Control of Outputs Table 10 MSB L L H H L L L L L H L H H L L OR-operation valid for channels 1 to 8 LSB L Control Byte Data Byte SI information: OR-operation valid for channels 1 to 8 SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle Table 11 MSB L L H H H H H H H L H L H L L OR-operation valid for channels 9 to 16 LSB L Control Byte Data Byte SI information: OR-operation valid for channels 9 to 16 SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle Table 12 MSB H H H H L L L L L H L H H L L AND-operation valid for channels 1 to 8 LSB L Control Byte Data Byte SI information: AND-operation valid for channels 1 to 8 SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle Table 13 MSB H H H H H H H H L H L H H L L AND-operation valid channels 9 to 16 LSB L Control Byte Data Byte SI information: AND-operation valid for channels 9 to 16 SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle Data Sheet 29 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device Diagnosis Read-Out Option 2): Diagnosis only Table 14 MSB L L L L L L L L X X X X X X X diagnosis - No change of output states LSB X Control Byte Data Byte SI information: Full diagnosis for channels 1 to 8. No change of output states SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle Table 15 MSB L L L L H H H H X X X X X X X diagnosis - No change of output states LSB X Control Byte Data Byte SI information: Full diagnosis for channels 9 to 16. No change of output states SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle Diagnosis Read-Out Option 3): Read back of parallel inputs plus simple diagnosis Table 16 MSB H H L L L L L L X X X X X X X No change of output states - read LSB X Control Byte Data Byte SI information: No change of the output states. Read back of parallel inputs and 1 bit diagnosis for channels 1 to 8 SO: State of eight inputs plus 1 bit diagnosis for channel 1 to 8 during next chip select cycle Table 17 MSB H H L L H H H H X X X X X X X No change of output states - read LSB X Control Byte Data Byte SI information: No change of the output states. Read back of parallel inputs and 1 bit diagnosis for channels 9 to 16 SO: State of eight inputs plus 1 bit diagnosis for channel 9 to 16 during next chip select cycle Diagnosis Read-Out Option 4): SPI Echo function Table 18 MSB H L H L L L L L X X X X X X X No change of output states - Echo LSB X Control Byte Data Byte Data Sheet 30 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Control of the Device SI information: Echo function of SPI interface. No change of the output states SO: During next chip select cycle the SI bits clocked in appear directly at SO because of an internal connection for this cycle Table 19 MSB H L No change of output states - Echo LSB H L H H H H X X X X X X X X Control Byte Data Byte SI information: Echo function of SPI interface. No change of the output states SO: During next chip select cycle the SI bits clocked in appear directly at SO because of an internal connection for this cycle CS SCLK SI SO C O 14 N 13 T 12 R 11 O 10 L 9 Byte 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 MSB 15 LSB Figure 22 Serial Interface Data Sheet 31 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Application Hints 7 Application Hints Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. 7.1 Application Circuits VS VBat 10K 47nF* I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SI SO CS CLK Micro Controller PRG FAULT RESET I/O I/O I/O I/O I/O I/O I/O I/O SO SI CS CLK OUTx OUTx OUTx TLE6240GP * Ceramic Capacitor located close to Power Device Application Circuit .vsd Figure 23 Application Circuit Data Sheet 32 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Application Hints 7.2 Engine Management Application TLE6240GP can be used in combination with Multichannel Switches for relays and general purpose loads. This arrangement covers the numerous loads to be driven in a modern Engine Management/Powertrain system. From 28 channels in sum 16 can be controlled direct in parallel for PWM applications. TLE 6240GP Application_Hint_EMS_FLEX.vsd Figure 24 Engine Management Application Data Sheet 33 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Application Hints 7.3 Daisy Chain Application Px .1 Px .2 CS CLK SO SI CS CLK SO SI CS CLK SO µC MTSR SI TL6240GP 16-folds MRST TL6240GP 16-folds TL6240GP 16-folds Figure 25 Daisy Chain Application Data Sheet 34 Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Package Outlines 8 Package Outlines 3.5 MAX. 3.25 ±0.1 11 ±0.15 1) B 0.25 +0.07 -0.02 0 +0.1 1.1 ±0.1 2.8 0.65 15.74 ±0.1 (Heatslug) 36x 0.25 M A B C 1.3 6.3 (Mold) 14.2 ±0.3 0.1 C Heatslug 0.95 ±0.15 0.25 B 0.25 +0.13 Bottom View 3.2 ±0.1 (Metal) 36 19 19 36 Index Marking 1 x 45˚ 1 18 10 15.9 ±0.1 1) (Mold) 1) A 13.7 -0.2 (Metal) 1 Heatslug Does not include plastic or metal protrusion of 0.15 max. per side 5.9 ±0.1 (Metal) 5˚ ±3˚ GPS09181 Figure 26 PG-DSO-36 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 35 Dimensions in mm Rev.3.3, 2010-02-15 TLE6240GP Smart 16-Channel Low-Side Switch Revision History 9 Version V3.3 Revision History Date 2010-02-15 Changes Template up-date ESD standard up-date Thermal Resistance parameters up-date Temperature range for functional range added Package name modified V3.3, 2010-02-15, up-date Data Sheet 36 Rev.3.3, 2010-02-15 Edition 2010-02-15 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2010. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.