TLE6288R_10

Data Sheet, Rev. 2.5, Oct. 2010 TLE6288R Smart 6 Channel Peak & Hold Switch Automotive Power TLE6288R Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 2 2.1 2.2 2.3 3 3.1 3.2 4 4.1 4.1.1 4.1.2 4.2 4.3 4.3.1 4.3.2 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 8 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 6 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gerneral Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Stage Control: Parallel Control and SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Regulator: Peak Current Control with Fixed Off-Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics: Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics: SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Commands, Values and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Assignment and Default Settings for Internal Logic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Input / Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply, Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zthjc Diagram Junction - Case for Single channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overload/Low Inductance Load Detection in Current Regulation Mode . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 11 13 14 14 14 15 15 16 17 18 19 21 22 24 24 24 25 26 27 27 27 29 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Sheet 2 Rev. 2.5, 2010-10-11 TLE6288R Features • • • 3 Channel high side with adjustable Peak & Hold current control 3 Channel high/low side configurable Protection – Overcurrent (current limitation) – Overtemperature – Overvoltage (active clamping) Diagnosis – Overcurrent – Overtemperature – Open load (Off-State) – Short to Ground (Off-state, lowside configuration) – Short to VB (Off-state, highside configuration) • Electrostatic discharge (ESD) protection of all pins Interface and Control • Green Product (RoHS compliant) – 16-Bit Serial Peripheral Interface (2 bit/CH) • AEC Qualified – Device programming via SPI – Separate diagnosis output for each CH (DIAG1 Application to 6) – General Fault Flag + Overtemperature Flag • Peak & Hold Loads (valves, coils) – Direct parallel control of all channels • Solenoids, Relays and Resistive Loads – General enable signal to control all channels • Fast protected Highside Switching simultaneously (PWM up to > 10 kHz) Low Quiescent Current Compatible with 3.3 V and 5 V microcontrollers • • • • General Description The TLE6288R is a 6-channel (150 mΩ) Smart Multichannel Switch in Smart Power Technology. The IC has embedded protection, diagnosis and configurable functions. Channels 1-3 are highside channels with integrated charge pump and can be programmed individually to do autonomous peak and hold current regulation with PWM. Channel 4-6 (also with integrated charge pump) can be configured to work as highside switch or lowside switch. This IC can be used to drive standard automotive loads in highside or lowside applications with switching frequencies up to 10 kHz. In addition the TLE6288R can be used to drive autonomously up to 3 inductive peak & hold (valves, coils) loads with programmable peak and hold current values. Table 1 Parameter Logic Supply voltage Product Summary Symbol Values 4.5 … 5.5 0.15 typ. @ 25 °C +55 -19 1.2 … 3.6 0.7 … 2 0 … 3.6 100 … 400 Package PG-DSO-36-54 3 Rev. 2.5, 2010-10-11 Unit V Ω V V A A ms μs VCC On resistance RDS(ON)1-6 Lowside clamping voltage Vcll(max) Highside clamping voltage Vclh(max) Peak current range Ipk Hold current range Ihd Peak time range Ip Fixed off time range Ifo Type TLE6288R Data Sheet TLE6288R Block Diagram 1 Block Diagram Reset Vcc VDO VCC VB Channel 3 Highside 300 m Ω Peak&Hold Channel 2 Highside 300 m Ω Peak&Hold Channel 1 Highside 300 m Ω Peak&Hold Channel 4 Highside/ Lowside 300 mΩ Channel 5 Highside/ Lowside 300 mΩ DOUT 3 / VB . Fault CLKProg IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 DIAG 1 . . . . . . . SOUT 3 DOUT 2 SOUT 2 DOUT 1 SOUT 1 DOUT 4 SOUT 4 DOUT 5 SOUT 5 DOUT 6 SOUT 6 Logic Driver Diagnosis DIAG 5 DIAG 6 Overtemp. SCLK Vcc Vcc GND . . GND Channel 6 Highside/ Lowside 300 mΩ CS SI SO . SPI Vcc Charge pump . FSIN GND VCP Figure 1 Data Sheet Block Diagram 4 Rev. 2.5, 2010-10-11 TLE6288R Pin Configuration 2 2.1 Pin Configuration Pin Assignment Figure 2 Pin Configuration PG-DSO-36-54 2.2 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Definitions and Functions Symbol SOUT4 DOUT4 DOUT1 SOUT1 IN4 IN1 DIAG1 DIAG2 DIAG3 DIAG4 DIAG5 DIAG6/Overtemp IN2 IN5 SOUT2 DOUT2 Function Source Output CH 4 (high/low side) Drain Output CH 4 (high/low side) Drain Output CH 1 (high side) Source Output CH 1 (high side) Control Input Channel 4 Control Input Channel 1 Diagnostic Output CH 1 Diagnostic Output CH 2 Diagnostic Output CH 3 Diagnostic Output CH 4 Diagnostic Output CH 5 Diagnostic Output CH 6 / Overtemp Control Input Channel 2 Control Input Channel 5 Source Output CH 2 (high side) Drain Output CH 2 (high side) 5 Rev. 2.5, 2010-10-11 Data Sheet TLE6288R Pin Configuration Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol DOUT5 SOUT5 SOUT3 DOUT3 VCP FSIN GND Fault IN3 IN6 Reset Function Drain Output CH 5 (high/low side) Source Output CH 5 (high/low side) Source Output CH 3 (high side) Drain Output CH 3 (high side) Charge Pump capacitor pin All Channels Enable/Disable Logic Ground General Fault Flag Control Input Channel 3 Control Input Channel 6 Reset pin (+ Standby Mode) Logic Supply Voltage (5 V) Supply pin for digital outputs SPI Serial Data Output Program pin of SPI Clock SPI Serial Clock SPI Chip Select SPI Serial Data Input Drain Output CH 6 (high/low side) Source Output CH 6 (high/low side) VCC VDO SO CLKProg SCLK CS SI DOUT6 SOUT6 2.3 Symbol Pin Description Description DOUT1-3 Drain of the 3 highside channels. These pins must always be connected to the same power (battery) supply line (VB). SOUT1-3 Source of the 3 highside channels. Outputs of the highside channels where the load is connected. DOUT4-6 Drain pins of the 3 configurable channels. In highside configuration they must be connected to the same voltage as DOUT1-3. In lowside configuration they are the output pins and connected to the load. SOUT4-6 Source of the 3 configurable channels. In highside configuration they are the outputs and connected to the load. In lowside configuration they must be connected with GND. IN1-6 GND FSIN Reset Parallel input pins for the 6 power outputs. These pins have an internal pull-down structure. Logic ground pin, the heat slug has to be connected to this potential. Disable pin. If the FSIN pin is in a logic low state, it switches all outputs OFF. The pin has an internal pull-up structure. Reset pin. When the reset is low all channels are off, the internal biasing is deactivated, all internal registers are cleared and the supply-current consumption is reduced (standby mode). The pin has an internal pull-up structure. General Fault pin. There is a general fault pin (open drain) which shows a high to low transition as soon as an error is latched into the diagnosis register. When the diagnosis register is cleared this flag is also reset (high ohmic). This fault indication can be used to generate a μC interrupt. Fault Data Sheet 6 Rev. 2.5, 2010-10-11 TLE6288R Pin Configuration Symbol Description CLKProg Programming pin for the SPI Clock signal. This pin can be used to configure the clock signal input of the SPI. In low state the SPI will read data at the rising clock edge and write data at the falling clock edge. In high state the SPI will read data at the falling clock edge and write data at the rising clock edge. The pin has an internal pull-down structure. DIAG1-5 DIAG6/ Overtemp VCP Parallel diagnostic pins (push-pull) change state according to the input signal of the corresponding channel. For further details refer to Chapter 4.3.1 Pin to connect the external capacitor of the integrated charge pump. Connect a ceramic capacitor with 47 nF between this pin and DOUT3 (VB). Supply pin of the push-pull digital output drivers. This pin can be used to vary the high-state output voltage of the SO pin and the DIAG1-6 pins. Logic supply pin. This pin is used to supply the integrated circuitry. Chip Select of the SPI (active low) Signal Output of the Serial Peripheral Interface Signal Input of the Serial Peripheral Interface. The pin has an internal pull-down structure. Clock Input of the Serial Peripheral Interface. The pin has an internal pull-up structure (if CLKProg = L) or an pull-down structure (if CLKProg = H). VDO VCC CS SO SI SCLK For more details about the SPI see Chapter 5. Data Sheet 7 Rev. 2.5, 2010-10-11 TLE6288R General Product Characteristics 3 3.1 General Product Characteristics Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 ⋅C to +150 ⋅C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Voltages 3.1.1 Power Supply Voltage 1 static dynamic: 1 min. 25 °C dynamic: Test cond. see Figure 3 Power Supply Voltage 2 Continuous Drain Source Voltage (lowside configuration) Continuous Source Voltage (highside configuration) 3.1.4 Input Voltage Parameter Symbol Limit Values Min. Max. 20 24 40 7 40 V DOUT1-3 DOUT1-32) DOUT1-32) VCC VDO DOUT - SOUT (channel 4 to 6) SOUT - GND (channel 4 to 6) IN1-6, Reset, FSIN, CS, SCLK, SI, CLKProg Fault DIAG1-6 SO VCP; no voltage must be applied between DOUT and SOUT; Channel 4 to 6 – – – Unit PIN / Conditions 3.1.2 3.1.3 VB VB VB VCC VDO VDSL VSH VIN -0.3 – – -0.3 – -9 -0.3 V V V VB VCC + 0.3 V 3.1.5 Output Voltage VOUT -0.3 VCC + 0.3 V 3.1.6 Currents 3.1.7 Output Voltage VCP – VB + 10 V Reverse Current (1 ms) Irev -4 – A Temperatures 3.1.8 3.1.9 3.1.10 Operating Temperature Storage Temperature ESD (Human Body Model) Tj Tstg VESDb -40 -55 – +150 +150 2000 °C °C V ESD Susceptibility C = 100 pF, R = 1.5 kΩ Applied to all terminals 3 times 3.1.11 ESD (Machine Model) C = 200 pF, R = 0 Ω Applied to all terminals 3 times VESDm – 250 V – 1) Not subject to production test, specified by design. 2) As long as max. junction temperature Tj is not exceeded. Attention: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data Sheet 8 Rev. 2.5, 2010-10-11 TLE6288R General Product Characteristics Attention: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 40V 10 times (once/ 30sec) 12V 160ms 350ms Figure 3 Test Condition 3.2 Pos. 3.2.1 3.2.2 3.2.3 Thermal Resistance Parameter Symbol Min. Junction to Case 1) 1) Limit Values Typ. Max. Unit Conditions – Junction to ambient RthjC RthjA 1 15.5 K/W K/W 2) 2) 3) 1) Not subject to production test, specified by design. 2) Channel 1-6 continously turned on, 0.8W power dissipation per channel 3) Specified RthjA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board ; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70μm Cu, 2 x 35μm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Further informations can be found in Chapter 7.2 Data Sheet 9 Rev. 2.5, 2010-10-11 TLE6288R Description 4 4.1 Description General Functional Description Channel 1 to 3 • • • • • High Side Configuration with Charge Pump On / off Current Control Peak & Hold Current Control with fixed off time, values adjustable by SPI Type of current control can be selected by SPI Peak Current,Peak Time, Hold Current and Off-Time can be selected by SPI to set average and ripple current for a given load (refer to Figure 6) Channel 4 to 6 • • Configurable as either High or Low Side switch (by SPI) On / Off operation 4.1.1 Output Stage Control: Parallel Control and SPI Control A Boolean operation (either AND or OR) is performed on each of the parallel inputs IN 1 … 6 and respective SPI data bits, in order to determine the states of the respective outputs. The type of Boolean operation performed is programmed via the serial interface. Both, parallel inputs and respective SPI databits are high active. IN 1…6 AND Output Driver OR Serial Input bits 6 -11 of command „Channels on / off „ Figure 4 Serial Input Bits 6-11 of Command “Channels on/off” Each output is independently controlled by an output latch and a common reset line FSIN, which disables all outputs. A logic high input ‘data bit’ turns the respective output channel ON, a logic low ‘data bit’ turns it OFF. Table 2 0 0 1 1 Truth Table SPI Bit 0 1 0 1 Output OR OFF ON ON ON Output AND OFF OFF OFF ON Parallel Input Data Sheet 10 Rev. 2.5, 2010-10-11 TLE6288R Description 4.1.2 • Current Regulator: Peak Current Control with Fixed Off-Time • • Hold only: When the channel is turned on externally (SPI or parallel input) the current rises to the programmed hold current level. Then the channel is internally turned off and a timer is started for a fixed off-time (e.g. 200 μs). After this time the channel is internally turned on again until the hold current level is reached again and so on. This regulation works automatically until the channel is turned of externally. Peak and hold mode with minimum peak time: When the channel is turned on the current rises to the programmed peak current level. Then the channel is internally turned off, the current regulator changes to hold current values and a timer is started for a constant off-time. After this time the channel is internally turned on again until the hold current value is reached and then again turned off for the fixed off time. This regulation works automatically until the channel is turned of externally. Peak and hold mode with programmed peak time: When the channel is turned on the current rises to the programmed peak current level. Then the channel is internally turned off and a timer is started for a fixed offtime. After this time the channel is internally turned on again until the peak current value is reached and then again turned off. This works until the programmed peak time is over. Then the current regulator changes to hold current values and works as described under “hold only”. Peak Current, Peak Time, Hold Current and fixed Off-Time can be set via SPI. To avoid regulation disturbances by current transients during switching (e.g. caused by ESD capacitors at the outputs) the current regulator has a “leading edge blanking” of typical 20 μs in all three regulation modes. After turning on the DMOS (internally or externally) the current regulation circuit is deactivated for the first 20 μs. This guarantees that switching of the DMOS itself or charging of small capacitors at the output (e.g. ESD) is not disturbing the current regulation. To detect shorted loads or low inductance loads in all three regulation modes a timer is started when a channel is turned on (tli). If the first rising edge of the load current reaches the programmed current level (peak or hold current depending on the configured current control mode) within this time a overload fault is reported (see Chapter 7.3). Figure 5 Simplified Functional Block Diagram Data Sheet 11 Rev. 2.5, 2010-10-11 TLE6288R Description Input Signal No Regulation Ihd Current defined only by load Hold only Ipk tfo Peak & Hold with min. peak time Ihd tfo tfo Ipk Peak and Hold with set peak time Ihd tp tfo Figure 6 Current Forms of the Different Current Control Modes of Channel 1-3 Data Sheet 12 Rev. 2.5, 2010-10-11 TLE6288R Description 4.2 Protection The TLE6288R has integrated protection functions1) for overload and short circuit (active current limitation), overtemperature, ESD at all pins and overvoltage at the power outputs (zener clamping). Overtemperature Behavior Each channel has an overtemperature sensor and is individually protected against overtemperature. As soon as overtemperature occurs the channel is immediately turned off. In this case there are two different behaviors of the affected channel that can be selected by SPI (for all channels generally): Autorestart: as long as the input signals of the channel remains on (e.g. parallel input high) the channel turns automatically on again after cooling down. Latching: After overtemperature shutdown the channel stays off until the this overtemperature latch is reset by a new L → H transition of the input signal. Note: These overtemperature sensors of the channels are only active if the channel is turned on. An additional overtemperature sensor is located in the logic of the device. It monitors permanently the IC temperature. As soon as the IC temperature reaches a specified level an overtemperature fault will be indicated. 1) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 13 Rev. 2.5, 2010-10-11 TLE6288R Description 4.3 Diagnostic The TLE6288R has a parallel diagnosis via 6 output pind (DIAG1 - DIAG6) and a serial diagnosis functionallity via SPI. 4.3.1 Parallel Diagnostic Functions Parallel diagnostic pins (push-pull) change state according to the input signal of the corresponding channel. As soon as an error occurs at the corresponding channel (overload and overtemperature is detected in on state and open load/switch bypass in off state) the DIAG output shows the inverted input signal. An fault is detected only if it lasts for longer than the fault filter time. The fault information is not latched in a register. If DIAG6 is configured as Overtemperature Flag: This is a general fault pin which shows a high to low transition as soon as an overtemperature error occurs for any one of the six channels (for longer than the fault filter time) or the IC logic. This fault indication can be used to differ between overload and overtemperature errors in one of the six channels or to detect a general IC overtemperature. 4.3.2 Electrical Characteristics: Diagnostic Functions Electrical Characteristics: Diagnostic Functions VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 4.3.1 Parameter Symbol Min. Open Load Detection Voltage VDS(OL) – Limit Values Typ. 5.5 Max. – V Unit Pin/ Comment – Conditions lowside configuration, V B = 12 V highside configuration, V B = 12 V 4.3.2 Open Load Detection Voltage VDS(OL) – 4.5 – V – 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 Output Open Load diagnosis Current Fault Filter Time Switch Bypass Detection Current Id(OL) tf(fault) Id(SB) -500 50 – 4 – -100 100 – – – -20 200 250 6 μA μs μA A μs – – – – VB = Vout = 12 V – – no regulation mode Overload Detection Threshold IDd(lim1-3) (Channel 1 to 3) Overload / low inductance load Detection time (Channel 1 to 3) tli tfo see current Chapter 7.3 control mode – – 4.3.8 Overload Detection Threshold IDd(lim 4-6) (Channel 4 to 6) 3 – 6 A Data Sheet 14 Rev. 2.5, 2010-10-11 TLE6288R SPI 5 SPI The SPI is a Serial Peripheral Interface with 4 digital pins and a 16-bit shift register. The SPI is used to configure and program the device, turn on and off channels and to read detailed diagnostic information. CS SCLK SI SO SPI Figure 7 Serial Peripheral Interface 5.1 SPI Signal Description CS - Chip Select. The system microcontroller selects the TLE6288R by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the μC and from the TLE6288R to the µC. • • CS = H: Any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS = H → L: – diagnostic information is transferred from the diagnosis register into the SPI shift register – serial input data can be clocked into the SPI shift register from then on – SO changes from high impedance state to logic high or low state corresponding to the SO bits LSB MSB internal logic registers CS SI Serial input data MSB first SO Serial output (diagnosis) MSB first 16 bit SPI shift register CS diagnosis register LSB MSB Figure 8 • • CS = L: SPI is working like a shift register. With each clock signal the state of the SI is read into the SPI shiftregister and one diagnosis bit is written out of SO. CS = L → H: – transfer of SI bits from SPI shift register into the internal logic registers – reset of diagnosis register if sent command was valid To avoid any false clocking the serial clock input pin SCLK should be logic high state (if CLKProg = L; low state if CLKProg = H) during high to low transition of CS. SCLK - Serial Clock. The serial clock pin clocks the internal SPI shift register of the TLE6288R. The serial input (SI) accepts data into the input SPI shift register on the rising edge of SCLK (if CLKProg = L; falling edge if CLKProg = H) while the serial output (SO) shifts diagnostic information out of the SPI shift register on the falling Data Sheet 15 Rev. 2.5, 2010-10-11 TLE6288R SPI edge (if CLKProg = L; rising edge if CLKProg = H) of serial clock. It is essential that the SCLK pin is in a logic high state (if CLKProg = L; low state if CLKProg = H) whenever chip select CS makes any transition. SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit (MSB) first. SI information is read in on the rising edge of SCLK (if CLKProg = L; falling edge if CLKProg = H). Input data is latched in the SPI shift register and then transferred to the internal registers of the logic. The input data consists of 16 bits, made up of 4 control bits and 12 data bits. The control word is used to program the device, to operate it in a certain mode as well as providing diagnostic information (see Chapter 5.5). SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit (MSB) first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin following the falling edge of SCLK (if CLKProg = L; rising edge if CLKProg = H). 5.2 Electrical Characteristics: SPI Timing Electrical Characteristics: SPI Timing VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 Parameter Serial Clock Frequency (depending on SO load) Serial Clock Period (1/fSCLK) Serial Clock High Time Serial Clock Low Time Enable Lead Time (falling edge of CS to falling edge of SCLK) Enable Lead Time (falling edge of CS to rising edge of SCLK) 5.2.6 Symbol Min. Limit Values Typ. – – – – – Max. 5 – – – – DC 200 50 50 200 Unit Pin/ Conditions Comment – – – – CLKProg = L fSCLK tp(SCLK) tSCLKH tSCLKL tleadL MHz – ns ns ns ns – – – – tleadH 200 – – ns – CLKProg = H Enable Lag Time (rising edge tlagL of SCLK to rising edge of CS) Enable Lag Time (falling edge tlagH of SCLK to rising edge of CS) 200 200 20 20 20 20 – – – – – – – – – – – – – – 200 ns ns ns ns ns ns ns – – – – – – – CLKProg = L CLKProg = H CLKProg = L CLKProg = H CLKProg = L CLKProg = H – 5.2.7 Data Setup Time (required time SI to rising of SCLK) Data Setup Time (required time SI to falling of SCLK) tSUL tSUH 5.2.8 Data Hold Time (rising edge of tHL SCLK to SI) Data Hold Time (falling edge of tHH SCLK to SI) 5.2.9 Disable Time1) tDIS Data Sheet 16 Rev. 2.5, 2010-10-11 TLE6288R SPI Electrical Characteristics: SPI Timing (cont’d) VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 5.2.10 Parameter Transfer Delay Time (CS high time between two accesses) Data Valid Time1) CL = 50 pF to 100 pF CL = 220 pF 2) Symbol Min. Limit Values Typ. – Max. – 200 Unit ns Pin/ Conditions Comment – – tdt 5.2.11 tvalid – – – – 120 150 ns – – 1) Not subject to production test, specified by design. 2) To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault filter time tf(fault)max = 200 μs. 5.3 SPI Diagnostics As soon as a fault occurs for longer than the fault filter time, the fault information is latched into the diagnosis register (and the Fault pin will change from high to low state). A new error on the same channel will overwrite the old error report. Serial data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially. If the sent command was valid (see Note in Chapter 5.5) the rising edge of CS will reset the diagnosis registers (except the channel OT flag) and restart the fault filter time. In case of an invalid command the device will ignore the data bits and the diagnosis register will not be reset at the rising CS edge. Diagnostic Serial Data Out SO MSB 15 14 13 12 11 10 9 8 7 6 5 Bit0 and Bit1 is always 1 4 3 2 1 0 LSB Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 IC Overtemperature Flag Channel Overtemperature Flag HH HL LH LL Figure 9 Normal function Overload, Shorted Load or Overtemperature Open Load Switch Bypassed Two Bits per Channel Diagnostic Feedback plus two Overtemperature Flags For Full Diagnosis there are two diagnostic bits per channel configured as shown in Figure 9. Diagnosis bit 0 and bit 1 are always set to 1. Data Sheet 17 Rev. 2.5, 2010-10-11 TLE6288R SPI Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function. Overload, Shorted Load or Overtemperature: HL is set when the current limitation gets active, i.e. there is a overload, short to supply or overtemperature condition. The second reason for this bit combination is overtemperature of the corresponding channel. In current regulation mode HL is also set if the load current reaches the programmed current value in a time shorter than the fixed off time (tfo). This detection is only performed at the first rising load current edge after a channel is turned on (for channel 1 to 3). See Chapter 7.3. Open load: LH is set when open load is detected (in off state of the channel). Switch Bypassed: • • Short to GND: in lowside configuration LL is set when this condition is detected. Short to Battery: in highside configuration LL is set when this condition is detected. Channel Overtemperature Flag: In case of overtemperature in any output channel in on state the overtemperature Flag in the SPI diagnosis register is set (change bit 3 from 0 to 1). This bit can be used to distinguish between Overload and Overtemperature (both HL combination) and is reset by switching OFF/ON the affected channel. In addition the DIAG6 / Overtemp pin is set low (if configured as Overtemp Flag). IC Overtemperature Flag: When the IC logic temperature exceeds typ. 170 °C the non-latching IC Overtemperature Flag will be set in the SPI diagnosis register (change bit 2 from 0 to 1). In addition the DIAG6 / Overtemp pin is set low (if configured as Overtemp. Flag). 5.4 SPI Commands, Values and Parameters The 16-bit SPI is used to program different IC functions and values, turn on and off the channels and to get detailed diagnosis information. Therefore 4 command bits and 12 data bits are used. CS SI SO 4 Bits Command 12 Bits Da ta Diagnosis ( Ch. 1 to 6) + 2 Temp. Flags SI command : 4 Command Bits program the operation mode of Channels 1 to 6. 12 Data Bits configure the device and give the input information (on or off) for Channel 1 to 6. SO diagnosis 16 bit diagnosis information (two bit per channel) of channels 1 to 6 plus two Overtemperature Flags Figure 10 Data Sheet 18 Rev. 2.5, 2010-10-11 TLE6288R SPI The following parameters and functional behavior can be programmed by SPI: • Current regulation mode (mode): for each of the 3 highside channels individually the operation mode can be set. – “no current regulation” – current regulation “hold only” – current regulation “peak & hold with minimum peak time” – current regulation “peak & hold with programmed peak time” Peak Current (Ipk): for each of the 3 highside channels individually the peak current value for P&H current regulation can be programmed. The current range is 1.2 A to 3.6 A. Fixed off time of the current regulator (tfo): for each of the 3 highside channels (Ch1 to Ch3) individually the fixed off time for all modes with current regulation can be programmed from 100 μs to 400 μs. Hold current (Ihd): for each of the 3 highside channels (Ch1 to Ch3) individually the hold current value for P&H and hold only current regulation can be programmed. The current range is 0.7 A to 2.0 A. Peak time (tp): for each of the 3 highside channels (Ch1 to Ch3) individually the peak time value for P&H current regulation can be programmed. The time range is 0.8 ms to 3.6 ms. Highside/Lowside configuration (H/L): Each of the 3 configurable channels (Ch4 to Ch6) can be programmed for use as Highside switch or Lowside switch. Open load and switch bypassed detection activated or deactivated (OL+SB): For each of the 3 configurable channels (Ch4 to Ch6) the open load and switch bypassed diagnosis can be deactivated. In lowside configuration the open load and the short to GND detection can be deactivated, in highside configuration the open load and short to battery detection. Boolean operation (OR/AND): For all channels generally the Boolean operation of the parallel input signal and the SPI bit of the corresponding channel can be defined. Overtemperature behavior (R/L): The overtemperature behavior of the channels can be programmed by SPI. Autorestart or latching overtemperature shutdown can be selected (for all channels the same behavior). DIAG6 or overtemperature flag (D/F): With this SPI bit the function of the DIAG6 / Overtemp pin is defined. This output can work as diagnosis output of channel 6 or as Overtemperature Flag. • • • • • • • • • 5.5 Table 3 Command SPI Commands Command Table MSB 14 1 0 0 0 0 1 13 0 0 1 1 0 12 0 1 0 1 0 11 X 10 X Mode Mode Mode 9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X LSB X X X X X X Set all to Default Config. Regulator 1 1 Config. Regulator 2 1 Config. Regulator 3 1 Config. Ch1 - Ch6 1 Ipk Ipk Ipk tfo tfo tfo Ihd Ihd Ihd tp tp tp X Ch6 Ch6 Ch5 Ch5 Ch4 Ch4 all all DIAG H/L OL+ H/L OL+ H/L OL+ OR/ R/L 6D/F SB SB SB AND Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 X X X X X X X X X X X X Channels on/off Diagnosis only 1 1 1 1 0 1 1 1 X X X X X X Data Sheet 19 Rev. 2.5, 2010-10-11 TLE6288R SPI Legend of SPI Command Table • Mode: Operation mode of the current regulator: – no regulation – hold only – peak & hold with minimum peak time – peak & hold with programmed peak time Ipk: Peak current values 1.2 A … 3.6 A Ihd: Hold current values 0.7 A … 2 A tp: Peak time value 0.8 ms … 3.6 ms tfo: Fixed off time value 100 μs … 400 μs H/L: Channel 4 to 6 in highside or lowside configuration OL+SB: open load detection and switch bypassed detection activated or deactivated OR/AND: Boolean Operation (parallel input and corresponding SPI Bit) R/L: Autorestart or Latching overtemperature behaviour D/F: DIAG6/Overtemp pin set as Diagnosis output of channel 6 or as Overtemperature Flag Ch1-Ch6: On/Off information of the output drivers (high active) • • • • • • • • • • Command Description Config. Regulator 1-3: With this command the values for the current regulation and the functional mode of the channel is written into the internal logic registers. Config. Ch1 to Ch6: This command writes the configuration data of the 3 configurable channels (4-6) and sets the Boolean operation and overtemperature behavior of all channels. It also sets the DIAG6/Overtemp. pin to Diagnosis of channel 6 or Overtemperature Flag. Set all to default: This command sets all internal logic registers back to default settings. Diagnosis only: When this command is sent the 12 data bits are ignored. The internal logic registers are not changed. Channels on/off: With this command the SPI bits for the ON/OFF information of the 6 Channels are set. Note: Specified control words (valid commands) are executed and the diagnosis register is reset after the rising CS edge. Not specified control words are not executed (cause no function) and the diagnosis register is not reset after the CS = L → H signal. Data Sheet 20 Rev. 2.5, 2010-10-11 TLE6288R SPI 5.6 Mode Bit Assignment and Default Settings for Internal Logic Registers 00 01 10 11 no current regulation hold only P&H minimum peak time P&H with programmed times 1.8 A 01 1.0 A 01 200 μs 01 1.2 ms 001 2.4 A 10 1.4 A 10 300 μs 10 1.6 ms 010 AND 1 Latch 1 Overtemp. Flag 1 Lowside 1 No 1 on 1 3.6 A 11 2.0 A 11 400 μs 11 2.0 ms 011 2.4 ms 100 2.8 ms 101 3.2 ms 110 3.6 ms 111 Peak Current (Ipk) 2 Bits Hold Current (Ihd) 2 Bits Fixed off Time (tfo) 2 Bits Peak Time (tp) 3 Bits Boolean operation 1 Bit Overtemp. behavior 1 Bit Diag6 / Overtemp 1 Bit Highside / Lowside 1 Bit Open Load & SB (4-6) 1 Bit Channels on / off 1 Bit 1.2 A 00 0.7 A 00 100 μs 00 0.8 ms 000 OR 0 Restart 0 Diag6 0 Highside 0 Yes 0 off 0 Default Settings are in bold print. Data Sheet 21 Rev. 2.5, 2010-10-11 TLE6288R SPI 5.7 CS SPI Timing Diagrams 0.7Vcc 0.2 Vcc tdt tSCKH tlagL 0.7Vcc SCLK tleadL tSUL tHL tSCKL 0.7Vcc 0.2Vcc SI 0.2Vcc Figure 11 Input Timing Diagram (CLKProg = L) SCLK tvalid 0.2 Vcc CS 0.2 Vcc tDis SO SO 0.7 Vcc 0.2 Vcc 0.7 Vcc 0.2 Vcc SO Figure 12 SO Valid Time Waveforms and Enable and Disable Time Waveforms (CLKProg = L) CS SCLK 4 control bit 12 data bit word 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 SI SO Co nt 14 rol 13 MSB 15 LSB 0 Figure 13 Serial Interface Data Sheet 22 Rev. 2.5, 2010-10-11 TLE6288R SPI CS 0.7Vcc 0.2 Vcc tSCKH tleadH tlagH 0.7Vcc 0.2Vcc tdt SCLK tSUH tSCKL tHH 0.7Vcc 0.2Vcc SI Figure 14 Input Timing Diagram (CLKProg = H) 0.7 V cc SCLK t valid CS 0.2 V cc t Dis SO SO 0.7 V cc 0.2 V cc 0.7 V cc 0.2 V cc SO Figure 15 SO Valid Time Waveforms and Enable and Disable Time Waveforms (CLKProg = H) CS SCLK 4 control bit 12 data bit rol 13 word 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 SI SO Co nt 14 MSB 15 LSB 0 Figure 16 Serial Interface Data Sheet 23 Rev. 2.5, 2010-10-11 TLE6288R Electrical Characteristics Input / Output Pins 6 6.1 Electrical Characteristics Input / Output Pins Power Supply, Reset Electrical Characteristics: Power Supply, Reset VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Parameter Power Supply Current 1 Power Supply Current 2 Power Supply Current in Standby Mode Minimum Reset Duration Wake-up time after reset Symbol Min. Limit Values Typ. – – – – – Max. 10 10 50 – 5 mA mA μA μs ms – – – 50 – Unit Pin/ Conditions Comment DOUT1-3 Ch1-Ch6: Off – IB ICC ICC + Ib tReset,min twakeup VCC VCC – – DOUT1-3, Reset = L – CCP = 10 nF 6.2 Power Outputs Electrical Characteristics: Power Outputs VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.11 6.2.12 6.2.13 Parameter On Resistance Forward Voltage Revers Diode Peak Current range Peak Current accuracy Hold Current range Hold Current accuracy Peak time range Peak time accuracy Fixed off Time range Fixed off Time accuracy Fixed off Time accuracy Output ON Delay time1 Output ON Rise time1 Symbol Min. Limit Values Typ. – – 1.2 … 3.6 – Max. 350 2 – ±15 ±20 ±15 ±20 – ±20 – ±30 ±20 10 10 mΩ V A % % A % % ms % μs % % μs μs – – – – – – – – – – – – – Unit Pin/ Conditions Comment DOUTx SOUTx SOUTx DOUTx – – – – – – – – – – – RDS(ON) VRDf Ipk Ipka Ihd Ihda tp tpa tfo tfoa tfoa tdON tr ID = 2.4 A VB = 1 0 V ID = -4 A Tj = 150 °C – Tj = 25, 150 °C Tj = -40 °C – 0.7 … 2 – – 0.8 … 3.6 – 100 … 400 – – – – Tj = 25, 150 °C Tj = -40 °C – – – 100 μs 200 μs 400 μs see Figure 17 see Figure 17 Data Sheet 24 Rev. 2.5, 2010-10-11 TLE6288R Electrical Characteristics Input / Output Pins Electrical Characteristics: Power Outputs (cont’d) VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 6.2.14 Parameter Output OFF Delay time Symbol Min. Limit Values Typ. – Max. 20 μs – Unit Pin/ Conditions Comment – HS- Mode LS- Mode see Figure 17 see Figure 17 Reset = L – – Refers to GND level Refers to GND level – – – tdOFF 6.2.15 6.2.16 6.2.17 6.2.18 6.2.19 6.2.20 6.2.21 6.2.22 6.2.23 Output OFF Fall time Leakage Current Leak Current in OFF (highside configuration) Leak Current in OFF (lowside configuration) Output Clamp Voltage (highside configuration) Output Clamp Voltage (lowside configuration) Current limitation (Channel 1 to 3) Current limitation (Channel 4 to 6) IC Overtemp. Warning1) Hysteresis tf – – – – – -19 40 4 3 160 – – – – – -14 – – – – 10 10 10 -250 500 -9 55 6 6 180 – μs μA μA μA V V A A °C °C – – SOUT1-6 DOUT4-6 SOUT1-6 DOUT4-6 – – – Iloff Iloff Vclh Vcll IDlim1-3 IDlim4-6 Tot Thys 1) Not subject to production test, specified by design. 6.3 Digital Inputs Electrical Characteristics: Digital Inputs VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 Parameter Input Low Voltage Input High Voltage Input Voltage Hysteresis Input pull-down current Input pull-up current Symbol Min. Limit Values Typ. – – 100 50 -50 Max. 1 – – 100 -20 V V mV μA μA – 2 – 20 -100 Unit Pin/ Conditions Comment all digit. inputs all digit. inputs all digit. inputs IN1-6; CLKProg Reset; FSIN – – – VINL VINH VINHys Ipd Ipu VIN = 5 V VIN = GND Data Sheet 25 Rev. 2.5, 2010-10-11 TLE6288R Electrical Characteristics Input / Output Pins Electrical Characteristics: Digital Inputs (cont’d) VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 6.3.6 Parameter SPI Input pull-down current Symbol Min. Limit Values Typ. 20 Max. 50 μA 10 Unit Pin/ Conditions Comment SI, SCLK VIN = 5 V (CLKProg = H) CS, SCLK VIN = GND (CLKProg = L) Ipd 6.3.7 SPI Input pull-up current Ipu -50 -20 -10 μA 6.4 Digital Outputs Electrical Characteristics: Digital Outputs VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 Parameter Symbol Min. SO Low State Output Voltage VSOL SO High State Output Voltage VSOH DIAG Low State Output Voltage DIAG High State Output Voltage Fault Low Output Voltage Fault Output leak Current – Limit Values Typ. – – – – – – Max. 0.4 – 0.4 – 0.4 1 V V V V V μA Unit Pin/ Conditions Comment SO SO DIAG1-6 DIAG1-6 Fault Fault VDO 0.4 V – ISOL = 2.5 mA ISOH = -2 mA IDIAGL = 50 μA IDIAGH = -50 μA VDIAGL VDIAGH Vol Ioh VDO 0.4 V – – Iout = 1 mA Output: OFF V(fault) = 5 V Input Voltage tdON tdOFF 70% 30% Output Voltage (Highside configuration) tr tf Figure 17 Turn on/off Timings with Resistive Load Data Sheet 26 Rev. 2.5, 2010-10-11 TLE6288R Application Information 7 7.1 Application Information Zthjc Diagram Junction - Case for Single channel operation 10 Zth(D, Pulse width) [K/W] 1 Dutycycle D 0,1 0,5 0,2 0,1 0,05 0,02 0,01 0,01 0,000001 0,00001 0,0001 0,001 0,01 0,1 Pulse width [s] Figure 18 • Zthjc Diagram Conditions for Figure 18 – Results based on FEM Simulations – Tcase = 125 °C – Single Channel operation, 0.8W power dissipation 7.2 Thermal Application Information All thermal resistance values in this document are data from FEM (Finite Element Modelling). The boundary conditions are chosen according to the JESD51 standard. Therefore, all values can be viewed as reliable and reproducible. The high effective thermal conductivity test PCB (2s2p) gives a near best case thermal performance value. compared to the single layer low effective thermal conductivity PCB (1s). It should be emphasized that values measured/simulated with these test boards cannot be used to directly predict any particular system application performance. In real applications, the RthjA can be influenced by the environment and PCB conditions. Thermal vias, application specific multi layer PCBs and a direct thermal connection to the ECU metal-case are often used to improve the thermal impedance RthjA. Data Sheet 27 Rev. 2.5, 2010-10-11 TLE6288R Application Information Figure 19 FE Model of the JEDEC 2s2p PCB Figure 20 Thermal via layout Figure 19 showes the Product TLE6288R on the 2s2p board used to specify the typical RthjA value in Chapter 3.2. In Figure 20, the thermal via layout according to JESD51-5 is shown. Data Sheet 28 Rev. 2.5, 2010-10-11 TLE6288R Application Information 7.3 Overload/Low Inductance Load Detection in Current Regulation Mode Input Signal Ipk / Ihd Load Current normal condition tli Ipk / Ihd tfo Overload / low inductance load detection Load Current low-inductance load tli Figure 21 tfo Data Sheet 29 Rev. 2.5, 2010-10-11 TLE6288R Package Outlines 8 Package Outlines 3.5 MAX. 3.25 ±0.1 11 ±0.15 1) B 0.25 +0.07 -0.02 0 +0.1 1.1 ±0.1 2.8 0.65 15.74 ±0.1 (Heatslug) 36x 0.25 M A B C 1.3 6.3 (Mold) 14.2 ±0.3 0.1 C Heatslug 0.95 ±0.15 0.25 B 0.25 +0.13 Bottom View 3.2 ±0.1 (Metal) 36 19 19 36 Index Marking 1 x 45˚ 1 18 10 15.9 ±0.1 1) (Mold) 1) A 13.7 -0.2 (Metal) 1 Heatslug Does not include plastic or metal protrusion of 0.15 max. per side 5.9 ±0.1 (Metal) 5˚ ±3˚ GPS09181 Figure 22 PG-DSO-36-54 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 30 Dimensions in mm Rev. 2.5, 2010-10-11 TLE6288R Revision History 9 Revision 2.2 2.3 2.4 Revision History Date Changes 2004-03-25 Preliminary Datasheet TLE6288R Vp2.2 2006-05-03 Formal changes, Thermal information added, Spec. values not changed 2007-08-08 RoHS-compliant version of the TLE6288R Page 3: “AEC qualified” and “RoHS” logo added, “Green Product (RoHS compliant)” and “AEC qualified” statement added to feature list, package names changed to RoHS compliant versions, package pictures updated Page 30: Package names changed to RoHS compliant versions, “Green Product” description added Revision History updated Legal Disclaimer updated 2010-10-11 Updated package type 2.5 Data Sheet 31 Rev. 2.5, 2010-10-11 Edition 2010-10-11 Published by Infineon Technologies AG 81726 Munich, Germany © 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.