TLE6361G_05

TLE 6361 G Multi-Voltage Processor Power Supply Data Sheet 1 1.1 • • • • • • • • Overview Features • • • • • • • • High efficiency regulator system Wide input voltage range, up to 60V Stand-by mode with low current consumption Suitable for standard 12V, 24V and 42V PowerNets Step down converter as pre-regulator: 5.5V / 1.5A Step down slope control for lowest EME Switching loss minimization Three high current linear post-regulators with selectable output voltages: 5V / 800mA 3.3V or 2.6V / 500mA 5V or 3.3V / 350mA Six independent voltage trackers (followers): 5V / 17mA each Stand-by regulator with 1mA current capability Three independent undervoltage detection circuits (e.g. reset, early warning) for each linear post-regulator Power on reset functionality Window watchdog triggered by SPI Tracker control and diagnosis by SPI All outputs protected against short-circuit Power-DSO-36 package Ordering Code Q 67007-A9466 Package P-DSO-36-12 Type TLE 6361 G SMD = Surface Mounted Device P-DSO-36-12 Data Sheet, Rev. 2.0 1 2005-03-01 TLE 6361 G 1.2 Short functional description The TLE 6361 G is a multi voltage power supply system especially designed for automotive applications using a standard 12V or 24V battery as well as the new 42V powernet. The device is intended to supply 32 bit micro-controller systems which require different supply voltage rails such as 5V, 3.3V and 2.6V. The regulators for external sensors are also provided. The TLE 6361 G cascades a Buck converter block with a linear regulator and tracker block on a single chip to achieve lowest power dissipation thus being able to power the application even at very high ambient temperatures. The step-down converter delivers a pre-regulated voltage of 5.5V with a minimum current capability of 1.5A. Supplied by this step down converter three low drop linear post-regulators offer 5V, 3.3V, or 2.6V of output voltages depending on the configuration of the device with current capabilities of 800mA, 500mA and 350mA. In addition the inputs of six voltage trackers are connected to the 5.5V bus voltage. Their outputs follow the main 5V linear regulator (Q_LDO1) with high accuracy and are able to drive a current of 17mA each. The trackers can be turned on and off individually by a 16 bit serial peripheral interface (SPI). Through this interface also the status information of each tracker (i.e. short circuit) can be read out. To monitor the output voltage levels of each of the linear regulators three independent undervoltage detection circuits are available which can be used to implement the reset or an early warning function. The supervision of the µC is managed by the SPI-triggered window watchdog. For energy saving reasons while the motor is turned off, the TLE 6361 G offers a standby mode, where the quiescent current does not exceed 30µA typically. In this stand-by mode just the stand-by regulator remains active. The TLE 6361 G is based on Infineon Power technology SPT  which allows bipolar , CMOS and Power DMOS circuitry to be integrated on the same monolithic circuitry. Data Sheet, Rev. 2.0 2 2005-03-01 TLE 6361 G 1.3 Pin configuration P-DSO-36-12 GND CLK CS DI DO ERR Q_STB Q_T1 Q_T2 Q_T3 Q_T4 Q_T5 Q_T6 Q_LDO3 R3 R2 R1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GND SLEW WAKE BOOST IN SW IN SW Bootstrap Q_LDO1 FB/L_IN FB/L_IN Q_LDO2 SEL CCP C+ CGND Figure 1 Pin Configuration (Top View), bottom heatslug and GND corner pins are connected Data Sheet, Rev. 2.0 3 2005-03-01 TLE 6361 G 1.4 Pin No. 1,18,19, 36 2 Pin definitions and functions Symbol GND Function Ground; to reduce thermal resistance place cooling areas on PCB close to this pins. Those pins are connected internally to the heatslug at the bottom. SPI Interface Clock input; clocks the shiftregister; CLK has an internal active pull down and requires CMOS logic level inputs;see also chapter SPI SPI Interface chip select input; CS is an active low input; serial communication is enabled by pulling the CS terminal low; CS input should only be switched when CLK is low; CS has an internal active pull up and requires CMOS logic level inputs ;see also chapter SPI SPI Interface Date input; receives serial data from the control device; serial data transmitted to DI is a 16 bit control word with the Least Significant Bit (LSB) being transferred first; the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see also chapter SPI SPI Interface Data output; this tristate output transfers diagnosis data to the controlling device; the output will remain 3stated unless the device is selected by a low on Chip-Select CS; see also the chapter SPI Error output; push-pull output. Monitors failures in parallel to the SPI diagnosis word, reset via SPI. ERR is a latched output. Standby Regulator Output; the output is active even when the buck regulator and all other circuitry is in off mode Voltage Tracker Output T1 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Voltage Tracker Output T2 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Voltage Tracker Output T3 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. CLK 3 CS 4 DI 5 DO 6 7 8 ERR Q_STB Q_T1 9 Q_T2 10 Q_T3 Data Sheet, Rev. 2.0 4 2005-03-01 TLE 6361 G 1.4 Pin No. 11 Pin definitions and functions (cont’d) Symbol Q_T4 Function Voltage Tracker Output T4 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Voltage Tracker Output T5 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Voltage Tracker Output T6 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Voltage Regulator Output 3; 5V or 3.3V output; ouput voltage is selected by pin SEL (see also 3.4.2); For stability a ceramic capacitor of 470nF to GND is sufficient. Reset output 3, undervoltage detection for output Q_LDO3; open collector output; an external pullup resistor of 10kΩ is required Reset output 2, undervoltage detection for output Q_LDO2; open collector output; an external pullup resistor of 10kΩ is required Reset output 1, undervoltage detection for output Q_LDO1 and watchdog failure reset; open collector output ; an external pullup resistor of 10kΩ is required Charge pump capacitor connection; Add the fly-capacitor of 100nF between C+ and CCharge pump capacitor connection; Add the fly-capacitor of 100nF between C+ and CCharge Pump Storage Capacitor Output; Add the storage capacitor of 220nF between pin CCP and GND. Select Pin for output voltage adjust of Q_LDO2 and Q_LDO3 (see also 2.2.2) Voltage Regulator Output 2; 3.3V or 2.6V output; output voltage is selected by pin SEL (see also 3.4.2); For stability a ceramic capacitor of 470nF to GND is sufficient. Feedback and Linear Regulator Input; input connection for the Buck converter output 12 Q_T5 13 Q_T6 14 Q_LDO3 15 R3 16 R2 17 R1 20 21 22 23 24 CC+ CCP SEL Q_LDO2 25, 26 FB/L_IN Data Sheet, Rev. 2.0 5 2005-03-01 TLE 6361 G 1.4 Pin No. 27 Pin definitions and functions (cont’d) Symbol Q_LDO1 Function Voltage Regulator Output 1; 5V output; acts as the reference for the voltage trackers.The SPI and window watchdog logic is supplied from this voltage. For stability a ceramic capacitor of 470nF to GND is sufficient. 28 Bootstrap Bootstrap Input; add the bootstrap capacitor between pin SW and pin Bootstrap, the capcitance value should be not lower than 2% of the Buck converter output capacitance SW Switch Output; connect both pins externally through short lines directly to the cathode of the catch diode and the Buck circuit inductance. Supply Voltage Input; connect both pins externally through short lines to the input filter/the input capacitors. Boost Input; for switching loss minimization connect a diode (cathode directly to boost pin) in series with a 100nF ceramic capacitor to the IN pin and from the anode of the diode to the buck converter output a 22Ω resistor. Recommended for 42V applications, in 12/24V applications connect boost directly to IN Wake Up Input; a positive voltage applied to this pin turns on the device Slew control Input; a resistor to GND defines the current slope in the buck switch for reduced EME 29, 31 30, 32 33 IN BOOST 34 35 WAKE SLEW Data Sheet, Rev. 2.0 6 2005-03-01 TLE 6361 G 1.5 Basic block diagram TLE 6361 Standby Regulator 2.5V Q_STB Boost SW 2* IN 2* BUCK REGULATOR Driver Bootstrap Slew OSZ PWM ErrorAmplifier Internal Reference feedback FB/L_IN 2* C+ Charge Pump C- Protection CCP Wake Power Down Logic SEL R1 Linear Reg. 1 Reset Logic Linear Reg. 2 Linear Reg. 3 Q_LDO1 R2 Q_LDO2 µ-controller / memory supply R3 Q_LDO3 ref Window Watchdog ref Tracker 5V Tracker 5V Tracker 5V Q_T1 Q_T2 CLK ref Q_T3 CS SPI 16 bit DI ref Tracker 5V Tracker 5V Tracker 5V Q_T4 Sensor supplies (off board supplies) ref Q_T5 DO ref Q_T6 ERR GND 4* Figure 2 Block Diagram Data Sheet, Rev. 2.0 7 2005-03-01 TLE 6361 G 2 Detailed circuit description In the following major buck regulator blocks, the linear voltage regulators and trackers, the undervoltage reset function, the watchdog and the SPI are described in more detail. For applications information e.g. choice of external components, please refer to section . 2.1 Buck Regulator The diagram below shows the internal implemented circuit of the Buck converter, i. e. the internal DMOS devices, the regulation loop and the other major blocks. IN 5V Int. voltage regulator Int. charge pump 14V 150µA to current sense amplifier 8 to 10V FB/L_IN C+ CCP Main switch ON/OFF Gate driver Main DMOS undervoltage lockout IN CBOOTSTRAP SW Divider switching frequency 330kHz Slope switch charge signal Slope DMOS BOOST Oscillator 1.4MHz Slope compensation Slope switch discharge signal Gate off signal from overtemp or sleep command Lowpass Voltage feedback amplifier Trigger for gate on PWM logic Slope logic Zero cross detection SW Current comparator Vref=6V Lowpass Trigger for gate off from current sensing Current sense amplifier + Delay unit Slope control SLEW external components pins Figure 3 Detailed Buck regulator diagram The 1.5A Buck regulator consists of two internal DMOS power stages including a current mode regulation scheme to avoid external compensation components plus additional blocks for low EME and reduced switching loss. Figure 3 indicates also the principle how Data Sheet, Rev. 2.0 8 2005-03-01 TLE 6361 G the gate driver supply is managed by the combination of internal charge pump, external charge pump and bootstrap capacitor. 2.1.1 Current mode control scheme The regulation loop is located at the left lower corner in the schematic, there you find the voltage feedback amplifier which gives the actual information of the actual output voltage level and the current sense amplifier for the load current information to form finally the regulation signal. To avoid subharmonic oscillations at duty cycles higher than 50% the slope compensation block is necessary. The control signal formed out of those three blocks is finally the input of the PWM regulator for the DMOS gate turn off command, which means this signal determines the duty cycle. The gate turn on signal is set by the oscillator periodically every 3µs which leads to a Buck converter switching frequency around 330kHz. With decreasing input voltage the device changes to the so called pulse skipping mode which means basically that some of the oscillator gate turn off signals are ignored. When the input voltage is still reduced the DMOS is turned on statically (100% duty cycle) and its gate is supplied by the internal charge pump. Below typical 4.5V at the feedback pin the device is turned off.During normal switching operation the gate driver is supplied by the bootstrap capacitor. 2.1.2 Start-up procedure To guarantee a device startup even under full load condition at the linear regulator outputs a special start up procedure is implemented. At first the bootstrap capacitor is charged by the internal charge pump. Afterwards the outpuput capacitor is charged where the driver supply in that case is maintained only by the bootstrap capacitor. Once the output capacitor of the buck converter is charged the external charge pump is activated being able to supply the linear regulators and finally the linear regulators are released to supply the loads. 2.1.3 Reduction of electromagnetic emission In figure 3 it is recognized that two internal DMOS switches are used, a main switch and an auxiliary switch. The second implemented switch is used to adjust the current slope of the switching current. The slope adjustment is done by a controlled charge and discharge of the gate of this DMOS. By choosing the external slew resistor appropriate the current transition time can be adjusted between 20ns and 100ns. 2.1.4 Reducing the switching losses The second purpose of the slope DMOS is to minimise the switching losses. Once being in freewheeling mode of the buck regulator the output voltage level is sufficient to force the load current to flow, the input voltage level is not needed in the first moment. By a feedback network consisting of a resistor and a diode to the boost pin (connection see Data Sheet, Rev. 2.0 9 2005-03-01 TLE 6361 G section ) the output voltage level is present at the drain of the switch. As soon as the voltage at the SW pin passes zero volts the handover to the main switch occurs and the traditional switching behaviour of the Buck switch can be observed. 2.2 Linear Voltage Regulators The Linear regulators offer voltage rails of 5V, 3.3V and 2.6V which can be determined by a hardware connection (see table at 2.2.2) for proper power up procedure. Being supplied by the output of the Buck pre-regulator the power loss within the three linear regulators is minimized. All voltage regulators are short circuit protected which means that each regulator provides a maximum current according to its current limit when shorted. Together with the external charge pump the NPN pass elements of the regulators allow low dropout voltage operation. By using this structure the linear regulators work stable even with a minimum of 470nF ceramic capacitors at their output. Q_LDO1 has 5V nominal output voltage, Q_LDO2 has a hardware programmable output voltage of 3.3V or 2.6V and Q_LDO3 is programmable to 5V or 3.3V (see 2.2.2). All three regulators are on all the time, if one regulator is not needed a base load resistor in parallel to the output capacitance for controlled power down is recommended. 2.2.1 Startup Sequence Linear Regulators When acting as 32 bit µC supply the so-called power sequencing (the dependency of the different voltage reails to each other) is important. Within the TLE 6361 G the following Startup-Sequence is defined (see also figure 4): VQ_LDO2 ≤ VQ_LDO1; VQ_LDO3 ≤ VQ_LDO1 with VQ_LDO1=5V, VQ_LDO2 = 2.6V and VQ_LDO3 = 3.3V and VQ_LDO2 ≤ VQ_LDO1 with VQ_LDO1=5V, VQ_LDO2 = 2.6V/3.3V and VQ_LDO3 = 5V The power sequencing refers to the regulator itself, externally voltages applied at Q_LDO2 and Q_LDO3 are not pulled down actively by the device if Q_LDO1 is lower than those outputs. That means for the power down sequencing if different output capacitors and different loads at the three outputs of the linear regulators are used the voltages at Q_LDO2 and Q_LDO3 might be higher than at Q_LDO1 due to slower discharging. To avoid this behaviour three Schottky diodes have to be connected between the three outputs of the linear regulators in that way that the cathodes of the diodes are always connected to the higher nominal rail. Data Sheet, Rev. 2.0 10 2005-03-01 TLE 6361 G Power Sequencing VFB/L_IN VLDO_EN t VQ_LDO1 5V VRth5 3.3V 2.6V t VQ_LDO2 (2.6V Mode) 0.7V 2.6V VRth2.6 5V LDO 5V LDO 0.7V t VQ_LDO3 (3.3V Mode) 5V LDO 3.3V VRth3.3 +/- 50mV 5V LDO +/- 50mV t Figure 4 Power-up and -down sequencing of the regulators 2.2.2 Q_LDO2 and Q_LDO3 output voltage selection* To determine the output voltage levels of the three linear regulators, the selection pin (SEL, pin 23) has to be connected according to the matrix given in the table below. Definition of Output voltage Q_LDO2 and Q_LDO3 Select Pin SEL connected to GND Q_LDO1 Q_LDO2 Q_LDO2 Q_LDO3 output voltage output voltage 3.3 V 2.6 V 2.6 V 5V 3.3 V 5V * for different output voltages please refer to the multi voltage supply TLE6368 Data Sheet, Rev. 2.0 11 2005-03-01 TLE 6361 G 2.3 Voltage Trackers For off board supplies i.e. sensors six voltage trackers Q_T1 to Q_T6 with 17mA output current capability each are available. The output voltages match Q_LDO1 within +5 / -15mV. They can be individually turned on and off by the appropriate SPI command word sent by the microcontroller. A ceramic capacitor with the value of 1µF at the output of each tracker is sufficient for stable operation without oscillation. The tracker outputs can be connected in parallel to obtain a higher output current capability, no matter if only two or up to all six trackers are tied together. For uniformly distributed current density in each tracker internal balance resistors at each output are foreseen internally. By connecting twice three trackers in parallel two sensors with more than 50mA each can be supplied, all six in parallel give more than 100mA. The tracker outputs can withstand short circuits to GND or battery in a range from -4 to +40V. A short circuit to GND at is detected and indicated individually for each tracker in the SPI status word. Also an open load condition might be recognised and indicated as a failure condition in the SPI status word. A minimum load current of 2mA is required to avoid open load failure indication. In case of connecting several trackers to a common branch balancing currents can prevent proper operation of the failure indication. 2.4 Standby Regulator The standby regulator is an ultra low power 2.5V linear voltage regulator with 1mA output current which is on all the time. It is intended to supply the microcontroller in stop mode and requires then only a minimum of quiescent current ( 1/48 of the actual OW/CW time between a ’Watchdog disable’ and ’Watchdog enable’ SPI-command should be maintained. This allows the internal Watchdog counters to be resetted. Thus after the enable command the Watchdog will start properly with a full CW of the adjusted length. Data Sheet, Rev. 2.0 14 2005-03-01 TLE 6361 G Perfect triggering after Power on Reset VQ_LDO1 VRth1 1V t R1 tRES t Watchdog window tCW tSR CW OW CW OW CW CW OW t CS with WDtrig=1 t ERR t Incorrect triggering Watchdog window CW OW t CS with WDtrig=1 1) 2) t 1) Pretrigger 2) Missing trigger Legend: OW = Open window CW = Closed window Figure 7 Window watchdog timing Figure 7 gives some timing information about the window watchdog. Looking at the upper signals the perfect triggering of the watchdog is shown. When the 5V linear regulator Q_LDO1 reaches its reset threshold, the reset delay time has to run off before Data Sheet, Rev. 2.0 15 2005-03-01 TLE 6361 G the closed window (CW) starts. Then three valid watchdog triggers are shown, no effect on the reset line and/or error pin is observed. With the missing watchdog trigger signal the error signal turns low immediately where the reset is asserted after another delay of half the closed window time. Also shown in the figure are two typical failure modes, one pretrigger and one missing signal. In both cases the error signal will go low immediately the failure is detected with the reset following after the half closed window time. 2.10 Overtemperature Protection At a chip temperature of more than 130° an error and temperature flag is set and can be read through the SPI. The device is switched off if the device reaches the overtemperature threshold of 170°C. The overtemperature shutdown has a hysteresis to avoid thermal pumping. 2.11 Power Down Mode The TLE 6361 G is started by a static high signal at the wake input or a high pulse with a minimum of 50µs duration at the Wake input (pin 34). Voltages in the range between the turn on and turn off thresholds for a few 100µs must be avoided! By SPI command (“Sleep”-bit, D8, equals zero) all voltage regulators including the switching regulator except the standby regulator can be turned off completely only if the wake input is low. In the case the Wake input is permanently connected to battery the device cannot be turned off by SPI command, it will always turn on again. For stable “on” operation of the device the “Sleep”-bit, D8 has to be set to high at each SPI cycle! When powering the device again after power down the status of the SPI controlled devices (e.g. trackers, watchdog etc.) depends on the output voltage on Q_LDO1. Did the voltage at Q_LDO1 decrease below 3.3V the default status (given in the next section) is set otherwise the last SPI command defines the status. 2.12 Serial Peripheral Interface A standard 16bit SPI is available for control and diagnostics. It is capable to operate in a daisy chain. It can be written or read by a 16 bit SPI interface as well as by an 8 bit SPI interface. The 16-bit control word (write bit assignment, see figure 8) is read in via the data input DI, synchronous to the clock input CLK supplied by the µC. The diagnosis word appears in the same way synchronously at the data output DO (read bit assignment, see figure 9), so with the first bit shifted on the DI line the first bit appears on the DO line. The transmission cycle begins when the TLE 6361 G is selected by the “not chip select” input CS (H to L). After the CS input returns from L to H, the word that has been read in at the DI line becomes the new control word. The DO output switches to tristate status at Data Sheet, Rev. 2.0 16 2005-03-01 TLE 6361 G this point, thereby releasing the DO bus circuit for other uses. For details of the SPI timing please refer to figures 10 to 13. The SPI will be reset to default values given in the following table “write bit meaning” if the RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V). The reset will be active as long as the power on reset is present so during the reset delay time at power up no SPI commands are acceptable. The register content of the SPI - including watchdog timings and reset delay timings - is maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not decrease below 3.3V). 2.12.1 Write mode The following tables show the bit assignment to the different control functions, how to change settings with the right bit combination and also the default status at power up. 2.12.2 BIT Name Default Write mode bit assignment DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D 15 WD_OF NOT F1 assigned T1control T2control T6control T4control T5control T6control sleep WD_OF F2 reset 1 reset 2 WD 1 WD 2 WD_OF WD-Trig F3 1 X 0 0 0 0 0 0 1 1 0 0 0 0 1 0 Figure 8 Write Bit assignment Write Bit meaning Function Not assigned Tracker 1 to 6 - control: turn on/off the individual trackers Bit D1 D2 D3 D4 D5 D6 D7 D8 Combination X 0: OFF 1: ON Default X 0 Power down: send device to sleep 0: SLEEP 1: NORMAL 1 Data Sheet, Rev. 2.0 17 2005-03-01 TLE 6361 G Write Bit meaning Function Reset timing: Reset delay time tRES valid at warm start Bit D10D11 Combination 00: 64ms 10: 32ms 01: 16ms 11: 8ms 00: 128ms 10: 64ms 01: 32ms 11: 16ms 010: OFF 1xx: ON x0x: ON xx1: ON Default 00 Window watchdog timing: Open window time tOW and closed window time tCW valid at warm start Window watchdog function: Enable /disable window watchdog D12D13 00 D0D9D14 111 Window watchdog trigger: Enable / disable window watchdog trigger D15 0: not triggered 1 1: triggered 2.12.3 Read mode Below the status information word and the bit assignments for diagnosis are shown. 2.12.3.1 Read mode bit assignment BIT Name Default DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D 15 ERROR temp_ warn T1status T2status T3status T4status T5status T6status RAM Good 1 RAM Good 2 WD Window R-Error1 R-Error2 R-Error3 WD Error DC/DC status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 9 Read Bit assignment Error bit D0: The error bit indicates fail function and turns high if the temperature prewarning, the watchdog error is active, further if one RAM good indicates a cold start or if a voltage tracker does not settle within 1ms when it is turned on. In addition to the error indication by software the ERR pin atcs as a hardware error flag. Data Sheet, Rev. 2.0 18 2005-03-01 TLE 6361 G Read Bit meaning Function Error indication, explanation see below this table Overtemperature warning Status of Tracker Output Q_T[1:6],only if output is ON Type Latched Bit D0 Combination Default 0: normal operation 0 1: fail function 0: normal operation 0 1: prewarning 1: settled output voltage 0:Tracker turned off or shorted output. Also open load may possibly be indicated as 0.1) 0: cold start 1: warm start 0: cold start 1: warm start 0: open window 1: closed window 0 Not latched D1 Not latched D2 D3 D4 D5 D6 D7 Indication of cold start/ warm start, Q_LDO1 Indication of cold start/ warm start, Q_LDO2 Indication for open or closed window Reset condition at output Q_LDO1 Reset condition at output Q_LDO2 Reset condition at output Q_LDO3 Watchdog Error DC/DC converter status 1) Latched Latched D8 D9 0 0 0 Not latched D10 Not latched D11 Not latched D12 Not latched D13 0: normal operation 0 1: Reset R1 0: normal operation 0 1: Reset R2 0: normal operation 0 1: Reset R3 0: normal operation 1: WD error 0: off 1: on 0 1 Latched D14 Not latched D15 Min. load current to avoid ’0’ signal caused by open load is 2mA. Data Sheet, Rev. 2.0 19 2005-03-01 TLE 6361 G 2.12.4 SPI Timings CS High to Low & rising edge of CLK: DO is enabled. Status information is transferred to Output Shift Register CS CS Low to High: Data from Register are transferred to e.g. Trackers time CLK 0 1 2 3 13 14 15 0 1 Data In (N) DI D0 D1 D2 D3 D13 D14 D15 Data In (N+1) D0 + D1 + DI: Data will be accepted on the falling edge of CLK-Signal Data Out (N-1) DO D0 D1 D2 D3 D13 D14 D15 Data Out (N) D0 D1 DO: State will change on the rising edge of CLK-Signal e.g. Trackercontrol Setting (N-1) Setting (N) e.g. Trackerstatus Status (N-1) Status (N) Figure 10 SPI Data Transfer Timing Data Sheet, Rev. 2.0 20 2005-03-01 TLE 6361 G Figure 11 SPI-Input Timing trIN tfIN