TLE7233G

Datasheet, Rev. 1.0, February 2008 TLE7233G SPIDER - 4 channel low side driver with limp home Automotive Power SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 2 2.1 3 3.1 3.2 4 4.1 4.2 4.3 5 5.1 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 8 8.1 8.2 9 9.1 9.2 9.3 9.4 9.5 10 11 12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Voltage and current naming definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Limp Home Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 15 16 18 18 18 18 19 Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Open Load Diagnosis timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Electrical Characteristics Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 23 24 26 27 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Datasheet 2 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G TLE7233G 1 Features • • • • • • • • • Overview 4 channel low side relay driver 8 bit SPI for diagnostics and control SPI providing Daisy Chain Capability Limp Home functionality Very wide range for digital Supply Voltage Four input pins provide flexible and straightforward PWM operation Stable behavior at Under Voltage Green Product (RoHS compliant) AEC Qualified PG-SSOP-24-5 Table 1 Product Summary Digital supply voltage Analog supply voltage ON State resistance at Tj = 150°C for each channel Nominal load current Overload switch off threshold Output leakage current per channel at 25 °C Drain to Source clamping voltage SPI clock frequency Diagnostic Features • • • • Latched diagnostic information via SPI Over temperature monitoring Over load detection in ON state Open load detection in OFF state VDD VDDA RDS(ON) IL (nom,min) ID (OVL,max) ID (STB,max) VDS(AZ) fSCLK 3.0 V ... 5.5 V 4.5 V ... 5.5 V 2.2 Ω 390 mA 950 mA 1 µA 41 V 5 MHz Type TLE7233G Datasheet Package PG-SSOP-24-5 3 Marking TLE7233G Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Overview Protection Functions • • • • Short circuit Over load Over temperature Electrostatic discharge (ESD) Application • • All types of resistive, inductive and capacitive loads Especially designed for driving relays in automotive applications Description The TLE7233G is a four channel low-side relay switch (1 Ω per channel) in PG-SSOP-24-5 package providing embedded protective functions. It is especially designed as a relay driver for automotive applications. The 8 bit serial peripheral interface (SPI) is provided for control and diagnostics of the device and the loads. The SPI interface provides daisy-chain capability. The TLE7233G is equipped with four input pins that can be individually routed to the output control of their corresponding channel and therefore offer complete flexibility in design and PCB layout. The input multiplexer is controlled via SPI. A limp home pin (LHI) provides a simple use of the input pins; this enables a direct connection between the input pins and their corresponding outputs. The limp home function works under VDDA in order to ensure functionality even with a missing digital supply. The device provides many diagnostics of the load enabling both open load and short circuit detection. The SPI diagnostic bits indicate any eventual latched fault condition. Each output stage is protected against short circuit. In case of over load, the affected channel switches off. Temperature sensors are available for each channel in order to protect the device against over temperature. The power transistors are made of N-channel vertical power MOSFETs. The inputs CMOS compatible referenced to Ground. The device is monolithically integrated in Smart Power Technology. Datasheet 4 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Block Diagram 2 Block Diagram RST VDD VDDA OUT0 IN0 IN1 IN2 IN3 LHI CS SCLK SI SO diagnostic register SPI input register control, diagnostic and protective functions input logic temperature sensor short circuit detection gate control open load detection OUT1 OUT2 OUT3 GND Overview_GS.emf Figure 1 Block Diagram Datasheet 5 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Block Diagram 2.1 Voltage and current naming definition Following figure shows all the terms used in this datasheet, with associated convention for positive values. Idda VDDA V DD VRS T V IN3 VIN2 V IN1 VIN0 V LHI VCS Idd IRS T I IN3 I IN2 I IN1 I IN0 I LHI ICS IS CLK VDDA VDD RST IN3 IN2 IN1 IN0 LHI CS SCLK SI SO GND I GND OUT0 OUT1 OUT2 OUT3 I D0 I D1 I D2 I D3 VDS 3 VDS 1 VDS 2 VDS 0 V bat VS CLK IS I VSI VSO IS O Terms_GS.emf Figure 2 Terms In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS0 … VDS3). All SPI register bits are marked as follows: PARAMETER (e.g. IN0). In SPI register description, the values in bold letters (e.g. 0) are default values. Datasheet 6 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Pin Configuration 3 3.1 Pin Configuration Pin Assignment (top view) SUB SUB OUT3 OUT2 VDD GND VDDA LHI OUT1 OUT0 SUB SUB 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 n.c. SCLK SO SI IN3 GND IN2 IN1 IN0 CS RST n.c. PG-SSOP-24 .emf Figure 3 Pin Configuration 3.2 Pin 5 7 6,19 1,2,11, 12 10 9 4 3 Inputs 16 17 IN0 IN1 Pin Definitions and Functions Symbol I/O 1) Function Digital Supply Voltage; Connected to 5V Voltage with Reverse protection Diode and Filter against EMC Analog Supply Voltage; Ground; common ground for digital, analog and power Substrate; shorted to die pad,can be left not connected or used for thermal connection and shorted to ground Power Supply VDD VDDA GND SUB Power Stages OUT0 OUT1 OUT2 OUT3 O O O O I I Output Channel 0; Drain of power transistor channel 0 Output Channel 1; Drain of power transistor channel 1 Output Channel 2; Drain of power transistor channel 2 Output Channel 3; Drain of power transistor channel 3 PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open. PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open. 7 Rev. 1.0, 2008-02-28 Datasheet SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Pin Configuration Pin 18 20 8 14 SPI 15 23 21 22 Others 13,24 n.c. not connected; pin not used 1) O: Output, I: Input, PD: pull-down resistor integrated, PU pull-up resistor integrated Symbol IN2 IN3 LHI RST CS SCLK SI SO I/O I I I I I I I O 1) Function PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open. PD Control Input; Digital input 3.3 V logic. In case of not used keep open. PD Limp Home; Digital input 3.3 V or 5V. In case of not used keep open. PD Reset input pin; Digital input 3.3 V or 5V. Low active PU SPI chip select; Digital input 3.3 V or 5V.Low active PD serial clock; Digital input 3.3 V or 5V. PD serial data in; Digital input 3.3 V or 5V. serial data out; Digital input 3.3 V or 5V. Datasheet 8 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G General Product Characteristics 4 4.1 General Product Characteristics Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V. All voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Power Supply 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 Digital supply voltage Analog supply voltage Load current Max. 5.5 5.5 0.5 36 41 – – EAR Unit Conditions VDD VDDA ID -0.3 -0.3 -0.5 – V V A V V mJ – – – – active clamped 2) Power Stages Output voltage for short circuit protection VD (single pulse) Voltage at power transistor Maximum energy dissipation one channel VDS EAS single pulse single pulse 65 30 Tj(0) = 85 °C ID(0) = 0.35 A Tj(0) = 150 °C ID(0) = 0.25 A Tj(0) = 150 °C ID(0) = 0.25 A ID(0) = 0.17 A repetitive (1 · 104 cycles) repetitive (1 · 106 cycles) Logic Pins 4.1.7 4.1.8 4.1.9 4.1.10 4.1.11 4.1.12 4.1.13 4.1.14 4.1.15 4.1.16 Voltage at input pins Voltage at LHI pin Voltage at reset pin Voltage at chip select pin Voltage at serial clock pin Voltage at serial input pin Voltage at serial output pin Junction Temperature during operation Storage Temperature ESD Resistivity Output Input / SPI – – VIN0..3 VLHI VRST VCS VSCLK VSI VSO 18 13 5.5 5.5 V V V V V V V °C °C kV -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 -55 – – 3) 3) 3) 3) 3) VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 150 150 Temperatures Tj Tstg VESD – – HBM4) ESD Susceptibility -4 -2 4 2 1) Not subject to production test, specified by design. 2) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse 3) VDD + 0.3 V < 5.5 V Datasheet 9 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G General Product Characteristics 4) ESD susceptibility, HBM according to EIA/JESD 22-A114B Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Pos. 4.2.1 4.2.2 4.2.3 4.2.4 Functional Range Parameter Digital supply voltage Analog supply voltage Digital supply current all channels ON Symbol Min. Limit Values Max. 5.5 5.5 0.5 5 V V mA mA – – – – 3. 0 4.5 – – Unit Conditions VDD VDDA IDD(ON) Analog supply current all channels IDDA(ON) ON Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. 4.3.5 4.3.6 Parameter Junction to Soldering Point Symbol Min. Limit Values Typ. – Max. 29 K/W pin 2,6, 11, 191) – Unit Conditions 1)2) Junction to Ambient – 47 – K/W 1) Specified RthJSP value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature). Ta = 25 °C. LS0 to LS3 are dissipating 1 W power (0.25 W each). RthJSP RthJA 2) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The product (Chip+Package PG-SSOP-24) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Ta = 25 °C, LS1 to LS3 are dissipating 1 W power (0.25 W each). Datasheet 10 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Power Supply 5 Power Supply The TLE7233G is supplied by two power supply lines VDD and VDDA. The digital power supply line VDD is designed to be functional at a very wide voltage range. The analog power supply VDDA supports 5 V supply. Power-on reset functions have been implemented for both supply lines. After start-up of the power supply, all SPI registers are reset to their default values and the device remains in idle mode. Capacitors at pins VDD - GND and VDDA - GND are recommended. A reset pin is available. At low logic level at this pin, all registers are set to their default values and the quiescent supply currents are minimized. The VDD supply line is used for the I/O buffer circuits of the SPI pins, therefore the voltage on the SO pin is always related to this supply voltage. A capacitor between pins VDD and GND is recommended (especially in case of EMI). To enable the Daisy chain functionality it is necessary to have VDD and VDDA in the specified functional range. The device provides a sleep mode to minimize current consumption, which also resets the register banks. It is controlled by a low active reset pin (RST) which disables the device and minimize the current consumption. The table below gives an overview of the different power modes. Table 2 Power modes1) RESET VDD (low active) low high X X ON X ON Power mode State Description SLEEP IDLE Device at minimum current consumption Device operational, all channels OFF no diagnosis activated VDDA X ON ON ON SCLK 0 Hz 0 Hz X 5 MHz (max) LHI low low high low LIMP HOME Device in Limp home mode ON Device operational with enabled channels and high diagnostic currents active 1) low: pin input is digital low, high: pin input is digital high, X: pin state don’t care, ON: voltage on this analog supply pin is in the specified functional range Datasheet 11 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Power Supply 5.1 Limp Home Mode The TLE7233G offers the capability of driving dedicated channels during eventual fail-safe operation of the system. This limp home mode is activated by a high signal at pin LHI. In this mode, the SPI registers are reset and the input pins are directly routed to their corresponding channels, see Table 3 for details. Furthermore, the SPI is ignored and all input pin are referred to VDDA in order to ensure a defined operation mode if the digital supply or the microcontroller fail. A high signal on LHI overrides a Reset signal on RST. In case of a limp home during sleep the device will therefore wake up and enter the limp home mode. During Limp home mode any SPI transmission will receive a TER flag. After limp home operation all registers are reset and the device enters in sleep mode following low logic RST state, or returns to ON state (all channels OFF with diagnostic currents active). Next SPI transmission will receive a TER Flag. Input IN0 IN1 IN2 IN3 Table 3 Routing during limp home mode controlled Output OUT0 OUT1 OUT2 OUT3 Datasheet 12 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Power Stages 6 Power Stages The TLE7233G is a four channel low-side relay switch. The power stages are made of N-channel vertical power MOSFET transistors. 6.1 Input Circuit The TLE7233G has four input pins, that can be configured to be used for control of the output stages. The INn parameter of the SPI provide the following operation modes: • • • • channel is in off mode without diagnosis (if all channels are programmed to this mode, the device goes into idle mode) channel is switched according to signal level at input pin INx channel is switched on channel is switched off with active diagnosis Figure 5 shows the input circuit of TLE7233G. IN IIN InputStage.emf Figure 4 Input signal conditioning circuit on all input and limp home pins Datasheet 13 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Power Stages OFF IN0 Channel 0 & IN0 ON OFF INx0 OFF LHI D0 IN1 Channel 1 & IN1 ON OFF INx1 OFF IN2 LHI D1 Channel 2 & IN2 ON OFF INx2 OFF IN3 LHI D2 Channel 3 & IN3 ON OFF INx3 LHI D3 InputLogic_GS .emf Figure 5 Input Multiplexer The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects the input circuit against ESD pulses. After power-on reset, the device enters idle mode. 6.2 Inductive Output Clamp When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential, because the inductance intends to continue driving the current. The voltage clamping is necessary to prevent destruction of the device, see Figure 6 for details. Nevertheless, the maximum allowed load inductance is limited. Datasheet 14 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Power Stages V bat ID VDS L, RL OUT VDS(CL) GND OutputClamp .emf Figure 6 Output Clamp Implementation Maximum Load Inductance During demagnetization of inductive loads, energy has to be dissipated in the TLE7233G. This energy can be calculated with following equation: V bat – V DS(CL)   RL ⋅ IL L E = V DS(CL) ⋅ ----------------------------------- ⋅ ln 1 – -----------------------------------  + I L ⋅ -----RL RL V bat – V DS(CL)   Following equation simplifies under the assumption of RL = 0:  V bat 2 1 E = -- LI L ⋅ 1 – -----------------------------------  2 V bat – V DS(CL)   The maximum energy, which is converted into heat, is limited by the thermal design of the component. 6.3 Timing Diagrams The power transistors are switched on and off with a dedicated slope via the IN bits of the serial peripheral interface SPI. The switching times tON and tOFF are designed equally. CS SPI: ON tON SPI: OFF tOFF t VDS 80% 20% t SwitchOn.emf Figure 7 Switching a Resistive Load In input mode, a high signal at the input pin is equivalent to a SPI ON command and a low signal to SPI OFF command respectively. Please refer to Section 9.3 for details on operation modes. The listed switching times are not valid, when switching to or from stand-by mode. Datasheet 15 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Power Stages 6.4 Electrical Characteristics Power Stages VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C All voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C Pos. Parameter Symbol Min. Power Supply 6.4.1 6.4.2 Digital supply voltage Digital supply current all channels ON Limit Values Typ. – – Max. 5.5 0.5 V mA – Unit Conditions VDD IDD(ON) 3. 0 – 6.4.3 Digital supply idle current IDD(idle) – – 20 20 40 µA 6.4.4 Digital supply sleep current IDD(sleep) – – 5 5 20 µA VDD = VDDA = 5 V VRST = VCS = VDD VSCLK = 0 V VIN = 0 V fSCLK = 0 Hz VRST = VCS = high T j = 25 ° C 1 ) T j = 85 ° C 1 ) Tj = 150 °C VRST = 0 V T j = 25 ° C 1 ) T j = 85 ° C 1 ) Tj = 150 °C – – – 6.4.5 6.4.6 6.4.7 6.4.8 Digital power-on reset threshold voltage Analog supply voltage ON Analog supply idle current VDD(PO) – 4.5 – – – – – – 3.0 5.5 5 V V mA µA VDDA Analog supply current all channels IDDA(ON) IDDA(idle) 25 6.4.9 Analog supply sleep current Idd(sleep) – – 5 5 20 µA VCS = VDD VSI = 0 V VSCLK = 0 V T j = 25 ° C 1 ) T j = 85 ° C 1 ) Tj = 150 °C VCS = VDD VRST = 0 V T j = 25 ° C 1 ) T j = 85 ° C 1 ) Tj = 150 °C – 6.4.10 Analog power-on reset threshold voltage On-State resistance per channel VDDA(PO) – – 4.5 V Output Characteristics 6.4.11 RDS(ON) – 1.0 2.0 2.2 – Ω IL = 250 mA Tj = 25 °C 1) Tj = 150 °C 2) 6.4.12 Nominal load current ID(nom) 390 415 mA Datasheet 16 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Power Stages VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C All voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C Pos. 6.4.13 Parameter Output leakage current (per channel) Symbol Min. ID(OFF) Limit Values Typ. – 1 2 5 Max. – Unit µA Conditions VDS = 13.5 V Tj = 25 °C 1) Tj = 85 °C 1) Tj = 150 °C 3) 6.4.14 6.4.15 6.4.16 6.4.17 6.4.18 6.4.19 6.4.20 6.4.21 6.4.22 Timings 6.4.23 6.4.24 6.4.25 Output clamping voltage L level of pin IN & LHI H level of pin IN & LHI L-input pull-down current through pin H-input pull-down current through pin L level of pin RST H level of pin RST L-input pull-down current through pin RST H-input pull-down current through pin RST Sleep wake-up time Reset duration Turn-on time VDS = 20% Vbat Turn-off time VDS = 80% Vbb VDS(CL) VIN(L) VIN(H) IIN(L) IIN(H) VRST(L) VRST(H) IRST(L) IRST(H) 41 0 2.2 3 10 0 0.4* – – – 12 40 – – 12 40 52 0.9 5.5 80 80 0.2* V V V µA µA Input Pin Characteristics – – VDD = 5 V 1) VIN = 0.6 V VDD = 5 V VIN = 5 V – – µA µA VDD 3 10 VDD VDD 80 80 VDD = 5 V 1) VRST = 0.6 V VDD = 5 V VRST = 5 V – – Vbb = 13.5 V IDS = 250 mA, resistive load Vbb = 13.5 V IDS = 250 mA, resistive load twu(sleep) tRST(L) tON – 1 – – – – 200 – 60 µs µs µs 6.4.26 tOFF – – 60 µs 1) Not subject to production test, specified by design 2) calculated value based on following parameters: all channels on with equal load current, RDS(ON) = RDS(ON,150°C) , 3) maximum value is increasing in sleep mode Ta = 85 °C, Tj,max = 150 °C, Rth = RthJA(typ) Datasheet 17 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Protection Functions 7 Protection Functions Note: The device provides embedded protective functions. Integrated protection functions are designed to prevent IC destruction under fault conditions described in this datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 7.1 Over Load Protection The TLE7233G is protected against over load or short circuit of the load. After time tOFF(OVL), the over loaded channel n switches off and therefore the corresponding diagnostics flag Dn is set. The channel can be switched on after clearing the diagnostics flag. Please refer to Figure 8 for details. IN tOFF(OVL) t ID0 ID0(OVL) IN0 = 01 b D0 = 0 b D0 = 1b IN0 = 00 b D0 = 0 b IN0 = 01 b t OverLoad .emf Figure 8 Shut Down at Over Load 7.2 Over Temperature Protection A temperature sensor for each channel causes an overheated channel n to switch off to prevent destruction. Then the according diagnostics flag Dn is set. The channel can be switched on after clearing the diagnosis flag. Please refer to Section 8 for information on diagnostics features. 7.3 Reverse Polarity Protection In case of reverse polarity, the intrinsic body diode of the power transistor causes increased power dissipation. The reverse current through the intrinsic body diode of the power transistor has to be limited by the connected load. The VDD and VDDA supply pins must be externally protected against reverse polarity. The over temperature and over load protection are not active during reverse polarity. Datasheet 18 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Protection Functions 7.4 Electrical Characteristics Protection VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C All voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C Pos. Parameter Symbol Min. Over Load Protection 7.4.1 7.4.2 7.4.3 7.4.4 Over load detection current Over load shut-down delay time Thermal shut down temperature Thermal hysteresis ID(OVL) tOFF(OVL) Tj(SC) Limit Values Typ. Max. 0.95 60 1701) 10 Unit Conditions 0.5 5 150 A µs °C K – – – 1) Over Temperature Protection ∆ Tj 1) Not subject to production test, specified by design Datasheet 19 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Diagnostic Features 8 Diagnostic Features The SPI of TLE7233G provides diagnosis information about the device and about the load. The diagnosis information of the protective functions of channel n is latched in the diagnosis flag Dn. The open load diagnosis of channel n is latched in the diagnosis flag OLn. Both flags are cleared by INn = 00B and the diagnosis current ID(PD), which is a small pull down current, is disabled. Following table shows possible failure modes and the according protective and diagnostic action. j Failure Mode Comment Open Load Diagnosis, when channel n is switched on: or short circuit to GND INn = 01B: if input pin is high: none INn = 10B: none Diagnosis, when channel n is switched off: INn = 00B: none, diagnosis flags are cleared and the diagnosis current is switched off INn = 01B: if input pin is low, according to voltage at the output pin, the flag OLn is set after time td(OL) INn = 11B: according to voltage level at the output pin, flags OLn are set after time td(OL) Over temperature When over temperature occurs, the affected channel n is switched off. The according diagnosis flag Dn is set. The diagnosis flags are latched until they have been cleared by INn = 00B. The over temperature detection is active in ON-state as well as OFF-state. When over load is detected at channel n, the affected channel is switched off after time tOFF(OVL) and the dedicated diagnosis flag Dn is set. The diagnosis flags are latched until they have been cleared by INn = 00B. Over Load (Short Circuit) 8.1 Open Load Diagnosis timing The TLE7233G offers a open load diagnosis for each channel in OFF mode. The time td(fault) is applied to filter short time events. Open Load occures here Open Load occures here IN t VDS V DS (OL) t d(fault) t IN t V DS VDS (OL) td(fault) t OLn = 1b OL n = 1b OpenLoad .emf Figure 9 Open Load timing Datasheet 20 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Diagnostic Features 8.2 Electrical Characteristics Diagnostic VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C All voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C Pos. Parameter Symbol Min. OFF State Diagnosis 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 Open load detection threshold voltage VDS(OL) Limit Values Typ. Max. 2.5 100 30 0.5 5 200 0.95 60 Unit Conditions 1.0 V µA µs Α µs – VDS = 13.5 V Output pull-down diagnosis current ID(PD) per channel Open load diagnosis delay time Over load detection current Over load detection delay time td(OL) ID(OVL) tOFF(OVL) – – – ON State Diagnosis Datasheet 21 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Serial Peripheral Interface (SPI) 9 Serial Peripheral Interface (SPI) The diagnosis and control interface is based on a serial peripheral interface (SPI). The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability. SO SI CS SCLK time CS MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB SPI.emf Figure 10 Serial Peripheral Interface The SPI protocol is described in Section 9.3. It is reset to the default values after power-on reset. 9.1 SPI Signal Description CS - Chip Select: The system micro controller selects the TLE7233G by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: • • The diagnosis information is transferred into the shift register. SO changes from high impedance state to high or low state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration, a high signal indicates a faulty transmission. The transmission error flag is set after any kind of reset, so a reset between two SPI commands is indicated. For details, please refer to Figure 11. This information stays available to the first rising edge of SCLK. Datasheet 22 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Serial Peripheral Interface (SPI) TER SI OR 1 0 SO SI CS SCLK S SPI SO S TER.emf Figure 11 Transmission Error Flag on SO Line CS Low to High transition: Data from shift register is transferred into the input matrix register only, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK signals have been detected. SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. Please refer to Section 9.3 for further information. SO - Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.3 for further information. 9.2 Daisy Chain Capability The SPI of TLE7233G provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 12), which builds a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK, which is connected to the SCLK line of each device in the chain. Datasheet 23 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Serial Peripheral Interface (SPI) device 1 MO SI SPI SO SI device 2 SPI SO SI device 3 SPI SO CS CS SCLK CS MI MCS MCLK Figure 12 Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must transit from low to high to make the device accept the transferred data. In daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. When using three devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the MCS line must transit from low to high (see Figure 13). MI MO MCS MCLK time SO device 3 SI device 3 SO device 2 SI device 2 SO device 1 SI device 1 SCLK SPI_DasyChain.emf SCLK SPI_DasyChain2.emf Figure 13 Data Transfer in Daisy Chain Configuration 9.3 SPI Protocol The SPI protocol of the TLE7233G provides two registers. The input register and the diagnosis register. The diagnosis register contains four pairs of diagnosis flags, the input register contains the input multiplexer configuration. After power-on reset, all register bits are cleared to 0. SI 7 IN3 6 5 IN2 4 3 IN1 2 1 IN0 0 Datasheet 24 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Serial Peripheral Interface (SPI) Field INn (n = 3-0) Bits 7:6, 5:4, 3:2, 1:0 Type Description W Input Register Channel n 00B Stand-by Mode: Fast channel switched off. Diagnosis flags are cleared. Diagnosis current is disabled. 01B Input Direct drive mode: Channel is switched according to signal at corresponding input pin. Diagnosis current is enabled in OFF-state. See Figure 5 for details. 10B ON Mode: Channel is switched on. Diagnosis current is enabled. 11B OFF Mode: Channel is switched off. Diagnosis current is enabled. Datasheet 25 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Serial Peripheral Interface (SPI) SO CS1) TER 7 OL3 6 D3 5 OL2 4 D2 3 OL1 2 D1 Reset Value: 100H 1 OL0 0 D0 1) This bit is valid between CS hi -> lo and first SCLK lo -> hi transition. Field TER Bits CS Type Description R Transmission Error 0 Previous transmission was successful (modulo 8 clocks received). 1 Previous transmission failed or first transmission after reset. Open Load Flag of channel n 0 Normal operation. 1 Open load has occurred in OFF state. Diagnosis Flag of channel n 0 Normal operation. 1 Over load or over temperature switch off has occurred in ON state. OLn (n = 3-0) Dn (n = 3-0) 7, 5, 3, R 1 6, 4, 2, R 0 9.4 Timing Diagrams tCS (lead) tCS (lag) tS C LK (P ) tS CLK (H) tS CLK (L) 0.7Vdd 0.2Vdd tCS (td) 0.7Vdd 0.2Vdd CS SCLK t S I(s u) tS I(h) SI tS O(en) tS O(v ) tS O(dis ) 0.7Vdd 0.2Vdd SO 0.7Vdd 0.2Vdd SPI Timing.emf Figure 14 Timing Diagram Datasheet 26 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Serial Peripheral Interface (SPI) 9.5 Electrical Characteristics SPI VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C All voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C Pos. Parameter Symbol Min. Input Characteristics (CS, SCLK, SI) 9.5.1 L level of pin CS SCLK SI H level of pin CS SCLK SI 0 – 0.2* – Limit Values Typ. Max. Unit Conditions VCS(L) VSCLK(L) VSI(L) 0.5*VDD – VDD 9.5.2 9.5.3 9.5.4 9.5.5 VCS(H) VSCLK(H) VSI(H) L-input pull-up current through CS ICS(L) H-input pull-up current through CS ICS(H) VDD – 5 3 3 17 15 12 40 40 80 µA µA µA VCS = 0 V 1) VCS = 2 V L-input pull-down current through pin SCLK SI H-input pull-down current through pin SCLK SI L level output voltage H level output voltage Output tristate leakage current Serial clock frequency Serial clock period Serial clock high time Serial clock low time Enable lead time (falling CS to rising SCLK) Enable lag time (falling SCLK to rising CS) Transfer delay time (rising CS to falling CS) 1) ISCLK(L) ISI(L) 10 40 80 µA VSCLK = 0.6 V VSI = 0.6 V 9.5.6 ISCLK(H) ISI(H) VSO(L) VSO(H) ISO(OFF) fSCLK tSCLK(P) tSCLK(H) tSCLK(L) tCS(lead) tCS(lag) tCS(td) 0 – – – – – – – – – – – – 0.4 V VSCLK = 5 V VSI = 5 V ISO = -2 mA ISO = 1.5 mA Output Characteristics (SO) 9.5.7 9.5.8 9.5.9 Timings 9.5.10 9.5.11 9.5.12 9.5.13 9.5.14 9.5.15 9.5.16 9.5.17 9.5.18 0 200 50 50 250 250 250 20 20 27 5 – – – – – – – – MHz ns ns ns ns ns ns ns ns – – – – – – – – – Rev. 1.0, 2008-02-28 VDD0.5 V -10 VDD 10 µA VCS = VDD Data setup time (required time SI to tSI(su) falling SCLK) Data hold time (falling SCLK to SI) tSI(h) Datasheet SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Serial Peripheral Interface (SPI) VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C All voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C Pos. 9.5.19 9.5.20 9.5.21 Parameter Output enable time (falling CS to SO valid) Output disable time (rising CS to SO tri-state) Output data valid time with capacitive load Symbol Min. tSO(en) tSO(dis) tSO(v) Limit Values Typ. – – – Max. 200 200 100 – – – Unit ns ns ns Conditions CL = 50 pF 1) CL = 50 pF 1) CL = 50 pF 1) 1) Not subject to production test, specified by design. Datasheet 28 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Application Information 10 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 15 shows a simplified application circuit. VDDA and VDD need to be reverse protected. Also the Resistors in the digital pins are for reverse polarity protection. Vbb VDDA C1 Vdda Vdd VDD C2 RST R10 C3 Discrete Limp home or PWM signal circuit Watch dog IN3 R9 IN2 IN1 R7 IN0 R6 LHI R5 CS R4 SCLK SPI uC R3 SI R2 SO R1 GND OUT3 OUT2 TLE 7233G R8 Loads OUT0 OUT1 Application_GS.emf Figure 15 Application Diagram Note: This is a very simplified example of an application circuit. The function must be verified in the real application. C1,C2,C3 are recommended to be 4.7nF and all Resistors can be 1kOhm. For further information you may contact http://www.infineon.com/ Datasheet 29 Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Package Outlines 11 Package Outlines 0.35 x 45˚ 0.175 ±0.07 3.9 ±0.11) 1.75 MAX. (1.47) C 0.19 +0.06 8˚ MAX. 8˚ MAX. 0˚...8˚ 0.65 0.25 ±0.05 2) 0˚...8˚ B 0.1 B Seating Plane 0.64 ±0.25 6 ±0.2 0.2 8˚ MAX. M 0.17 M C A B 24x C 24 13 1 12 8.65 ±0.11) Index Marking A 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.13 max. Figure 16 PG-SSOP-24-5 (Plastic Green Shrink Small Outline Package) PG-SSOP-24-5, -6 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Datasheet 30 Dimensions in mm Rev. 1.0, 2008-02-28 SPI Driver for Enhanced Relay Control SPIDER - TLE7233G Revision History 12 Version Rev. 1.0 Revision History Date 2008-02-28 Changes initial released Datasheet Datasheet 31 Rev. 1.0, 2008-02-28 Edition 2008-02-28 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.